mirror of
https://github.com/WeActStudio/ArduinoCore-AT32F4.git
synced 2026-05-21 09:22:01 +00:00
97 lines
2.9 KiB
C
97 lines
2.9 KiB
C
/*
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* MIT License
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* Copyright (c) 2017 - 2022 _VIFEXTech
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "wdg.h"
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uint32_t WDG_Init(uint32_t timeout)
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{
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uint32_t reload_value;
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uint32_t real_timeout = 0;
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uint16_t division;
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static const uint8_t div_map[] =
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{
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WDT_CLK_DIV_4, /*!< wdt clock divider value is 4 */
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WDT_CLK_DIV_8, /*!< wdt clock divider value is 8 */
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WDT_CLK_DIV_16, /*!< wdt clock divider value is 16 */
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WDT_CLK_DIV_32, /*!< wdt clock divider value is 32 */
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WDT_CLK_DIV_64, /*!< wdt clock divider value is 64 */
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WDT_CLK_DIV_128, /*!< wdt clock divider value is 128 */
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WDT_CLK_DIV_256 /*!< wdt clock divider value is 256 */
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};
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/* set reload value
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* lick_freq = 40000
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* timeout = reload_value * divider / lick_freq * 1000 (ms)
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* timeout / divider * lick_freq / 1000 = reload_value
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*/
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const uint32_t lick_freq = 40000;
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for(int i = 0; i < sizeof(div_map) / sizeof(uint8_t); i++)
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{
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int div = 4 << i;
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reload_value = (uint64_t)timeout * lick_freq / div / 1000;
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if(reload_value <= 0xFFF)
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{
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real_timeout = (uint64_t)reload_value * div * 1000 / lick_freq;
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division = div_map[i];
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break;
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}
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}
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if(reload_value > 0xFFF)
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{
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return 0;
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}
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if(crm_flag_get(CRM_WDT_RESET_FLAG) != RESET)
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{
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/* reset from wdt */
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crm_flag_clear(CRM_WDT_RESET_FLAG);
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}
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/* disable register write protection */
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wdt_register_write_enable(TRUE);
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/* set the wdt divider value */
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wdt_divider_set(division);
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/* Set counter reload value */
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wdt_reload_value_set(3000 - 1);
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/* Reload IWDG counter */
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wdt_counter_reload();
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/* Enable IWDG (the LSI oscillator will be enabled by hardware) */
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wdt_enable();
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return real_timeout;
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}
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void WDG_ReloadCounter(void)
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{
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wdt_counter_reload();
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}
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