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https://github.com/WeActStudio/ArduinoCore-AT32F4.git
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support linux system
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ZYQ-FEIYUE
430
cores/arduino/SPI.cpp
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430
cores/arduino/SPI.cpp
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/*
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* MIT License
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* Copyright (c) 2017 - 2022 _VIFEXTech
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "SPI.h"
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#define SPI1_CLOCK (F_CPU)
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#define SPI2_CLOCK (F_CPU)
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#define SPI3_CLOCK (F_CPU)
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SPIClass::SPIClass(spi_type* spix)
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: SPIx(spix)
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, SPI_Clock(0)
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{
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memset(&spi_init_struct, 0, sizeof(spi_init_struct));
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}
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void SPIClass::SPI_Settings(
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spi_master_slave_mode_type master_slave_mode,
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spi_frame_bit_num_type frame_bit_num,
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uint16_t SPI_MODEx,
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spi_cs_mode_type cs_mode,
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spi_mclk_freq_div_type mclk_freq_div,
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spi_first_bit_type first_bit)
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{
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spi_clock_polarity_type clock_polarity;
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spi_clock_phase_type clock_phase;
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spi_enable(SPIx, FALSE);
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switch(SPI_MODEx)
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{
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case 0:
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clock_polarity = SPI_CLOCK_POLARITY_LOW;
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clock_phase = SPI_CLOCK_PHASE_1EDGE;
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break;
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case 1:
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clock_polarity = SPI_CLOCK_POLARITY_LOW;
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clock_phase = SPI_CLOCK_PHASE_2EDGE;
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break;
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case 2:
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clock_polarity = SPI_CLOCK_POLARITY_HIGH;
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clock_phase = SPI_CLOCK_PHASE_1EDGE;
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break;
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case 3:
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clock_polarity = SPI_CLOCK_POLARITY_HIGH;
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clock_phase = SPI_CLOCK_PHASE_2EDGE;
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break;
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default:
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return;
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}
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spi_default_para_init(&spi_init_struct);
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spi_init_struct.transmission_mode = SPI_TRANSMIT_FULL_DUPLEX;
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spi_init_struct.master_slave_mode = master_slave_mode;
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spi_init_struct.frame_bit_num = frame_bit_num;
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spi_init_struct.clock_polarity = clock_polarity;
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spi_init_struct.clock_phase = clock_phase;
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spi_init_struct.cs_mode_selection = cs_mode;
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spi_init_struct.mclk_freq_division = mclk_freq_div;
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spi_init_struct.first_bit_transmission = first_bit;
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spi_init(SPIx, &spi_init_struct);
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spi_enable(SPIx, TRUE);
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}
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void SPIClass::begin(void)
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{
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spi_i2s_reset(SPIx);
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if(SPIx == SPI1)
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{
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SPI_Clock = SPI1_CLOCK;
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crm_periph_clock_enable(CRM_SPI1_PERIPH_CLOCK, TRUE);
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pinMode(PA5, OUTPUT_AF_PP);
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pinMode(PA6, OUTPUT_AF_PP);
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pinMode(PA7, OUTPUT_AF_PP);
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}
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else if(SPIx == SPI2)
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{
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SPI_Clock = SPI2_CLOCK;
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crm_periph_clock_enable(CRM_SPI2_PERIPH_CLOCK, TRUE);
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pinMode(PB13, OUTPUT_AF_PP);
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pinMode(PB14, OUTPUT_AF_PP);
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pinMode(PB15, OUTPUT_AF_PP);
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}
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else if(SPIx == SPI3)
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{
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SPI_Clock = SPI3_CLOCK;
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crm_periph_clock_enable(CRM_SPI3_PERIPH_CLOCK, TRUE);
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pinMode(PB3, OUTPUT_AF_PP);
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pinMode(PB4, OUTPUT_AF_PP);
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pinMode(PB5, OUTPUT_AF_PP);
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}
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else
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{
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return;
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}
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SPI_Settings(
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SPI_MODE_MASTER,
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SPI_FRAME_8BIT,
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SPI_MODE0,
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SPI_CS_SOFTWARE_MODE,
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SPI_MCLK_DIV_8,
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SPI_FIRST_BIT_MSB
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);
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}
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void SPIClass::begin(uint32_t clock, uint16_t dataOrder, uint16_t dataMode)
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{
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begin();
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setClock(clock);
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setBitOrder(dataOrder);
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setDataMode(dataMode);
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spi_enable(SPIx, TRUE);
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}
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void SPIClass::begin(SPISettings settings)
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{
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begin();
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setClock(settings.clock);
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setBitOrder(settings.bitOrder);
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setDataMode(settings.dataMode);
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spi_enable(SPIx, TRUE);
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}
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void SPIClass::beginSlave(void)
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{
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begin();
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SPI_Settings(
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SPI_MODE_SLAVE,
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SPI_FRAME_8BIT,
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SPI_MODE0,
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SPI_CS_SOFTWARE_MODE,
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SPI_MCLK_DIV_16,
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SPI_FIRST_BIT_MSB
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);
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spi_enable(SPIx, TRUE);
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}
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void SPIClass::end(void)
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{
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spi_enable(SPIx, FALSE);
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}
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void SPIClass::setClock(uint32_t clock)
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{
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if(clock == 0)
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{
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return;
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}
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static const spi_mclk_freq_div_type mclk_freq_div_map[] =
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{
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SPI_MCLK_DIV_2,
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SPI_MCLK_DIV_2,
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SPI_MCLK_DIV_4,
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SPI_MCLK_DIV_8,
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SPI_MCLK_DIV_16,
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SPI_MCLK_DIV_32,
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SPI_MCLK_DIV_64,
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SPI_MCLK_DIV_128,
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SPI_MCLK_DIV_256,
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SPI_MCLK_DIV_512,
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SPI_MCLK_DIV_1024,
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};
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const uint8_t mapSize = sizeof(mclk_freq_div_map) / sizeof(mclk_freq_div_map[0]);
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uint32_t clockDiv = SPI_Clock / clock;
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uint8_t mapIndex = 0;
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while(clockDiv > 1)
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{
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clockDiv = clockDiv >> 1;
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mapIndex++;
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}
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if(mapIndex >= mapSize)
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{
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mapIndex = mapSize - 1;
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}
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spi_init_struct.mclk_freq_division = mclk_freq_div_map[mapIndex];
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spi_init(SPIx, &spi_init_struct);
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spi_enable(SPIx, TRUE);
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}
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void SPIClass::setClockDivider(uint32_t Div)
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{
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if(Div == 0)
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{
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Div = 1;
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}
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#if SPI_CLASS_AVR_COMPATIBILITY_MODE
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setClock(16000000 / Div); // AVR:16MHz
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#else
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setClock(SPI_Clock / Div);
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#endif
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}
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void SPIClass::setBitOrder(uint16_t bitOrder)
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{
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spi_init_struct.first_bit_transmission = (bitOrder == MSBFIRST) ? SPI_FIRST_BIT_MSB : SPI_FIRST_BIT_LSB;
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spi_init(SPIx, &spi_init_struct);
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spi_enable(SPIx, TRUE);
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}
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/* Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
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* Input parameter should be SPI_CR1_DFF set to 0 or 1 on a 32bit word.
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*
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*/
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void SPIClass::setDataSize(uint32_t datasize)
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{
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spi_init_struct.frame_bit_num = (spi_frame_bit_num_type)datasize;
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spi_init(SPIx, &spi_init_struct);
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spi_enable(SPIx, TRUE);
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}
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void SPIClass::setDataMode(uint8_t dataMode)
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{
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/* Notes. As far as I can tell, the AVR numbers for dataMode appear to match the numbers required by the STM32
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From the AVR doc http://www.atmel.com/images/doc2585.pdf section 2.4
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SPI Mode CPOL CPHA Shift SCK-edge Capture SCK-edge
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0 0 0 Falling Rising
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1 0 1 Rising Falling
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2 1 0 Rising Falling
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3 1 1 Falling Rising
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On the STM32 it appears to be
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bit 1 - CPOL : Clock polarity
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(This bit should not be changed when communication is ongoing)
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0 : CLK to 0 when idle
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1 : CLK to 1 when idle
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bit 0 - CPHA : Clock phase
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(This bit should not be changed when communication is ongoing)
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0 : The first clock transition is the first data capture edge
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1 : The second clock transition is the first data capture edge
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If someone finds this is not the case or sees a logic error with this let me know ;-)
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*/
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spi_clock_polarity_type clock_polarity;
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spi_clock_phase_type clock_phase;
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spi_enable(SPIx, FALSE);
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switch(dataMode)
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{
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case 0:
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clock_polarity = SPI_CLOCK_POLARITY_LOW;
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clock_phase = SPI_CLOCK_PHASE_1EDGE;
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break;
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case 1:
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clock_polarity = SPI_CLOCK_POLARITY_LOW;
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clock_phase = SPI_CLOCK_PHASE_2EDGE;
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break;
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case 2:
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clock_polarity = SPI_CLOCK_POLARITY_HIGH;
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clock_phase = SPI_CLOCK_PHASE_1EDGE;
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break;
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case 3:
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clock_polarity = SPI_CLOCK_POLARITY_HIGH;
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clock_phase = SPI_CLOCK_PHASE_2EDGE;
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break;
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default:
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return;
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}
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spi_init_struct.clock_polarity = clock_polarity;
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spi_init_struct.clock_phase = clock_phase;
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spi_init(SPIx, &spi_init_struct);
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spi_enable(SPIx, TRUE);
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}
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void SPIClass::beginTransaction(SPISettings settings)
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{
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SPISettings(settings.clock, settings.bitOrder, settings.dataMode);
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setClock(settings.clock);
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setBitOrder(settings.bitOrder);
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setDataMode(settings.dataMode);
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setDataSize(settings.dataSize);
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spi_enable(SPIx, TRUE);
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}
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void SPIClass::beginTransactionSlave(void)
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{
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beginSlave();
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}
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void SPIClass::endTransaction(void)
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{
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spi_enable(SPIx, FALSE);
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}
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uint16_t SPIClass::read(void)
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{
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SPI_I2S_WAIT_RX(SPIx);
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return (uint16_t)(SPI_I2S_RXDATA(SPIx));
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}
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void SPIClass::read(uint8_t *buf, uint32_t len)
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{
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if (len == 0)
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return;
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SPI_I2S_RXDATA_VOLATILE(SPIx);
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SPI_I2S_TXDATA(SPIx, 0x00FF);
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while((--len))
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{
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SPI_I2S_WAIT_TX(SPIx);
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noInterrupts();
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SPI_I2S_TXDATA(SPIx, 0x00FF);
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SPI_I2S_WAIT_RX(SPIx);
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*buf++ = (uint8_t)SPI_I2S_RXDATA(SPIx);
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interrupts();
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}
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SPI_I2S_WAIT_RX(SPIx);
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*buf++ = (uint8_t)SPI_I2S_RXDATA(SPIx);
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}
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void SPIClass::write(uint16_t data)
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{
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SPI_I2S_TXDATA(SPIx, data);
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SPI_I2S_WAIT_TX(SPIx);
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SPI_I2S_WAIT_BUSY(SPIx);
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}
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void SPIClass::write(uint16_t data, uint32_t n)
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{
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while ((n--) > 0)
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{
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SPI_I2S_TXDATA(SPIx, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
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SPI_I2S_WAIT_TX(SPIx); // wait till Tx empty
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}
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SPI_I2S_WAIT_BUSY(SPIx); // wait until BSY=0 before returning
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}
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void SPIClass::write(const uint8_t *data, uint32_t length)
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{
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while (length--)
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{
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SPI_I2S_WAIT_TX(SPIx);
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SPI_I2S_TXDATA(SPIx, *data++);
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}
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SPI_I2S_WAIT_TX(SPIx);
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SPI_I2S_WAIT_BUSY(SPIx);
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}
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void SPIClass::write(const uint16_t *data, uint32_t length)
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{
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while (length--)
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{
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SPI_I2S_WAIT_TX(SPIx);
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SPI_I2S_TXDATA(SPIx, *data++);
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}
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SPI_I2S_WAIT_TX(SPIx);
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SPI_I2S_WAIT_BUSY(SPIx);
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}
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uint8_t SPIClass::transfer(uint8_t wr_data) const
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{
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SPI_I2S_RXDATA_VOLATILE(SPIx);
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SPI_I2S_TXDATA(SPIx, wr_data);
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SPI_I2S_WAIT_TX(SPIx);
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SPI_I2S_WAIT_BUSY(SPIx);
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return (uint8_t)SPI_I2S_RXDATA(SPIx);
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}
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uint16_t SPIClass::transfer16(uint16_t wr_data) const
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{
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SPI_I2S_RXDATA_VOLATILE(SPIx);
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SPI_I2S_TXDATA(SPIx, wr_data);
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SPI_I2S_WAIT_TX(SPIx);
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SPI_I2S_WAIT_BUSY(SPIx);
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return (uint16_t)SPI_I2S_RXDATA(SPIx);
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}
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uint8_t SPIClass::send(uint8_t data)
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{
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this->write(data);
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return 1;
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}
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uint8_t SPIClass::send(uint8_t *buf, uint32_t len)
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{
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this->write(buf, len);
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return len;
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}
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uint8_t SPIClass::recv(void)
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{
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return this->read();
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}
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#if SPI_CLASS_1_ENABLE
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SPIClass SPI(SPI_CLASS_1_SPI);
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#endif
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#if SPI_CLASS_2_ENABLE
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SPIClass SPI_2(SPI_CLASS_2_SPI);
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#endif
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#if SPI_CLASS_3_ENABLE
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SPIClass SPI_3(SPI_CLASS_3_SPI);
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#endif
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