init

BSP/at32_board.c

@@ -0,0 +1,420 @@
+/**
+  **************************************************************************
+  * File   : at32_board.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : 1. Set of firmware functions to manage Leds, push-button and COM ports.
+  *          2. initialize Delay Function and USB
+  **************************************************************************
+  */
+
+#include "at32_board.h"
+#include "stdio.h"
+
+#ifdef __cplusplus
+namespace std
+{
+  extern "C" {
+#endif
+
+/* Suport printf function, useMicroLib is unnecessary */
+#ifdef __CC_ARM
+  #pragma import(__use_no_semihosting)
+  struct __FILE
+  {
+    int handle;
+  };
+  
+  FILE __stdout;
+  
+  void _sys_exit(int x)
+  {
+    x = x;
+  }
+#endif
+
+#ifdef __GNUC__
+  /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
+     set to 'Yes') calls __io_putchar() */
+  #define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
+// #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
+#else
+  #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
+#endif /* __GNUC__ */
+
+/**
+  * @brief  Retargets the C library printf function to the USART.
+  * @param  None
+  * @retval None
+  */
+PUTCHAR_PROTOTYPE
+{  
+  USART_SendData(AT32_PRINT_UART, ch);
+  while ( USART_GetFlagStatus(AT32_PRINT_UART, USART_FLAG_TRAC) == RESET );    
+  return ch;
+}
+
+#ifdef __cplusplus
+  } /* extern "C" */
+} /* namespace */
+#endif
+
+/*delay macros*/
+#define STEP_DELAY_MS	50
+  
+/*AT-START LED resouce array*/
+GPIO_Type *LED_GPIO_PORT[LED_NUM] = {LED1_GPIO, LED2_GPIO, LED3_GPIO, LED4_GPIO};
+uint16_t LED_GPIO_PIN[LED_NUM]    = {LED1_PIN, LED2_PIN, LED3_PIN, LED4_PIN};
+uint32_t LED_GPIO_RCC_CLK[LED_NUM] = {LED1_GPIO_RCC_CLK, LED2_GPIO_RCC_CLK, LED3_GPIO_RCC_CLK, LED4_GPIO_RCC_CLK};
+
+/*AT-START Button resouce arry*/
+GPIO_Type *BUTTON_GPIO_PORT[BUTTON_NUM] = {BUTTON_WAKEUP_GPIO, BUTTON_USER_KEY_GPIO};
+uint16_t BUTTON_GPIO_PIN[BUTTON_NUM]    = {BUTTON_WAKEUP_PIN, BUTTON_USER_KEY_PIN};
+uint32_t BUTTON_GPIO_RCC_CLK [BUTTON_NUM] = {BUTTON_WAKEUP_RCC_CLK, BUTTON_USER_KEY_RCC_CLK};
+
+/*delay variable*/
+static __IO uint32_t fac_us;
+static __IO uint32_t fac_ms;
+ 
+/**
+  * @brief  Board initialize interface 
+  *         init LED and BUTTON
+  * @param  None
+  * @retval None
+  */
+void AT32_Board_Init()
+{
+  /*initialize Delay Function*/
+  Delay_init();
+
+  /*Configure LED in AT_START_BOARD*/
+  AT32_LEDn_Init(LED2);
+  AT32_LEDn_Init(LED3);
+  AT32_LEDn_Init(LED4);
+  AT32_LEDn_OFF(LED2);
+  AT32_LEDn_OFF(LED3);
+  AT32_LEDn_OFF(LED4);
+
+  /*Configure Button in AT_START_BOARD*/
+  AT32_BUTTON_Init(BUTTON_WAKEUP); /*PA0*/   
+  AT32_BUTTON_Init(BUTTON_USER_KEY); /*PC13*/
+}
+
+/**
+  * @brief  USB GPIO initialize
+  *         USB use DP->PA12, DM->PA11    
+  * @param  None
+  * @retval None
+  */
+void AT32_USB_GPIO_init()
+{
+  GPIO_InitType GPIO_InitStructure;
+  /* Enable the USB Clock*/
+  RCC_APB2PeriphClockCmd(USB_GPIO_RCC_CLK, ENABLE);
+
+  /*Configure DP, DM pin as GPIO_Mode_OUT_PP*/
+  GPIO_StructInit(&GPIO_InitStructure);
+  GPIO_InitStructure.GPIO_Pins  = USB_DP_PIN | USB_DM_PIN;
+#if !defined (AT32F421xx)
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT_PP;
+#else
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OutType = GPIO_OutType_PP;
+  GPIO_InitStructure.GPIO_Pull = GPIO_Pull_NOPULL;
+#endif
+  GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
+  GPIO_Init(USB_GPIO, &GPIO_InitStructure);
+  GPIO_ResetBits(USB_GPIO, USB_DP_PIN);
+}
+
+/**
+  * @brief  Configure Button GPIO   
+  * @param  Button: Specifies the Button to be configured.
+  * @retval None
+  */
+void AT32_BUTTON_Init(BUTTON_Type button)
+{
+  GPIO_InitType GPIO_InitStructure;
+
+  /*Enable the Button Clock*/
+#if defined (AT32F421xx)
+  RCC_AHBPeriphClockCmd(BUTTON_GPIO_RCC_CLK[button], ENABLE);
+#else
+  RCC_APB2PeriphClockCmd(BUTTON_GPIO_RCC_CLK[button], ENABLE);
+#endif
+
+  /*Configure Button pin as input with pull-up/pull-down*/
+  GPIO_StructInit(&GPIO_InitStructure);
+  GPIO_InitStructure.GPIO_Pins = BUTTON_GPIO_PIN[button];
+#if !defined (AT32F421xx)
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_PD;
+#else
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_Pull = GPIO_Pull_PD;
+#endif
+  GPIO_Init(BUTTON_GPIO_PORT[button], &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Returns the selected button state   
+  * @param  Button: Specifies the Button to be Checked
+  * @retval The Button GPIO Pin value
+  */
+uint8_t AT32_BUTTON_State(BUTTON_Type button)
+{
+  return GPIO_ReadInputDataBit(BUTTON_GPIO_PORT[button], BUTTON_GPIO_PIN[button]);
+}
+
+/**
+  * @brief  Returns which Button have press down 
+  * @param  None
+  * @retval The Button have press down
+  */
+BUTTON_Type AT32_BUTTON_Press()
+{
+  static uint8_t Pressed = 1;
+  /*Get Button state in AT_START board*/
+  if ((Pressed == 1) && ((AT32_BUTTON_State(BUTTON_WAKEUP) == Bit_SET ) || (AT32_BUTTON_State(BUTTON_USER_KEY) == Bit_SET )))
+  {
+    /*debounce*/
+    Pressed = 0;
+    Delay_ms(10);
+    if (AT32_BUTTON_State(BUTTON_WAKEUP) == Bit_SET)
+      return BUTTON_WAKEUP;
+    if (AT32_BUTTON_State(BUTTON_USER_KEY) == Bit_SET)
+      return BUTTON_USER_KEY;
+  }else if((AT32_BUTTON_State(BUTTON_USER_KEY) == Bit_RESET) && (AT32_BUTTON_State(BUTTON_WAKEUP) == Bit_RESET))
+  {
+    Pressed = 1;
+  }
+  return NO_BUTTON;
+}
+
+/**
+  * @brief  Configure LED GPIO   
+  * @param  led: Specifies the LED to be configured.
+  * @retval None
+  */
+void AT32_LEDn_Init(LED_Type led)
+{
+  GPIO_InitType GPIO_InitStructure;
+  /*Enable the LED Clock*/
+#if defined (AT32F421xx)
+  RCC_AHBPeriphClockCmd(LED_GPIO_RCC_CLK[led], ENABLE);
+#else
+  RCC_APB2PeriphClockCmd(LED_GPIO_RCC_CLK[led], ENABLE);
+#endif
+
+  /*Configure the LED pin as ouput push-pull*/
+  GPIO_StructInit(&GPIO_InitStructure);
+  GPIO_InitStructure.GPIO_Pins = LED_GPIO_PIN[led];				 
+#if !defined (AT32F421xx)
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT_PP;
+#else
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OutType = GPIO_OutType_PP;
+  GPIO_InitStructure.GPIO_Pull = GPIO_Pull_NOPULL;
+#endif 
+  GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;	
+  GPIO_Init(LED_GPIO_PORT[led], &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Turns selected LED On.
+  * @param  Led: Specifies the Led to be set on. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4  
+  * @retval None
+  */
+void AT32_LEDn_ON(LED_Type led)
+{
+  if ( led > (LED_NUM - 1))
+    return;
+  if ( LED_GPIO_PIN[led] )
+    LED_GPIO_PORT[led]->BRE = LED_GPIO_PIN[led];
+}
+
+/**
+  * @brief  Turns selected LED Off.
+  * @param  Led: Specifies the Led to be set off. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4 
+  * @retval None
+  */
+void AT32_LEDn_OFF(LED_Type led)
+{
+  if ( led > (LED_NUM - 1))
+    return;
+  if ( LED_GPIO_PIN[led] )
+    LED_GPIO_PORT[led]->BSRE = LED_GPIO_PIN[led];
+}
+
+/**
+  * @brief  Turns selected LED Tooggle.
+  * @param  Led: Specifies the Led to be set off. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4 
+  * @retval None
+  */
+void AT32_LEDn_Toggle(LED_Type led)
+{
+  if ( led > (LED_NUM - 1))
+    return;
+  if ( LED_GPIO_PIN[led] )
+    LED_GPIO_PORT[led]->OPTDT ^= LED_GPIO_PIN[led];
+}
+
+/**
+  * @brief  initialize UART1   
+  * @param  bound: UART BaudRate
+  * @retval None
+  */
+void UART_Print_Init(uint32_t bound)
+{
+  GPIO_InitType GPIO_InitStructure;
+  USART_InitType USART_InitStructure;
+
+  /*Enable the UART Clock*/
+#if defined (AT32F421xx)
+  RCC_AHBPeriphClockCmd(AT32_PRINT_UARTTX_GPIO_RCC | AT32_PRINT_UARTRX_GPIO_RCC, ENABLE);	
+#else
+  RCC_APB2PeriphClockCmd(AT32_PRINT_UARTTX_GPIO_RCC | AT32_PRINT_UARTRX_GPIO_RCC, ENABLE);	
+#endif
+  AT32_PRINT_UART_RCC_CLK_FUNC;
+
+  /* Configure the UART1 TX pin */
+  GPIO_StructInit(&GPIO_InitStructure);
+  GPIO_InitStructure.GPIO_Pins = AT32_PRINT_UARTTX_PIN; 
+  GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
+#if !defined (AT32F421xx)
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+#else
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OutType = GPIO_OutType_PP;
+  GPIO_InitStructure.GPIO_Pull = GPIO_Pull_NOPULL;
+#endif
+  GPIO_Init(AT32_PRINT_UARTTX_GPIO, &GPIO_InitStructure);
+
+  /* Configure the UART1 RX pin */
+  GPIO_InitStructure.GPIO_Pins = AT32_PRINT_UARTRX_PIN;//PA10
+#if !defined (AT32F421xx)
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+#else
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Pull = GPIO_Pull_PU;
+#endif
+  GPIO_Init(AT32_PRINT_UARTRX_GPIO, &GPIO_InitStructure);
+
+#if defined (AT32F421xx)
+  GPIO_PinAFConfig(GPIOA, GPIO_PinsSource9, GPIO_AF_1);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinsSource10, GPIO_AF_1);
+#endif
+
+  /*Configure UART param*/
+  USART_StructInit(&USART_InitStructure);
+  USART_InitStructure.USART_BaudRate = bound;
+  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+  USART_InitStructure.USART_StopBits = USART_StopBits_1;
+  USART_InitStructure.USART_Parity = USART_Parity_No;
+  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;	
+
+  USART_Init(AT32_PRINT_UART, &USART_InitStructure); 
+  USART_INTConfig(AT32_PRINT_UART, USART_INT_RDNE, ENABLE);
+  USART_Cmd(AT32_PRINT_UART, ENABLE);   
+}
+
+/**
+  * @brief  initialize Delay function   
+  * @param  None
+  * @retval None
+  */		   
+void Delay_init()
+{
+  /*Config Systick*/
+  SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
+  fac_us = SystemCoreClock / (1000000U);
+  fac_ms = fac_us * (1000U);
+}
+
+/**
+  * @brief  Inserts a delay time.
+  * @param  nus: specifies the delay time length, in microsecond.
+  * @retval None
+  */
+void Delay_us(u32 nus)
+{
+  u32 temp;
+  SysTick->LOAD = (u32)(nus*fac_us);
+  SysTick->VAL = 0x00;
+  SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk ;
+  do
+  {
+    temp = SysTick->CTRL;
+  }while((temp & 0x01) &&! (temp & (1<<16)));
+
+  SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+  SysTick->VAL = 0x00;
+}
+
+/**
+  * @brief  Inserts a delay time.
+  * @param  nms: specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+void Delay_ms(u16 nms)
+{
+  u32 temp;
+  while(nms)
+  {
+    if(nms > STEP_DELAY_MS)
+    {
+      SysTick->LOAD = (u32)(STEP_DELAY_MS * fac_ms);
+      nms -= STEP_DELAY_MS;
+    }
+    else
+    {
+      SysTick->LOAD = (u32)(nms * fac_ms);
+      nms = 0;
+    }
+    SysTick->VAL = 0x00;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+    do
+    {
+      temp = SysTick->CTRL;
+    }while( (temp & 0x01) && !(temp & (1<<16)) );
+
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->VAL = 0x00;
+  }
+}
+
+/**
+  * @brief  Inserts a delay time.
+  * @param  sec: specifies the delay time length, in seconds.
+  * @retval None
+  */
+void Delay_sec(u16 sec)
+{
+  u16 i;
+  for(i=0; i<sec; i++)
+  {
+    Delay_ms(500);
+    Delay_ms(500);
+  }
+}
+	
+
+
+
+
+

BSP/inc/at32_board.h

@@ -0,0 +1,196 @@
+/**
+  **************************************************************************
+  * File   : at32_board.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : Header file for AT-START board
+  *          1. Set of firmware functions to manage Leds, push-button and COM ports.
+  *          2. initialize Delay Function and USB
+  */
+
+#ifndef __AT32_BOARD_H
+#define __AT32_BOARD_H	 
+#include <at32f4xx.h>
+/*
+* This header include define support list:
+* 	1. AT-START-F403 V1.2 Board
+* 	2. AT-START-F413 V1.0 Board
+* 	3. AT-START-F415 V1.0 Board
+* 	4. AT-START-F403A V1.0 Board
+* 	5. AT-START-F407 V1.0 Board
+* 	6. AT-START-F421 V1.0 Board
+* if define AT_START_F403_V1_2, the header file support AT-START-F403 V1.2 Board
+* if define AT_START_F413_V1_0, the header file support AT-START-F413 V1.0 Board
+* if define AT_START_F415_V1_0, the header file support AT-START-F415 V1.0 Board
+* if define AT_START_F403A_V1_0, the header file support AT-START-F403A V1.0 Board
+* if define AT_START_F407_V1_0, the header file support AT-START-F407 V1.0 Board
+* if define AT_START_F421_V1_0, the header file support AT-START-F421 V1.0 Board
+*/
+#if !defined (AT_START_F403_V1_2) && !defined (AT_START_F413_V1_0) && !defined (AT_START_F415_V1_0) && \
+    !defined (AT_START_F403A_V1_0)&& !defined (AT_START_F407_V1_0) && !defined (AT_START_F421_V1_0)
+#error "Please select first the board AT-START device used in your application (in at32_board.h file)"
+#endif
+
+/*define usb pin*/
+#define USB_DP_PIN          GPIO_Pins_12
+#define USB_DM_PIN          GPIO_Pins_11
+
+#define USB_GPIO            GPIOA
+#if defined (AT32F421xx)
+#define USB_GPIO_RCC_CLK    RCC_AHBPERIPH_GPIOA
+#else
+#define USB_GPIO_RCC_CLK    RCC_APB2PERIPH_GPIOA
+#endif
+
+/*AT_START LED*/
+typedef enum
+{
+  LED1 = 0,
+  LED2,
+  LED3,
+  LED4
+}LED_Type;    
+
+#define LED_NUM     4
+
+#if defined (AT_START_F413_V1_0) || defined (AT_START_F415_V1_0)
+/*have no LED1*/
+#define LED1_PIN                0
+#define LED1_GPIO               NULL
+#define LED1_GPIO_RCC_CLK       0
+
+#define LED2_PIN                GPIO_Pins_2
+#define LED2_GPIO               GPIOC
+#define LED2_GPIO_RCC_CLK       RCC_APB2PERIPH_GPIOC
+
+#define LED3_PIN                GPIO_Pins_3
+#define LED3_GPIO               GPIOC
+#define LED3_GPIO_RCC_CLK       RCC_APB2PERIPH_GPIOC
+
+#define LED4_PIN                GPIO_Pins_5
+#define LED4_GPIO               GPIOC
+#define LED4_GPIO_RCC_CLK       RCC_APB2PERIPH_GPIOC
+
+#elif defined (AT_START_F403_V1_2) || defined (AT_START_F403A_V1_0) || \
+    defined (AT_START_F407_V1_0)
+/*have no LED1*/
+#define LED1_PIN                0
+#define LED1_GPIO               NULL
+#define LED1_GPIO_RCC_CLK       0
+
+#define LED2_PIN                GPIO_Pins_13
+#define LED2_GPIO               GPIOC
+#define LED2_GPIO_RCC_CLK       RCC_APB2PERIPH_GPIOC
+
+#define LED3_PIN                GPIO_Pins_14
+#define LED3_GPIO               GPIOC
+#define LED3_GPIO_RCC_CLK       RCC_APB2PERIPH_GPIOC
+
+#define LED4_PIN                GPIO_Pins_15
+#define LED4_GPIO               GPIOC
+#define LED4_GPIO_RCC_CLK       RCC_APB2PERIPH_GPIOC
+
+#elif defined (AT_START_F421_V1_0)
+/*have no LED1*/
+#define LED1_PIN                0
+#define LED1_GPIO               NULL
+#define LED1_GPIO_RCC_CLK       0
+
+#define LED2_PIN                GPIO_Pins_6
+#define LED2_GPIO               GPIOF
+#define LED2_GPIO_RCC_CLK       RCC_AHBPERIPH_GPIOF
+
+#define LED3_PIN                GPIO_Pins_7
+#define LED3_GPIO               GPIOF
+#define LED3_GPIO_RCC_CLK       RCC_AHBPERIPH_GPIOF
+
+#define LED4_PIN                GPIO_Pins_11
+#define LED4_GPIO               GPIOB
+#define LED4_GPIO_RCC_CLK       RCC_AHBPERIPH_GPIOB 
+#endif
+/*End LED define*/
+
+
+/*define button*/
+typedef enum
+{
+  BUTTON_WAKEUP = 0,
+  BUTTON_USER_KEY,
+  BUTTON_KEY1_DOWN,
+  BUTTON_KEY2_LEFT,   
+  NO_BUTTON    
+}BUTTON_Type;
+
+#define BUTTON_NUM  2
+
+#define BUTTON_WAKEUP_PIN              GPIO_Pins_0
+#define BUTTON_WAKEUP_GPIO             GPIOA
+#if defined (AT32F421xx)
+#define BUTTON_WAKEUP_RCC_CLK          RCC_AHBPERIPH_GPIOA
+#else
+#define BUTTON_WAKEUP_RCC_CLK          RCC_APB2PERIPH_GPIOA
+#endif
+
+#define BUTTON_USER_KEY_PIN            GPIO_Pins_13
+#define BUTTON_USER_KEY_GPIO           GPIOD
+#if defined (AT32F421xx)
+#define BUTTON_USER_KEY_RCC_CLK        RCC_AHBPERIPH_GPIOC
+#else
+#define BUTTON_USER_KEY_RCC_CLK        RCC_APB2PERIPH_GPIOC
+#endif
+
+/*end define button*/
+#ifdef AT_START_F403_V1_2
+/*Audio DAC OUTPUT GPIO Pin*/
+#define F403_AUDIO_DAC_OUTPIN      GPIO_Pins_4
+#endif
+
+/**************** UART printf ****************/
+#define AT32_PRINT_UART                USART1
+#define USARTx_IRQn                    USART1_IRQn
+#define USARTx_IRQ_Handler             USART1_IRQHandler
+#define AT32_PRINT_UART_RCC_CLK_FUNC   RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_USART1, ENABLE)
+
+/*Tx*/
+#define AT32_PRINT_UARTTX_PIN          GPIO_Pins_9 
+#define AT32_PRINT_UARTTX_GPIO         GPIOA
+#if defined (AT32F421xx)
+#define AT32_PRINT_UARTTX_GPIO_RCC     RCC_AHBPERIPH_GPIOA
+#else
+#define AT32_PRINT_UARTTX_GPIO_RCC     RCC_APB2PERIPH_GPIOA
+#endif
+
+/*Rx*/
+#define AT32_PRINT_UARTRX_PIN          GPIO_Pins_10
+#define AT32_PRINT_UARTRX_GPIO         GPIOA
+#if defined (AT32F421xx)
+#define AT32_PRINT_UARTRX_GPIO_RCC     RCC_AHBPERIPH_GPIOA
+#else
+#define AT32_PRINT_UARTRX_GPIO_RCC     RCC_APB2PERIPH_GPIOA
+#endif
+
+/**************** End UART printf ****************/
+
+void AT32_Board_Init(void);
+void AT32_USB_GPIO_init(void);
+
+/*Led Operation function*/
+void AT32_LEDn_Init(LED_Type led);
+void AT32_LEDn_ON(LED_Type led);
+void AT32_LEDn_OFF(LED_Type led);
+void AT32_LEDn_Toggle(LED_Type led);
+
+/*Button Operation function*/
+void AT32_BUTTON_Init(BUTTON_Type button);
+BUTTON_Type AT32_BUTTON_Press(void);
+uint8_t AT32_BUTTON_State(BUTTON_Type button);
+
+void UART_Print_Init(uint32_t bound);
+
+/*Delay function*/
+void Delay_init(void);
+void Delay_us(u32 nus);
+void Delay_ms(u16 nms);
+void Delay_sec(u16 sec);
+#endif
+

CMSIS/CoreSupport/arm_common_tables.h

@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. October 2015
+* $Revision: 	V.1.4.5 a
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */

CMSIS/CoreSupport/arm_const_structs.h

@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

CMSIS/CoreSupport/cmsis_armcc.h

@@ -0,0 +1,734 @@
+/**************************************************************************//**
+ * File   :cmsis_armcc.h
+ * Brief  :CMSIS Cortex-M Core Function/Instruction Header File
+ * Version:V4.30
+ * Date   :20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+
+#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    value  Value to rotate
+  \param [in]    value  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

CMSIS/CoreSupport/cmsis_iar.h

@@ -0,0 +1,266 @@
+/**************************************************
+ *
+ * This file shall be included in appropriate CMSIS header
+ * files, to provide required functions and intrinsics when
+ * building with the IAR C/C++ Compiler for ARM (iccarm).
+ *
+ * Copyright 2011 IAR Systems. All rights reserved.
+ *
+ * $Revision: 78346 $
+ *
+ **************************************************/
+
+#ifndef __CMSIS_IAR_H__
+#define __CMSIS_IAR_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#include <intrinsics.h>
+
+#if (__CORE__ == __ARM6M__)
+  /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+  #define __CLZ __cmsis_iar_clz
+  #define __SSAT __cmsis_iar_ssat
+#endif
+
+#pragma diag_suppress=Pe940
+#pragma diag_suppress=Pe177
+
+#define __enable_irq    __enable_interrupt
+#define __disable_irq   __disable_interrupt
+#define __NOP           __no_operation
+
+#if (__VER__ >= 6040000)  /* If iccarm version is 6.40.x or newer ---------- */
+
+#define __BKPT(value)   asm volatile ("BKPT\t%0" : : "i"(value))
+
+#endif
+
+#if (__VER__ < 6020000)  /* If iccarm version is older than 6.20.0 ---------- */
+
+#if (__VER__ < 6010002)  /* If iccarm version is older than 6.10.2 ---------- */
+
+static uint32_t __get_APSR(void)
+{
+  __ASM("mrs r0, apsr");
+}
+
+static uint32_t __get_xPSR(void)
+{
+  __ASM("mrs r0, psr");           /* assembler does not know "xpsr" */
+}
+
+#endif                   /* __VER__ < 6010002 */
+
+static uint32_t __get_IPSR(void)
+{
+  __ASM("mrs r0, ipsr");
+}
+
+static uint32_t __get_PSR(void)
+{
+  __ASM("mrs r0, psr");
+}
+
+static uint32_t __get_PSP(void)
+{
+  __ASM("mrs r0, psp");
+}
+ 
+static void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM("msr psp, r0");
+}
+
+static uint32_t __get_MSP(void)
+{
+  __ASM("mrs r0, msp");
+}
+ 
+static void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM("msr msp, r0");
+}
+
+static __INLINE  void __WFI(void)
+{
+  __ASM ("wfi");
+}
+
+static __INLINE  void __WFE(void)
+{
+  __ASM ("wfe");
+}
+
+static __INLINE  void __SEV(void)
+{
+  __ASM ("sev");
+}
+
+static uint32_t __REV16(uint32_t value)
+{
+  __ASM("rev16 r0, r0");
+}
+
+#else                   /* __VER__ < 6020000 */
+
+static uint32_t __get_xPSR(void)
+{
+  return __get_PSR();   /* __get_PSR() intrinsic introduced in iccarm 6.20 */
+}
+
+#endif                   /* __VER__ < 6020000 */
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+#if (__VER__ < 6020000)  /* If iccarm version is older than 6.20.0 ---------- */
+
+static __INLINE void __enable_fault_irq(void)
+{
+  __ASM ("cpsie f");
+}
+
+static __INLINE void __disable_fault_irq(void)
+{
+  __ASM ("cpsid f");
+}
+
+static uint32_t __RBIT(uint32_t value)
+{
+  __ASM("rbit r0, r0");
+}
+
+static uint8_t __LDREXB(volatile uint8_t *addr)
+{
+  __ASM("ldrexb r0, [r0]");
+}
+
+static uint16_t __LDREXH(volatile uint16_t *addr)
+{
+  __ASM("ldrexh r0, [r0]");
+}
+
+static uint32_t __LDREXW(volatile uint32_t *addr)
+{
+  __ASM("ldrex r0, [r0]");
+}
+
+static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+  __ASM("strexb r0, r0, [r1]");
+}
+
+static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+  __ASM("strexh r0, r0, [r1]");
+}
+
+static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+  __ASM("strex r0, r0, [r1]");
+}
+
+static __INLINE void __CLREX(void)
+{
+  __ASM ("clrex");
+}
+
+#else                  /* __VER__ >= 6020000 --------------------- */
+
+#define __LDREXW        __LDREX
+#define __STREXW        __STREX
+#define __enable_fault_irq __enable_fiq
+#define __disable_fault_irq __disable_fiq
+
+#endif                 /* __VER__ < 6020000 */
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if (__CORTEX_M == 0x04)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+#if (__VER__ < 6020000)  /* If iccarm version is older than 6.20.0 ---------- */
+
+static uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1)   /* __FPU_PRESENT is defined in the device header file, if present in current device. */
+  __ASM("vmrs r0, fpscr"); 
+#else
+  return(0);
+#endif
+}
+
+static void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1)   /* __FPU_PRESENT is defined in the device header file, if present in current device. */
+  __ASM("vmsr fpscr, r0");
+#endif
+}
+
+#endif                 /* __VER__ < 6020000 */
+
+#endif /* (__CORTEX_M == 0x04) */
+
+#if (__VER__ >= 7000000)  /* If iccarm version is 7.x or newer ---------- */
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+static __INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+  __ASM("RRX %0, %1" : "=r"(result) : "r" (value) );
+  return(result);
+}
+
+static __INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+  uint32_t result;
+  __ASM("LDRBT %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+  return ((uint8_t) result);
+}
+
+static __INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+  uint32_t result;
+  __ASM("LDRHT %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+  return ((uint16_t) result);
+}
+
+static __INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+  uint32_t result;
+  __ASM("LDRT %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+  return(result);
+}
+
+static __INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+  __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory" );
+}
+
+static __INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+  __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory" );
+}
+
+static __INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+  __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory" );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#endif                 /* __VER__ >= 7000000 */
+
+static __INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+}
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_IAR_H__ */

CMSIS/CoreSupport/core_cmFunc.h

@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * File   :core_cmFunc.h
+ * Brief  :CMSIS Cortex-M Core Function Access Header File
+ * Version:V4.30
+ * Date   :20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

CMSIS/CoreSupport/core_cmInstr.h

@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * File   :core_cmInstr.h
+ * Brief  :CMSIS Cortex-M Core Instruction Access Header File
+ * Version:V4.30
+ * Date   :20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

CMSIS/CoreSupport/core_cmSimd.h

@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * File   :core_cmSimd.h
+ * Brief  :CMSIS Cortex-M SIMD Header File
+ * Version:V4.30
+ * Date   :20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */

CMSIS/DeviceSupport/at32f4xx_conf.h

@@ -0,0 +1,74 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_conf.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx configuration file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_CONF_H
+#define __AT32F4XX_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
+#include "at32f4xx_acc.h"
+#include "at32f4xx_adc.h"
+#include "at32f4xx_bkp.h"
+#include "at32f4xx_can.h"
+#include "at32f4xx_comp.h"
+#include "at32f4xx_crc.h"
+#include "at32f4xx_dac.h"
+#include "at32f4xx_dbgmcu.h"
+#include "at32f4xx_dma.h"
+#include "at32f4xx_ertc.h"
+#include "at32f4xx_exti.h"
+#include "at32f4xx_flash.h"
+#if !defined (AT32F421xx)
+#include "at32f4xx_gpio.h"
+#else
+#include "at32f4xx_gpio_ex.h"
+#endif
+#include "at32f4xx_i2c.h"
+#include "at32f4xx_iwdg.h"
+#include "at32f4xx_pwr.h"
+#include "at32f4xx_rcc.h"
+#include "at32f4xx_rtc.h"
+#include "at32f4xx_sdio.h"
+#include "at32f4xx_spi.h"
+#include "at32f4xx_tim.h"
+#include "at32f4xx_usart.h"
+#include "at32f4xx_wwdg.h"
+#include "at32f4xx_xmc.h"
+#include "at32f4xx_syscfg.h"
+#include "misc.h"
+/* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports
+  *         the name of the source file and the source line number of the call
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __AT32F4XX_CONF_H */
+
+

CMSIS/DeviceSupport/linker/AT32F403AxG_FLASH.ld

@@ -0,0 +1,134 @@
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20018000;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1000K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

CMSIS/DeviceSupport/startup/startup_at32f403acgt7.s

@@ -0,0 +1,462 @@
+/**
+  ******************************************************************************
+  * File   : startup_at32f403acgt7.s
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                               */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  0                                   /* Reserved                                */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+

CMSIS/DeviceSupport/syscalls.c

@@ -0,0 +1,194 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Abstract    : System Workbench Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : System Workbench for MCU
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright System Workbench for MCU.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. System Workbench for MCU permit registered System Workbench(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the System Workbench for MCU toolchain.
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <stdio.h>
+#include <signal.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+#define FreeRTOS
+#define MAX_STACK_SIZE 0x2000
+
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+#ifndef FreeRTOS
+  register char * stack_ptr asm("sp");
+#endif
+
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+int _read (int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+//		write(1, "Heap and stack collision\n", 25);
+//		abort();
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}

CMSIS/DeviceSupport/system_at32f4xx.h

@@ -0,0 +1,88 @@
+/**
+  **************************************************************************
+  * File   : system_at32f4xx.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : CMSIS Cortex-M4 system header file.
+  **************************************************************************
+  */
+
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup at32f4xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_AT32F4XX_H
+#define __SYSTEM_AT32F4XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup AT32F4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup AT32F4xx_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup AT32F4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup AT32F4xx_System_Exported_Macros
+  * @{
+  */
+#define HSE_STABLE_DELAY             (5000u)
+#define PLL_STABLE_DELAY             (500u)
+/**
+  * @}
+  */
+
+/** @addtogroup AT32F4xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_AT32F4XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

CMakeLists.txt

@@ -0,0 +1,65 @@
+#此文件从模板自动生成! 请勿更改!
+set(CMAKE_SYSTEM_NAME Generic)
+set(CMAKE_SYSTEM_VERSION 1)
+cmake_minimum_required(VERSION 3.21)
+
+# specify cross compilers and tools
+set(CMAKE_C_COMPILER arm-none-eabi-gcc)
+set(CMAKE_CXX_COMPILER arm-none-eabi-g++)
+set(CMAKE_ASM_COMPILER arm-none-eabi-gcc)
+set(CMAKE_AR arm-none-eabi-ar)
+set(CMAKE_OBJCOPY arm-none-eabi-objcopy)
+set(CMAKE_OBJDUMP arm-none-eabi-objdump)
+set(SIZE arm-none-eabi-size)
+set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
+
+# project settings
+project(FPU_TEST C CXX ASM)
+set(CMAKE_CXX_STANDARD 17)
+set(CMAKE_C_STANDARD 11)
+
+#Uncomment for hardware floating point
+#add_compile_definitions(ARM_MATH_CM4;ARM_MATH_MATRIX_CHECK;ARM_MATH_ROUNDING)
+#add_compile_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)
+#add_link_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)
+
+#Uncomment for software floating point
+#add_compile_options(-mfloat-abi=soft)
+
+add_compile_options(-mcpu=cortex-m4 -mthumb -mthumb-interwork)
+add_compile_options(-ffunction-sections -fdata-sections -fno-common -fmessage-length=0)
+# uncomment to mitigate c++17 absolute addresses warnings
+#set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-register")
+add_compile_options(-O3)
+include_directories(
+        User/inc
+        StdPeriph_Driver/inc
+        CMSIS/CoreSupport
+        CMSIS/DeviceSupport
+        BSP/inc
+)
+
+add_definitions(-DAT32F403ACGT7 -DUSE_STDPERIPH_DRIVER -DAT_START_F403A_V1_0)
+
+file(GLOB_RECURSE SOURCES
+        "BSP/*.*"
+        "CMSIS/DeviceSupport/*.*"
+        "CMSIS/DeviceSupport/startup/*.*"
+        "StdPeriph_Driver/src/*.*"
+        User/*.*
+        )
+set(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/CMSIS/DeviceSupport/linker/AT32F403AxG_FLASH.ld)
+add_link_options(-Wl,-gc-sections,--print-memory-usage,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map)
+add_link_options(-mcpu=cortex-m4 -mthumb -mthumb-interwork)
+add_link_options(-T ${LINKER_SCRIPT})
+
+add_executable(${PROJECT_NAME}.elf ${SOURCES} ${LINKER_SCRIPT})
+
+set(HEX_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.hex)
+set(BIN_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.bin)
+
+add_custom_command(TARGET ${PROJECT_NAME}.elf POST_BUILD
+        COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${PROJECT_NAME}.elf> ${HEX_FILE}
+        COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${PROJECT_NAME}.elf> ${BIN_FILE}
+        COMMENT "Building ${HEX_FILE}
+Building ${BIN_FILE}")

README.md

@@ -0,0 +1,2 @@
+#AT32_BSPV1_Clion_Template
+使用自己的linker文件时注意修改_estack的值为4字节对齐

StdPeriph_Driver/inc/at32f4xx_acc.h

@@ -0,0 +1,96 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_acc.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx ACC header file
+  **************************************************************************
+  */
+
+
+ /* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_ACC_H
+#define __AT32F4XX_ACC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ACC
+  * @{
+  */
+
+  /** @defgroup ACC_Exported_Constants
+  * @{
+  */
+#define ACC_CAL_Enable                        ((uint16_t)0x0001)
+
+#define ACC_CAL_ON                            ((uint16_t)0x0001)
+#define ACC_TRIM_ON                           ((uint16_t)0x0003)
+
+#define ACC_CAL_HSICAL                        ((uint16_t)0x0000)
+#define ACC_CAL_HSITRIM                       ((uint16_t)0x0002)
+  
+#define ACC_FLAG_RSLOST                       ((uint16_t)0x0002)
+#define ACC_FLAG_CALRDY                       ((uint16_t)0x0001)
+
+#define ACC_IT_CALRDYIEN                      ((uint16_t)0x0020)
+#define ACC_IT_EIEN                           ((uint16_t)0x0010)
+/**
+  * @}
+  */
+  
+/** @defgroup ACC_Exported_Functions
+  * @{
+  */  
+
+void ACC_EnterCALMode(uint16_t ACC_ON, FunctionalState NewState);
+void ACC_ExitCALMode(void);
+void ACC_SetStep(uint8_t StepValue);
+void ACC_CAL_Choose(uint16_t ACC_Calibration_Choose);
+void ACC_ITConfig(uint16_t ACC_IT, FunctionalState NewState);
+
+uint8_t ACC_GetHSITRIM(void);
+uint8_t ACC_GetHSICAL(void);
+
+void ACC_WriteC1(uint16_t ACC_C1_Value);
+void ACC_WriteC2(uint16_t ACC_C2_Value);
+void ACC_WriteC3(uint16_t ACC_C3_Value);
+
+uint16_t ACC_ReadC1(void);
+uint16_t ACC_ReadC2(void);
+uint16_t ACC_ReadC3(void);
+
+FlagStatus ACC_GetFlagStatus(uint16_t ACC_FLAG);
+void ACC_ClearFlag(uint16_t ACC_FLAG);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_ACC_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/**
+  * @}
+  */    
+
+
+
+
+

StdPeriph_Driver/inc/at32f4xx_adc.h

@@ -0,0 +1,568 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_adc.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx ADC header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_ADC_H
+#define __AT32F4XX_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  ADC Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in independent or
+                                               dual mode.
+                                               This parameter can be a value of @ref ADC_mode */
+
+    FunctionalState ADC_ScanMode;           /*!< Specifies whether the conversion is performed in
+                                                   Scan (multichannels) or Single (one channel) mode.
+                                                   This parameter can be set to ENABLE or DISABLE */
+
+    FunctionalState ADC_ContinuousMode;     /*!< Specifies whether the conversion is performed in
+                                                   Continuous or Single mode.
+                                                   This parameter can be set to ENABLE or DISABLE. */
+
+    uint32_t ADC_ExternalTrig;              /*!< Defines the external trigger used to start the analog
+                                                   to digital conversion of regular channels. This parameter
+                                                   can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+    uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.
+                                               This parameter can be a value of @ref ADC_data_align */
+
+    uint8_t ADC_NumOfChannel;               /*!< Specifies the number of ADC channels that will be converted
+                                               using the sequencer for regular channel group.
+                                               This parameter must range from 1 to 16. */
+} ADC_InitType;
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */
+
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+#define IS_ADC_ALL_PERIPH(PERIPH)           (((PERIPH) == ADC1) || \
+                                             ((PERIPH) == ADC2) || \
+                                             ((PERIPH) == ADC3))
+#elif defined (AT32F413xx)
+#define IS_ADC_ALL_PERIPH(PERIPH)           (((PERIPH) == ADC1) || \
+                                             ((PERIPH) == ADC2))
+#elif defined (AT32F415xx) || defined (AT32F421xx)
+#define IS_ADC_ALL_PERIPH(PERIPH)           (((PERIPH) == ADC1))
+#endif
+
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+#define IS_ADC_DMA_PERIPH(PERIPH)           (((PERIPH) == ADC1) || \
+                                             ((PERIPH) == ADC3))
+#elif defined (AT32F413xx) || defined (AT32F415xx) || defined (AT32F421xx)
+#define IS_ADC_DMA_PERIPH(PERIPH)           (((PERIPH) == ADC1))
+#endif
+
+
+/** @defgroup ADC_mode
+  * @{
+  */
+
+#define ADC_Mode_Independent                ((uint32_t)0x00000000)
+#if (!defined (AT32F421xx)) && (!defined (AT32F415xx))
+#define ADC_Mode_RegInjecSimult             ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig        ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl     ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl     ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult                ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult                  ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl                 ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl                 ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig                  ((uint32_t)0x00090000)
+#endif
+#if defined (AT32F421xx) || defined (AT32F415xx)
+#define IS_ADC_MODE(MODE)                   (((MODE) == ADC_Mode_Independent))
+#else
+#define IS_ADC_MODE(MODE)                   (((MODE) == ADC_Mode_Independent) || \
+                                             ((MODE) == ADC_Mode_RegInjecSimult) || \
+                                             ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
+                                             ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
+                                             ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
+                                             ((MODE) == ADC_Mode_InjecSimult) || \
+                                             ((MODE) == ADC_Mode_RegSimult) || \
+                                             ((MODE) == ADC_Mode_FastInterl) || \
+                                             ((MODE) == ADC_Mode_SlowInterl) || \
+                                             ((MODE) == ADC_Mode_AlterTrig))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
+  * @{
+  */
+
+#define ADC_ExternalTrig_TMR1_CC1_ADC12             ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrig_TMR1_CC2_ADC12             ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
+#if !defined (AT32F421xx)
+#define ADC_ExternalTrig_TMR2_CC2_ADC12             ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
+#endif
+#define ADC_ExternalTrig_TMR3_TRGO_ADC12            ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
+#if !defined (AT32F421xx)
+#define ADC_ExternalTrig_TMR4_CC4_ADC12             ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
+#endif
+#define ADC_ExternalTrig_Ext_INT11_TMR8_TRGO_ADC12  ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
+#if !defined (AT32F421xx)
+#define ADC_ExternalTrig_TMR8_CC1_ADC12             ((uint32_t)0x020C0000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrig_TMR8_CC2_ADC12             ((uint32_t)0x020E0000) /*!< For ADC1 and ADC2 */
+#endif
+
+#define ADC_ExternalTrig_TMR1_CC3                   ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrig_None                       ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
+#if !defined (AT32F421xx)
+#define ADC_ExternalTrig_TMR15_CC1                  ((uint32_t)0x02000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrig_TMR15_CC2                  ((uint32_t)0x02020000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrig_TMR15_CC3                  ((uint32_t)0x02040000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrig_TMR15_CC4                  ((uint32_t)0x02060000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrig_TMR15_TRGO                 ((uint32_t)0x02080000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrig_TMR1_TRGO                  ((uint32_t)0x020A0000) /*!< For ADC1, ADC2 and ADC3 */
+                                                    
+#define ADC_ExternalTrig_TMR3_CC1_ADC3              ((uint32_t)0x00000000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR2_CC3_ADC3              ((uint32_t)0x00020000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR8_CC1_ADC3              ((uint32_t)0x00060000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR8_TRGO_ADC3             ((uint32_t)0x00080000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR5_CC1_ADC3              ((uint32_t)0x000A0000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR5_CC3_ADC3              ((uint32_t)0x000C0000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR1_CC1_ADC3              ((uint32_t)0x020C0000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR8_CC3_ADC3              ((uint32_t)0x020E0000) /*!< For ADC3 only */
+#else
+#define ADC_ExternalTrig_TMR15_CC1                  ((uint32_t)0x000A0000) /*!< For ADC1, ADC2 and ADC3 */
+#endif
+
+#if !defined (AT32F421xx)
+#define IS_ADC_EXT_TRIG(REGTRIG)                    (((REGTRIG) == ADC_ExternalTrig_TMR1_CC1_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR1_CC2_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR2_CC2_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR3_TRGO_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR4_CC4_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_Ext_INT11_TMR8_TRGO_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR8_CC1_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR8_CC2_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR1_CC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_None) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR15_CC1) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR15_CC2) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR15_CC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR15_CC4) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR15_TRGO) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR1_TRGO) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR3_CC1_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR2_CC3_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR8_CC1_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR8_TRGO_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR5_CC1_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR5_CC3_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR1_CC1_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR8_CC3_ADC3))
+#else
+#define IS_ADC_EXT_TRIG(REGTRIG)                    (((REGTRIG) == ADC_ExternalTrig_TMR1_CC1_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR1_CC2_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR3_TRGO_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_Ext_INT11_TMR8_TRGO_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR1_CC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_None) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR15_CC1))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_data_align
+  * @{
+  */
+
+#define ADC_DataAlign_Right                         ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                          ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN(ALIGN)                    (((ALIGN) == ADC_DataAlign_Right) || \
+                                                     ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_channels
+  * @{
+  */
+
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_9                               ((uint8_t)0x09)
+#define ADC_Channel_10                              ((uint8_t)0x0A)
+#define ADC_Channel_11                              ((uint8_t)0x0B)
+#define ADC_Channel_12                              ((uint8_t)0x0C)
+#define ADC_Channel_13                              ((uint8_t)0x0D)
+#define ADC_Channel_14                              ((uint8_t)0x0E)
+#define ADC_Channel_15                              ((uint8_t)0x0F)
+#define ADC_Channel_16                              ((uint8_t)0x10)
+#define ADC_Channel_17                              ((uint8_t)0x11)
+                                                    
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
+                                                    
+#define IS_ADC_CHANNEL(CHANNEL)                     (((CHANNEL) == ADC_Channel_0)  || ((CHANNEL) == ADC_Channel_1) || \
+                                                     ((CHANNEL) == ADC_Channel_2)  || ((CHANNEL) == ADC_Channel_3) || \
+                                                     ((CHANNEL) == ADC_Channel_4)  || ((CHANNEL) == ADC_Channel_5) || \
+                                                     ((CHANNEL) == ADC_Channel_6)  || ((CHANNEL) == ADC_Channel_7) || \
+                                                     ((CHANNEL) == ADC_Channel_8)  || ((CHANNEL) == ADC_Channel_9) || \
+                                                     ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
+                                                     ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
+                                                     ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
+                                                     ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_sampling_time
+  * @{
+  */
+
+#define ADC_SampleTime_1_5                          ((uint8_t)0x00)
+#define ADC_SampleTime_7_5                          ((uint8_t)0x01)
+#define ADC_SampleTime_13_5                         ((uint8_t)0x02)
+#define ADC_SampleTime_28_5                         ((uint8_t)0x03)
+#define ADC_SampleTime_41_5                         ((uint8_t)0x04)
+#define ADC_SampleTime_55_5                         ((uint8_t)0x05)
+#define ADC_SampleTime_71_5                         ((uint8_t)0x06)
+#define ADC_SampleTime_239_5                        ((uint8_t)0x07)
+#define IS_ADC_SAMPLE_TIME(TIME)                    (((TIME) == ADC_SampleTime_1_5) || \
+                                                     ((TIME) == ADC_SampleTime_7_5) || \
+                                                     ((TIME) == ADC_SampleTime_13_5) || \
+                                                     ((TIME) == ADC_SampleTime_28_5) || \
+                                                     ((TIME) == ADC_SampleTime_41_5) || \
+                                                     ((TIME) == ADC_SampleTime_55_5) || \
+                                                     ((TIME) == ADC_SampleTime_71_5) || \
+                                                     ((TIME) == ADC_SampleTime_239_5))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
+  * @{
+  */
+#if !defined (AT32F421xx)
+#define ADC_ExternalTrigInjec_TMR2_TRGO_ADC12             ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjec_TMR2_CC1_ADC12              ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
+#endif
+#define ADC_ExternalTrigInjec_TMR3_CC4_ADC12              ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
+#if !defined (AT32F421xx)
+#define ADC_ExternalTrigInjec_TMR4_TRGO_ADC12             ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
+#endif
+#define ADC_ExternalTrigInjec_Ext_INT15_TMR8_CC4_ADC12    ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
+#if !defined (AT32F421xx)
+#define ADC_ExternalTrigInjec_TMR8_CC1_ADC12              ((uint32_t)0x01006000) /*!< For ADC1 and ADC2 */
+ #endif                                                   
+#define ADC_ExternalTrigInjec_TMR1_TRGO                   ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_TMR1_CC4                    ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_None                        ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
+#if !defined (AT32F421xx)
+#define ADC_ExternalTrigInjec_TMR15_CC1                   ((uint32_t)0x01000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_TMR15_CC2                   ((uint32_t)0x01001000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_TMR15_CC3                   ((uint32_t)0x01002000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_TMR15_CC4                   ((uint32_t)0x01003000) /*!< For ADC1, ADC2 and ADC3 */
+#endif
+#define ADC_ExternalTrigInjec_TMR15_TRGO                  ((uint32_t)0x01004000) /*!< For ADC1, ADC2 and ADC3 */
+#if !defined (AT32F421xx)
+#define ADC_ExternalTrigInjec_TMR1_CC1                    ((uint32_t)0x01005000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_TMR8_TRGO                   ((uint32_t)0x01007000) /*!< For ADC1, ADC2 and ADC3 */
+                                                    
+#define ADC_ExternalTrigInjec_TMR4_CC3_ADC3               ((uint32_t)0x00002000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjec_TMR8_CC2_ADC3               ((uint32_t)0x00003000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjec_TMR8_CC4_ADC3               ((uint32_t)0x00004000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjec_TMR5_TRGO_ADC3              ((uint32_t)0x00005000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjec_TMR5_CC4_ADC3               ((uint32_t)0x00006000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjec_TMR1_CC2_ADC3               ((uint32_t)0x01006000) /*!< For ADC3 only */
+#endif
+#if !defined (AT32F421xx)
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG)              (((INJTRIG) == ADC_ExternalTrigInjec_TMR2_TRGO_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR2_CC1_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR3_CC4_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR4_TRGO_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_Ext_INT15_TMR8_CC4_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR8_CC1_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR1_TRGO) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR1_CC4) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_None) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR15_CC1) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR15_CC2) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR15_CC3) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR15_CC4) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR15_TRGO) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR1_CC1) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR8_TRGO) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR4_CC3_ADC3) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR8_CC2_ADC3) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR8_CC4_ADC3) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR5_TRGO_ADC3) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR5_CC4_ADC3) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR1_CC2_ADC3))
+#else
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG)              (((INJTRIG) == ADC_ExternalTrigInjec_TMR3_CC4_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_Ext_INT15_TMR8_CC4_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR1_TRGO) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR1_CC4) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_None) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR15_TRGO))
+#endif
+
+                                        
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_channel_selection
+  * @{
+  */
+
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) == ADC_InjectedChannel_1) || \
+                                                     ((CHANNEL) == ADC_InjectedChannel_2) || \
+                                                     ((CHANNEL) == ADC_InjectedChannel_3) || \
+                                                     ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_selection
+  * @{
+  */
+
+#define ADC_AnalogWDG_SingleRegEnable               ((uint32_t)0x00800200)
+#define ADC_AnalogWDG_SingleInjecEnable             ((uint32_t)0x00400200)
+#define ADC_AnalogWDG_SingleRegOrInjecEnable        ((uint32_t)0x00C00200)
+#define ADC_AnalogWDG_AllRegEnable                  ((uint32_t)0x00800000)
+#define ADC_AnalogWDG_AllInjecEnable                ((uint32_t)0x00400000)
+#define ADC_AnalogWDG_AllRegAllInjecEnable          ((uint32_t)0x00C00000)
+#define ADC_AnalogWDG_None                          ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WDG(WDG)                      (((WDG) == ADC_AnalogWDG_SingleRegEnable) || \
+                                                     ((WDG) == ADC_AnalogWDG_SingleInjecEnable) || \
+                                                     ((WDG) == ADC_AnalogWDG_SingleRegOrInjecEnable) || \
+                                                     ((WDG) == ADC_AnalogWDG_AllRegEnable) || \
+                                                     ((WDG) == ADC_AnalogWDG_AllInjecEnable) || \
+                                                     ((WDG) == ADC_AnalogWDG_AllRegAllInjecEnable) || \
+                                                     ((WDG) == ADC_AnalogWDG_None))
+/**                                                 
+  * @}
+  */
+
+/** @defgroup ADC_interrupts_definition
+  * @{
+  */
+
+#define ADC_INT_EC                                  ((uint16_t)0x0220)
+#define ADC_INT_AWD                                 ((uint16_t)0x0140)
+#define ADC_INT_JEC                                 ((uint16_t)0x0480)
+
+#define IS_ADC_INT(INT)                             ((((INT) & (uint16_t)0xF81F) == 0x00) && ((INT) != 0x00))
+
+#define IS_ADC_GET_INT(INT)                         (((INT) == ADC_INT_EC) || ((INT) == ADC_INT_AWD) || \
+                                                     ((INT) == ADC_INT_JEC))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition
+  * @{
+  */
+
+#define ADC_FLAG_AWD                                ((uint8_t)0x01)
+#define ADC_FLAG_EC                                 ((uint8_t)0x02)
+#define ADC_FLAG_JEC                                ((uint8_t)0x04)
+#define ADC_FLAG_JSTR                               ((uint8_t)0x08)
+#define ADC_FLAG_RSTR                               ((uint8_t)0x10)
+#define IS_ADC_CLEAR_FLAG(FLAG)                     ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG)                       (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EC) || \
+                                                     ((FLAG) == ADC_FLAG_JEC) || ((FLAG)== ADC_FLAG_JSTR) || \
+                                                     ((FLAG) == ADC_FLAG_RSTR))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_thresholds
+  * @{
+  */
+
+#define IS_ADC_THRESHOLD(THRESHOLD)                 ((THRESHOLD) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_offset
+  * @{
+  */
+
+#define IS_ADC_OFFSET(OFFSET)                       ((OFFSET) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_length
+  * @{
+  */
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH)              (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_rank
+  * @{
+  */
+
+#define IS_ADC_INJECTED_RANK(RANK)                  (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup ADC_regular_length
+  * @{
+  */
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH)               (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_rank
+  * @{
+  */
+
+#define IS_ADC_REGULAR_RANK(RANK)                   (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_discontinuous_mode_number
+  * @{
+  */
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER)          (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions
+  * @{
+  */
+void ADC_SetInjectedOffset(ADC_Type* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionValue(ADC_Type* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_AnalogWDGCtrl(ADC_Type* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWDGThresholdsConfig(ADC_Type* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWDGSingleChannelConfig(ADC_Type* ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefintCtrl(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_Type* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_Type* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetINTStatus(ADC_Type* ADCx, uint16_t ADC_INT);
+void ADC_INTConfig(ADC_Type* ADCx, uint16_t ADC_INT, FunctionalState NewState);
+void ADC_RstCalibration(ADC_Type* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_Type* ADCx);
+void ADC_StartCalibration(ADC_Type* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_Type* ADCx);
+void ADC_SoftwareStartConvCtrl(ADC_Type* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Type* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_Type* ADCx, uint8_t Number);
+void ADC_DiscModeCtrl(ADC_Type* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_Type* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ClearINTPendingBit(ADC_Type* ADCx, uint16_t ADC_INT);
+void ADC_ExternalTrigConvCtrl(ADC_Type* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_Type* ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCtrl(ADC_Type* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCtrl(ADC_Type* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_Type* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCtrl(ADC_Type* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCtrl(ADC_Type* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCtrlStatus(ADC_Type* ADCx);
+void ADC_InjectedChannelConfig(ADC_Type* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_Type* ADCx, uint8_t Length);
+void ADC_Reset(ADC_Type* ADCx);
+void ADC_Init(ADC_Type* ADCx, ADC_InitType* ADC_InitStruct);
+void ADC_StructInit(ADC_InitType* ADC_InitStruct);
+void ADC_Ctrl(ADC_Type* ADCx, FunctionalState NewState);
+void ADC_DMACtrl(ADC_Type* ADCx, FunctionalState NewState);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4XX_ADC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_bkp.h

@@ -0,0 +1,197 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_bkp.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx BKP header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_BKP_H
+#define __AT32F4XX_BKP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup BKP
+  * @{
+  */
+
+/** @defgroup BKP_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Tamper_Pin_active_level
+  * @{
+  */
+
+#define BKP_TamperPinLv_H                   ((uint16_t)0x0000)
+#define BKP_TamperPinLv_L                   ((uint16_t)0x0001)
+
+#define IS_BKP_TAMPER_PIN_LV(LV)            (((LV) == BKP_TamperPinLv_H) || \
+                                             ((LV) == BKP_TamperPinLv_L))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
+  * @{
+  */
+
+#define BKP_RTCOutput_None                  ((uint16_t)0x0000)
+#define BKP_RTCOutput_CalClk                ((uint16_t)0x0080)
+#define BKP_RTCOutput_Alarm_Pulse           ((uint16_t)0x0100)
+#define BKP_RTCOutput_Second_Pulse          ((uint16_t)0x0300)
+#if defined (AT32F403Axx) || defined (AT32F407xx) 
+#define BKP_RTCOutput_Alarm_Toggle          ((uint16_t)0x0900)
+#define BKP_RTCOutput_Second_Toggle         ((uint16_t)0x0B00)
+#endif
+
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_BKP_RTC_OUTPUT_SEL(SEL)          (((SEL) == BKP_RTCOutput_None) || \
+                                             ((SEL) == BKP_RTCOutput_CalClk) || \
+                                             ((SEL) == BKP_RTCOutput_Alarm_Pulse) || \
+                                             ((SEL) == BKP_RTCOutput_Second_Pulse) || \
+                                             ((SEL) == BKP_RTCOutput_Alarm_Toggle) || \
+                                             ((SEL) == BKP_RTCOutput_Second_Toggle))
+#elif defined (AT32F403xx) || defined (AT32F413xx)
+#define IS_BKP_RTC_OUTPUT_SEL(SEL)          (((SEL) == BKP_RTCOutput_None) || \
+                                             ((SEL) == BKP_RTCOutput_CalClk) || \
+                                             ((SEL) == BKP_RTCOutput_Alarm_Pulse) || \
+                                             ((SEL) == BKP_RTCOutput_Second_Pulse))
+#endif																		 
+/**
+  * @}
+  */
+
+/** @defgroup Data_Backup_Register
+  * @{
+  */
+
+#define BKP_DT1                             ((uint16_t)0x0004)
+#define BKP_DT2                             ((uint16_t)0x0008)
+#define BKP_DT3                             ((uint16_t)0x000C)
+#define BKP_DT4                             ((uint16_t)0x0010)
+#define BKP_DT5                             ((uint16_t)0x0014)
+#define BKP_DT6                             ((uint16_t)0x0018)
+#define BKP_DT7                             ((uint16_t)0x001C)
+#define BKP_DT8                             ((uint16_t)0x0020)
+#define BKP_DT9                             ((uint16_t)0x0024)
+#define BKP_DT10                            ((uint16_t)0x0028)
+#define BKP_DT11                            ((uint16_t)0x0040)
+#define BKP_DT12                            ((uint16_t)0x0044)
+#define BKP_DT13                            ((uint16_t)0x0048)
+#define BKP_DT14                            ((uint16_t)0x004C)
+#define BKP_DT15                            ((uint16_t)0x0050)
+#define BKP_DT16                            ((uint16_t)0x0054)
+#define BKP_DT17                            ((uint16_t)0x0058)
+#define BKP_DT18                            ((uint16_t)0x005C)
+#define BKP_DT19                            ((uint16_t)0x0060)
+#define BKP_DT20                            ((uint16_t)0x0064)
+#define BKP_DT21                            ((uint16_t)0x0068)
+#define BKP_DT22                            ((uint16_t)0x006C)
+#define BKP_DT23                            ((uint16_t)0x0070)
+#define BKP_DT24                            ((uint16_t)0x0074)
+#define BKP_DT25                            ((uint16_t)0x0078)
+#define BKP_DT26                            ((uint16_t)0x007C)
+#define BKP_DT27                            ((uint16_t)0x0080)
+#define BKP_DT28                            ((uint16_t)0x0084)
+#define BKP_DT29                            ((uint16_t)0x0088)
+#define BKP_DT30                            ((uint16_t)0x008C)
+#define BKP_DT31                            ((uint16_t)0x0090)
+#define BKP_DT32                            ((uint16_t)0x0094)
+#define BKP_DT33                            ((uint16_t)0x0098)
+#define BKP_DT34                            ((uint16_t)0x009C)
+#define BKP_DT35                            ((uint16_t)0x00A0)
+#define BKP_DT36                            ((uint16_t)0x00A4)
+#define BKP_DT37                            ((uint16_t)0x00A8)
+#define BKP_DT38                            ((uint16_t)0x00AC)
+#define BKP_DT39                            ((uint16_t)0x00B0)
+#define BKP_DT40                            ((uint16_t)0x00B4)
+#define BKP_DT41                            ((uint16_t)0x00B8)
+#define BKP_DT42                            ((uint16_t)0x00BC)
+
+#define IS_BKP_DT(DT)                       (((DT) == BKP_DT1)  || ((DT) == BKP_DT2)  || ((DT) == BKP_DT3)  || \
+                                             ((DT) == BKP_DT4)  || ((DT) == BKP_DT5)  || ((DT) == BKP_DT6)  || \
+                                             ((DT) == BKP_DT7)  || ((DT) == BKP_DT8)  || ((DT) == BKP_DT9)  || \
+                                             ((DT) == BKP_DT10) || ((DT) == BKP_DT11) || ((DT) == BKP_DT12) || \
+                                             ((DT) == BKP_DT13) || ((DT) == BKP_DT14) || ((DT) == BKP_DT15) || \
+                                             ((DT) == BKP_DT16) || ((DT) == BKP_DT17) || ((DT) == BKP_DT18) || \
+                                             ((DT) == BKP_DT19) || ((DT) == BKP_DT20) || ((DT) == BKP_DT21) || \
+                                             ((DT) == BKP_DT22) || ((DT) == BKP_DT23) || ((DT) == BKP_DT24) || \
+                                             ((DT) == BKP_DT25) || ((DT) == BKP_DT26) || ((DT) == BKP_DT27) || \
+                                             ((DT) == BKP_DT28) || ((DT) == BKP_DT29) || ((DT) == BKP_DT30) || \
+                                             ((DT) == BKP_DT31) || ((DT) == BKP_DT32) || ((DT) == BKP_DT33) || \
+                                             ((DT) == BKP_DT34) || ((DT) == BKP_DT35) || ((DT) == BKP_DT36) || \
+                                             ((DT) == BKP_DT37) || ((DT) == BKP_DT38) || ((DT) == BKP_DT39) || \
+                                             ((DT) == BKP_DT40) || ((DT) == BKP_DT41) || ((DT) == BKP_DT42))
+
+#define IS_BKP_CAL_VAL(VAL)                 ((VAL) <= 0x7F)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Functions
+  * @{
+  */
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetIntStatus(void);
+void BKP_ClearIntPendingBit(void);
+void BKP_Reset(void);
+void BKP_SetRTCCalValue(uint8_t CalibrationValue);
+void BKP_WriteBackupReg(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupReg(uint16_t BKP_DR);
+void BKP_TamperPinLvConfig(uint16_t BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_IntConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_BKP_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_can.h

@@ -0,0 +1,688 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_can.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx CAN header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_CAN_H
+#define __AT32F4XX_CAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+/** @defgroup CAN_Exported_Types
+  * @{
+  */
+
+#if defined (AT32F403xx) || defined (AT32F415xx)
+#define IS_CAN_ALL_PERIPH(PERIPH)           ((PERIPH) == CAN1)
+#elif defined (AT32F413xx) || defined (AT32F403Axx) || \
+      defined (AT32F407xx)
+#if !defined (AT32FEBKCx_MD)
+#define IS_CAN_ALL_PERIPH(PERIPH)           (((PERIPH) == CAN1) || ((PERIPH) == CAN2))
+#else
+#define IS_CAN_ALL_PERIPH(PERIPH)           (((PERIPH) == CAN1))
+#endif
+#endif
+
+/**
+  * @brief  CAN init structure definition
+  */
+
+typedef struct
+{
+    uint16_t CAN_Prescaler;                 /*!< Specifies the length of a time quantum.
+                                               It ranges from 1 to 1024. */
+                                            
+    uint8_t CAN_Mode;                       /*!< Specifies the CAN operating mode.
+                                               This parameter can be a value of
+                                              @ref CAN_Mode */
+                                            
+    uint8_t CAN_SJW;                        /*!< Specifies the maximum number of time quanta
+                                               the CAN hardware is allowed to lengthen or
+                                               shorten a bit to perform resynchronization.
+                                               This parameter can be a value of
+                                               @ref CAN_synchronisation_jump_width */
+                                            
+    uint8_t CAN_BS1;                        /*!< Specifies the number of time quanta in Bit
+                                               Segment 1. This parameter can be a value of
+                                               @ref CAN_time_quantum_in_bit_segment_1 */
+                                            
+    uint8_t CAN_BS2;                        /*!< Specifies the number of time quanta in Bit
+                                               Segment 2.
+                                               This parameter can be a value of
+                                               @ref CAN_time_quantum_in_bit_segment_2 */
+                                            
+    FunctionalState CAN_TTC;                /*!< Enable or disable the time triggered
+                                               communication mode. This parameter can be set
+                                               either to ENABLE or DISABLE. */
+                                            
+    FunctionalState CAN_ABO;                /*!< Enable or disable the automatic bus-off
+                                                management. This parameter can be set either
+                                                to ENABLE or DISABLE. */
+                                            
+    FunctionalState CAN_AWU;                /*!< Enable or disable the automatic wake-up mode.
+                                                This parameter can be set either to ENABLE or
+                                                DISABLE. */
+                                            
+    FunctionalState CAN_NART;                /*!< Enable or disable the no-automatic
+                                                retransmission mode. This parameter can be
+                                                set either to ENABLE or DISABLE. */
+                                            
+    FunctionalState CAN_RFL;                /*!< Enable or disable the Receive FIFO Locked mode.
+                                                This parameter can be set either to ENABLE
+                                                or DISABLE. */
+                                            
+    FunctionalState CAN_TFP;                /*!< Enable or disable the transmit FIFO priority.
+                                                This parameter can be set either to ENABLE
+                                                or DISABLE. */
+} CAN_InitType;
+
+/**
+  * @brief  CAN filter init structure definition
+  */
+
+typedef struct
+{
+    uint16_t CAN_FilterIdHigh;              /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                                   configuration, first one for a 16-bit configuration).
+                                                   This parameter can be a value between 0x0000 and 0xFFFF */
+                                            
+    uint16_t CAN_FilterIdLow;               /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                                   configuration, second one for a 16-bit configuration).
+                                                   This parameter can be a value between 0x0000 and 0xFFFF */
+                                            
+    uint16_t CAN_FilterMskIdHigh;           /*!< Specifies the filter mask number or identification number,
+                                                    according to the mode (MSBs for a 32-bit configuration,
+                                                    first one for a 16-bit configuration).
+                                                    This parameter can be a value between 0x0000 and 0xFFFF */
+                                            
+    uint16_t CAN_FilterMskIdLow;            /*!< Specifies the filter mask number or identification number,
+                                                    according to the mode (LSBs for a 32-bit configuration,
+                                                    second one for a 16-bit configuration).
+                                                    This parameter can be a value between 0x0000 and 0xFFFF */
+
+    uint16_t CAN_FilterFIFOAssignment;      /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                                   This parameter can be a value of @ref CAN_filter_FIFO */
+                                            
+    uint8_t CAN_FilterNumber;               /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+                                            
+    uint8_t CAN_FilterMode;                 /*!< Specifies the filter mode to be initialized.
+                                                   This parameter can be a value of @ref CAN_filter_mode */
+                                            
+    uint8_t CAN_FilterScale;                /*!< Specifies the filter scale.
+                                                   This parameter can be a value of @ref CAN_filter_scale */
+
+    FunctionalState CAN_FilterActivation;   /*!< Enable or disable the filter.
+                                                This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitType;
+
+/**
+  * @brief  CAN Tx message structure definition
+  */
+
+typedef struct
+{
+    uint32_t StdId;                         /*!< Specifies the standard identifier.
+                                               This parameter can be a value between 0 to 0x7FF. */
+                                            
+    uint32_t ExtId;                         /*!< Specifies the extended identifier.
+                                               This parameter can be a value between 0 to 0x1FFFFFFF. */
+                                            
+    uint8_t IDT;                            /*!< Specifies the type of identifier for the message that
+                                               will be transmitted. This parameter can be a value
+                                               of @ref CAN_identifier_type */
+                                            
+    uint8_t RTR;                            /*!< Specifies the type of frame for the message that will
+                                               be transmitted. This parameter can be a value of
+                                               @ref CAN_remote_transmission_request */
+                                            
+    uint8_t DLC;                            /*!< Specifies the length of the frame that will be
+                                               transmitted. This parameter can be a value between
+                                               0 to 8 */
+                                            
+    uint8_t Data[8];                        /*!< Contains the data to be transmitted. It ranges from 0
+                                               to 0xFF. */
+} CanTxMsg;
+
+/**
+  * @brief  CAN Rx message structure definition
+  */
+
+typedef struct
+{
+    uint32_t StdId;                         /*!< Specifies the standard identifier.
+                                               This parameter can be a value between 0 to 0x7FF. */
+                                            
+    uint32_t ExtId;                         /*!< Specifies the extended identifier.
+                                               This parameter can be a value between 0 to 0x1FFFFFFF. */
+                                            
+    uint8_t IDT;                            /*!< Specifies the type of identifier for the message that
+                                               will be received. This parameter can be a value of
+                                               @ref CAN_identifier_type */
+                                            
+    uint8_t RTR;                            /*!< Specifies the type of frame for the received message.
+                                               This parameter can be a value of
+                                               @ref CAN_remote_transmission_request */
+                                            
+    uint8_t DLC;                            /*!< Specifies the length of the frame that will be received.
+                                               This parameter can be a value between 0 to 8 */
+                                            
+    uint8_t Data[8];                        /*!< Contains the data to be received. It ranges from 0 to
+                                               0xFF. */
+                                            
+    uint8_t FID;                            /*!< Specifies the index of the filter the message stored in
+                                               the mailbox passes through. This parameter can be a
+                                               value between 0 to 0xFF */
+} CanRxMsg;
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CAN_sleep_constants
+  * @{
+  */
+
+#define CAN_InitStatus_Failed               ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success              ((uint8_t)0x01) /*!< CAN initialization OK */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Mode
+  * @{
+  */
+
+#define CAN_Mode_Normal                     ((uint8_t)0x00)  /*!< normal mode */
+#define CAN_Mode_LoopBack                   ((uint8_t)0x01)  /*!< loopback mode */
+#define CAN_Mode_Silent                     ((uint8_t)0x02)  /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack            ((uint8_t)0x03)  /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE)                   (((MODE) == CAN_Mode_Normal) || \
+                                             ((MODE) == CAN_Mode_LoopBack)|| \
+                                             ((MODE) == CAN_Mode_Silent) || \
+                                             ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+  * @}
+  */
+
+
+/**
+  * @defgroup CAN_Operating_Mode
+  * @{
+  */
+#define CAN_OperatingMode_Initialization    ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal            ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep             ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE)         (((MODE) == CAN_OperatingMode_Initialization) ||\
+                                             ((MODE) == CAN_OperatingMode_Normal)|| \
+                                             ((MODE) == CAN_OperatingMode_Sleep))
+/**
+  * @}
+  */
+
+/**
+  * @defgroup CAN_Mode_Status
+  * @{
+  */
+
+#define CAN_ModeStatus_Failed               ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success              ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_synchronisation_jump_width
+  * @{
+  */
+
+#define CAN_SJW_1tq                         ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SJW_2tq                         ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_SJW_3tq                         ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_SJW_4tq                         ((uint8_t)0x03)  /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW)                     (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+                                             ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1
+  * @{
+  */
+
+#define CAN_BS1_1tq                         ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS1_2tq                         ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS1_3tq                         ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS1_4tq                         ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS1_5tq                         ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS1_6tq                         ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS1_7tq                         ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS1_8tq                         ((uint8_t)0x07)  /*!< 8 time quantum */
+#define CAN_BS1_9tq                         ((uint8_t)0x08)  /*!< 9 time quantum */
+#define CAN_BS1_10tq                        ((uint8_t)0x09)  /*!< 10 time quantum */
+#define CAN_BS1_11tq                        ((uint8_t)0x0A)  /*!< 11 time quantum */
+#define CAN_BS1_12tq                        ((uint8_t)0x0B)  /*!< 12 time quantum */
+#define CAN_BS1_13tq                        ((uint8_t)0x0C)  /*!< 13 time quantum */
+#define CAN_BS1_14tq                        ((uint8_t)0x0D)  /*!< 14 time quantum */
+#define CAN_BS1_15tq                        ((uint8_t)0x0E)  /*!< 15 time quantum */
+#define CAN_BS1_16tq                        ((uint8_t)0x0F)  /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1)                     ((BS1) <= CAN_BS1_16tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2
+  * @{
+  */
+
+#define CAN_BS2_1tq                         ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS2_2tq                         ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS2_3tq                         ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS2_4tq                         ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS2_5tq                         ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS2_6tq                         ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS2_7tq                         ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS2_8tq                         ((uint8_t)0x07)  /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2)                     ((BS2) <= CAN_BS2_8tq)
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_clock_prescaler
+  * @{
+  */
+
+#define IS_CAN_PRESCALER(PRESCALER)         (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_number
+  * @{
+  */
+#define IS_CAN_FILTER_NUMBER(NUMBER)        ((NUMBER) <= 13)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_mode
+  * @{
+  */
+
+#define CAN_FilterMode_IdMask               ((uint8_t)0x00)  /*!< identifier/mask mode */
+#define CAN_FilterMode_IdList               ((uint8_t)0x01)  /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE)            (((MODE) == CAN_FilterMode_IdMask) || \
+                                             ((MODE) == CAN_FilterMode_IdList))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_scale
+  * @{
+  */
+
+#define CAN_FilterScale_16bit               ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit               ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE)          (((SCALE) == CAN_FilterScale_16bit) || \
+                                             ((SCALE) == CAN_FilterScale_32bit))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_FIFO
+  * @{
+  */
+
+#define CAN_Filter_FIFO0                    ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1                    ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO)            (((FIFO) == CAN_FilterFIFO0) || \
+                                             ((FIFO) == CAN_FilterFIFO1))
+/**
+  * @}
+  */
+
+/** @defgroup Start_bank_filter_for_slave_CAN
+  * @{
+  */
+#define IS_CAN_BANKNUMBER(BANKNUMBER)       (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Tx
+  * @{
+  */
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX)     ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID)                         ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)                         ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)                             ((DLC) <= ((uint8_t)0x08))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_identifier_type
+  * @{
+  */
+
+#define CAN_Id_Standard                     ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_Id_Extended                     ((uint32_t)0x00000004)  /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE)               (((IDTYPE) == CAN_Id_Standard) || \
+                                             ((IDTYPE) == CAN_Id_Extended))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_remote_transmission_request
+  * @{
+  */
+
+#define CAN_RTR_Data                        ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_Remote                      ((uint32_t)0x00000002)  /*!< Remote frame */
+#define IS_CAN_RTR(RTR)                     (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_transmit_constants
+  * @{
+  */
+
+#define CAN_TxStatus_Failed                 ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok                     ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending                ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox              ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_receive_FIFO_number_constants
+  * @{
+  */
+
+#define CAN_FIFO0                           ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1                           ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO)                   (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_sleep_constants
+  * @{
+  */
+
+#define CAN_Sleep_Failed                    ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok                        ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_wake_up_constants
+  * @{
+  */
+
+#define CAN_WakeUp_Failed                   ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok                       ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+  * @}
+  */
+
+/**
+  * @defgroup   CAN_Error_Code_constants
+  * @{
+  */
+
+#define CAN_ErrorCode_NoErr                 ((uint8_t)0x00) /*!< No Error */
+#define	CAN_ErrorCode_StuffErr              ((uint8_t)0x10) /*!< Stuff Error */
+#define	CAN_ErrorCode_FormErr               ((uint8_t)0x20) /*!< Form Error */
+#define	CAN_ErrorCode_ACKErr                ((uint8_t)0x30) /*!< Acknowledgment Error */
+#define	CAN_ErrorCode_BitRecessiveErr       ((uint8_t)0x40) /*!< Bit Recessive Error */
+#define	CAN_ErrorCode_BitDominantErr        ((uint8_t)0x50) /*!< Bit Dominant Error */
+#define	CAN_ErrorCode_CRCErr                ((uint8_t)0x60) /*!< CRC Error  */
+#define	CAN_ErrorCode_SoftwareSetErr        ((uint8_t)0x70) /*!< Software Set Error */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags
+  * @{
+  */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+   and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function.  */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0                      ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1                      ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2                      ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_RFP0                       ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
+#define CAN_FLAG_RFFU0                      ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
+#define CAN_FLAG_RFOV0                      ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
+#define CAN_FLAG_RFP1                       ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
+#define CAN_FLAG_RFFU1                      ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
+#define CAN_FLAG_RFOV1                      ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WK                         ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SAK                        ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+         In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_ERG                        ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
+#define CAN_FLAG_ERP                        ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
+#define CAN_FLAG_BU                         ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
+#define CAN_FLAG_ERC                        ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG)               (((FLAG) == CAN_FLAG_ERC)   || ((FLAG) == CAN_FLAG_BU)   || \
+                                             ((FLAG) == CAN_FLAG_ERP)   || ((FLAG) == CAN_FLAG_ERG)   || \
+                                             ((FLAG) == CAN_FLAG_WK)    || ((FLAG) == CAN_FLAG_RFOV0)  || \
+                                             ((FLAG) == CAN_FLAG_RFFU0) || ((FLAG) == CAN_FLAG_RFP0)  || \
+                                             ((FLAG) == CAN_FLAG_RFOV1) || ((FLAG) == CAN_FLAG_RFFU1)   || \
+                                             ((FLAG) == CAN_FLAG_RFP1)  || ((FLAG) == CAN_FLAG_RQCP2) || \
+                                             ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
+                                             ((FLAG) == CAN_FLAG_SAK ))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)             (((FLAG) == CAN_FLAG_ERC)   || ((FLAG) == CAN_FLAG_RQCP2) || \
+                                             ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
+                                             ((FLAG) == CAN_FLAG_RFFU0) || ((FLAG) == CAN_FLAG_RFOV0) ||\
+                                             ((FLAG) == CAN_FLAG_RFFU1) || ((FLAG) == CAN_FLAG_RFOV1) || \
+                                             ((FLAG) == CAN_FLAG_WK)    || ((FLAG) == CAN_FLAG_SAK))
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_interrupts
+  * @{
+  */
+
+
+
+#define CAN_INT_TSME                        ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_INT_RFP0                        ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
+#define CAN_INT_RFFU0                       ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
+#define CAN_INT_RFOV0                       ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
+#define CAN_INT_RFP1                        ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
+#define CAN_INT_RFFU1                       ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
+#define CAN_INT_RFOV1                       ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_INT_WK                          ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_INT_SAK                         ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_INT_ERG                         ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_INT_ERP                         ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_INT_BU                          ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_INT_LEC                         ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_INT_ERR                         ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_INT_RQCP0                       CAN_INT_TSME
+#define CAN_INT_RQCP1                       CAN_INT_TSME
+#define CAN_INT_RQCP2                       CAN_INT_TSME
+
+
+#define IS_CAN_INT(INT)                     (((INT) == CAN_INT_TSME)  || ((INT) == CAN_INT_RFP0)  ||\
+                                             ((INT) == CAN_INT_RFFU0) || ((INT) == CAN_INT_RFOV0)  ||\
+                                             ((INT) == CAN_INT_RFP1)  || ((INT) == CAN_INT_RFFU1)   ||\
+                                             ((INT) == CAN_INT_RFOV1) || ((INT) == CAN_INT_ERG)   ||\
+                                             ((INT) == CAN_INT_ERP)   || ((INT) == CAN_INT_BU)   ||\
+                                             ((INT) == CAN_INT_LEC)   || ((INT) == CAN_INT_ERR)   ||\
+                                             ((INT) == CAN_INT_WK)    || ((INT) == CAN_INT_SAK))
+
+#define IS_CAN_CLEAR_INT(INT)               (((INT) == CAN_INT_TSME)  || ((INT) == CAN_INT_RFFU0)    ||\
+                                             ((INT) == CAN_INT_RFOV0) || ((INT) == CAN_INT_RFFU1)    ||\
+                                             ((INT) == CAN_INT_RFOV1) || ((INT) == CAN_INT_ERG)    ||\
+                                             ((INT) == CAN_INT_ERP)   || ((INT) == CAN_INT_BU)    ||\
+                                             ((INT) == CAN_INT_LEC)   || ((INT) == CAN_INT_ERR)    ||\
+                                             ((INT) == CAN_INT_WK)    || ((INT) == CAN_INT_SAK))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Legacy
+  * @{
+  */
+#define CANINITFAILED                       CAN_InitStatus_Failed
+#define CANINITOK                           CAN_InitStatus_Success
+#define CAN_FilterFIFO0                     CAN_Filter_FIFO0
+#define CAN_FilterFIFO1                     CAN_Filter_FIFO1
+#define CAN_ID_STD                          CAN_Id_Standard
+#define CAN_ID_EXT                          CAN_Id_Extended
+#define CAN_RTR_DATA                        CAN_RTR_Data
+#define CAN_RTR_REMOTE                      CAN_RTR_Remote
+#define CANTXFAILE                          CAN_TxStatus_Failed
+#define CANTXOK                             CAN_TxStatus_Ok
+#define CANTXPENDING                        CAN_TxStatus_Pending
+#define CAN_NO_MB                           CAN_TxStatus_NoMailBox
+#define CANSLEEPFAILED                      CAN_Sleep_Failed
+#define CANSLEEPOK                          CAN_Sleep_Ok
+#define CANWAKEUPFAILED                     CAN_WakeUp_Failed
+#define CANWAKEUPOK                         CAN_WakeUp_Ok
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions
+  * @{
+  */
+  
+/* Interrupts and flags management functions **********************************/
+void CAN_INTConfig(CAN_Type* CANx, uint32_t CAN_INT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_Type* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_Type* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetINTStatus(CAN_Type* CANx, uint32_t CAN_INT);
+void CAN_ClearINTPendingBit(CAN_Type* CANx, uint32_t CAN_INT);
+
+/*  Function used to set the CAN configuration to the default reset state *****/
+void CAN_Reset(CAN_Type* CANx);
+
+/* Receive functions **********************************************************/
+void CAN_Receive(CAN_Type* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_Type* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_Type* CANx, uint8_t FIFONumber);
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_Type* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_Type* CANx);
+uint8_t CAN_WakeUp(CAN_Type* CANx);
+
+/* Error management functions *************************************************/
+uint8_t CAN_GetLastErrorCode(CAN_Type* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_Type* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_Type* CANx);
+
+/* Initialization and Configuration functions *********************************/
+uint8_t CAN_Init(CAN_Type* CANx, CAN_InitType* CAN_InitStruct);
+void CAN_FilterInit(CAN_Type* CANx, CAN_FilterInitType* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitType* CAN_InitStruct);
+void CAN_DBGFreeze(CAN_Type* CANx, FunctionalState NewState);
+void CAN_TTComModeCtrl(CAN_Type* CANx, FunctionalState NewState);
+
+/* Transmit functions *********************************************************/
+uint8_t CAN_Transmit(CAN_Type* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_Type* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_Type* CANx, uint8_t Mailbox);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_CAN_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_comp.h

@@ -0,0 +1,358 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_comp.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx COMP header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_COMP_H
+#define __AT32F4XX_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup AT32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup COMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  COMP Init structure definition  
+  */
+  
+typedef struct
+{
+
+  uint32_t COMP_INMInput;     /*!< Selects the inverting input of the comparator.
+                                          This parameter can be a value of @ref COMP_INMInput */
+
+  uint32_t COMP_Output;             /*!< Selects the output redirection of the comparator.
+                                          This parameter can be a value of @ref COMP_Output */
+
+  uint32_t COMP_OutPolarity;           /*!< Selects the output polarity of the comparator.
+                                          This parameter can be a value of @ref COMP_OutputPolarity */
+
+  uint32_t COMP_Hysteresis;         /*!< Selects the hysteresis voltage of the comparator.
+                                          This parameter can be a value of @ref COMP_Hysteresis */
+
+  uint32_t COMP_Mode;               /*!< Selects the operating mode of the comparator
+                                         and allows to adjust the speed/consumption.
+                                          This parameter can be a value of @ref COMP_Mode */
+
+}COMP_InitType;
+
+/* Exported constants --------------------------------------------------------*/
+   
+/** @defgroup COMP_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup COMP_Selection
+  * @{
+  */
+
+#define COMP1_Selection                    ((uint32_t)0x00000000) /*!< COMP1 Selection */
+#ifndef AT32F421xx
+#define COMP2_Selection                    ((uint32_t)0x00000010) /*!< COMP2 Selection */
+#endif
+
+#ifdef AT32F421xx
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP1_Selection))
+#else
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP1_Selection) || \
+                                    ((PERIPH) == COMP2_Selection))
+#endif
+
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_NonInvertingInput
+  * @{
+  */
+#ifdef AT32F421xx
+#define COMP_INPInput_00               ((uint32_t)0x00000000) /*!< PA5 connected to comparator1 non-inverting input */
+#define COMP_INPInput_01               ((uint32_t)0x00000080) /*!< PA1 connected to comparator1 non-inverting input */
+#define COMP_INPInput_10               ((uint32_t)0x00000100) /*!< PA0 connected to comparator1 non-inverting input */
+#define COMP_INPInput_11               ((uint32_t)0x00000180) /*!< VSSA connected to comparator1 non-inverting input */
+#define IS_COMP_NONINVERTING_INPUT(INPUT) (((INPUT) == COMP_INPInput_00) || \
+                                          ((INPUT) == COMP_INPInput_01) || \
+                                          ((INPUT) == COMP_INPInput_10) || \
+                                          ((INPUT) == COMP_INPInput_11))
+#else
+#define COMP_INPInput_00               ((uint32_t)0x00000000) /*!< PA5/PA7 connected to comparator1/2 non-inverting input */
+#define COMP_INPInput_01               ((uint32_t)0x00000001) /*!< PA1/PA3 connected to comparator1/2 non-inverting input */
+#define COMP_INPInput_10               ((uint32_t)0x00000002) /*!< PA0/PA2 connected to comparator1/2 non-inverting input */
+#define IS_COMP_NONINVERTING_INPUT(INPUT) (((INPUT) == COMP_INPInput_00) || \
+                                          ((INPUT) == COMP_INPInput_01) || \
+                                          ((INPUT) == COMP_INPInput_10))
+#endif
+
+
+/** @defgroup COMP_InvertingInput
+  * @{
+  */
+
+#define COMP_INMInput_1_4VREFINT          ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
+#define COMP_INMInput_1_2VREFINT          ((uint32_t)0x00000010) /*!< 1/2 VREFINT connected to comparator inverting input */
+#define COMP_INMInput_3_4VREFINT          ((uint32_t)0x00000020) /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_INMInput_VREFINT             ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
+#define COMP_INMInput_IN1                 ((uint32_t)0x00000040) /*!< I/O (PA4 for COMP1 and PA3 for COMP2) connected to comparator inverting input */
+#define COMP_INMInput_IN2                 ((uint32_t)0x00000050) /*!< I/O (PA5 for COMP1 and PA7 for COMP2) connected to comparator inverting input */
+#define COMP_INMInput_IN3                 ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */
+#ifdef AT32F421xx
+#define COMP_INMInput_IN4                 ((uint32_t)0x00000070) /*!< I/O (PA2 for COMP1) connected to comparator inverting input */
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_INMInput_1_4VREFINT) || \
+                                        ((INPUT) == COMP_INMInput_1_2VREFINT) || \
+                                        ((INPUT) == COMP_INMInput_3_4VREFINT) || \
+                                        ((INPUT) == COMP_INMInput_VREFINT)    || \
+                                        ((INPUT) == COMP_INMInput_IN1)        || \
+                                        ((INPUT) == COMP_INMInput_IN2)        || \
+                                        ((INPUT) == COMP_INMInput_IN3)        || \
+                                        ((INPUT) == COMP_INMInput_IN4))
+#else
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_INMInput_1_4VREFINT) || \
+                                        ((INPUT) == COMP_INMInput_1_2VREFINT) || \
+                                        ((INPUT) == COMP_INMInput_3_4VREFINT) || \
+                                        ((INPUT) == COMP_INMInput_VREFINT)    || \
+                                        ((INPUT) == COMP_INMInput_IN1)        || \
+                                        ((INPUT) == COMP_INMInput_IN2)        || \
+                                        ((INPUT) == COMP_INMInput_IN3))
+#endif
+
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup COMP_Output
+  * @{
+  */
+
+#define COMP_Output_None                  ((uint32_t)0x00000000)   /*!< COMP output isn't connected to other peripherals */
+#ifdef AT32F421xx
+#define COMP_Output_TMR1BKIN              ((uint32_t)0x00000400)   /*!< COMP output connected to TIM1 Break Input (BKIN) */
+#define COMP_Output_TMR1IC1               ((uint32_t)0x00000800)   /*!< COMP output connected to TIM1 Input Capture 1 */
+#define COMP_Output_TMR1OCREFCLR          ((uint32_t)0x00000C00)   /*!< COMP output connected to TIM1 OCREF Clear */
+#define COMP_Output_TMR3IC1               ((uint32_t)0x00001800)   /*!< COMP output connected to TIM3 Input Capture 1 */
+#define COMP_Output_TMR3OCREFCLR          ((uint32_t)0x00001C00)   /*!< COMP output connected to TIM3 OCREF Clear */
+#else
+#define COMP_Output_TMR1BKIN              ((uint32_t)0x00000100)   /*!< COMP output connected to TIM1 Break Input (BKIN) */
+#define COMP_Output_TMR1IC1               ((uint32_t)0x00000200)   /*!< COMP output connected to TIM1 Input Capture 1 */
+#define COMP_Output_TMR1OCREFCLR          ((uint32_t)0x00000300)   /*!< COMP output connected to TIM1 OCREF Clear */
+#define COMP_Output_TMR2IC4               ((uint32_t)0x00000400)   /*!< COMP output connected to TIM2 Input Capture 4 */
+#define COMP_Output_TMR2OCREFCLR          ((uint32_t)0x00000500)   /*!< COMP output connected to TIM2 OCREF Clear */
+#define COMP_Output_TMR3IC1               ((uint32_t)0x00000600)   /*!< COMP output connected to TIM3 Input Capture 1 */
+#define COMP_Output_TMR3OCREFCLR          ((uint32_t)0x00000700)   /*!< COMP output connected to TIM3 OCREF Clear */
+#endif
+
+#ifdef AT32F421xx
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None)         || \
+                                ((OUTPUT) == COMP_Output_TMR1BKIN)     || \
+                                ((OUTPUT) == COMP_Output_TMR1IC1)      || \
+                                ((OUTPUT) == COMP_Output_TMR1OCREFCLR) || \
+                                ((OUTPUT) == COMP_Output_TMR3IC1)      || \
+                                ((OUTPUT) == COMP_Output_TMR3OCREFCLR))
+#else
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None)         || \
+                                ((OUTPUT) == COMP_Output_TMR1BKIN)     || \
+                                ((OUTPUT) == COMP_Output_TMR1IC1)      || \
+                                ((OUTPUT) == COMP_Output_TMR1OCREFCLR) || \
+                                ((OUTPUT) == COMP_Output_TMR2IC4)      || \
+                                ((OUTPUT) == COMP_Output_TMR2OCREFCLR) || \
+                                ((OUTPUT) == COMP_Output_TMR3IC1)      || \
+                                ((OUTPUT) == COMP_Output_TMR3OCREFCLR))
+#endif
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_OutputPolarity
+  * @{
+  */
+#define COMP_OutPolarity_NonInverted          ((uint32_t)0x00000000)  /*!< COMP output on GPIO isn't inverted */
+#define COMP_OutPolarity_Inverted             COMP_CTRLSTS_COMP1POL       /*!< COMP output on GPIO is inverted */
+
+#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutPolarity_NonInverted)  || \
+                                 ((POL) == COMP_OutPolarity_Inverted))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_Hysteresis
+  * @{
+  */
+/* Please refer to the electrical characteristics in the device datasheet for
+   the hysteresis level */
+#define COMP_Hysteresis_No                         ((uint32_t)0x00000000)   /*!< No hysteresis */
+#define COMP_Hysteresis_Low                        COMP_CTRLSTS_COMP1HYST_0 /*!< Hysteresis level low */
+#define COMP_Hysteresis_Medium                     COMP_CTRLSTS_COMP1HYST_1 /*!< Hysteresis level medium */
+#define COMP_Hysteresis_High                       COMP_CTRLSTS_COMP1HYST   /*!< Hysteresis level high */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS)    (((HYSTERESIS) == COMP_Hysteresis_No) || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_Low) || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_Medium) || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_High))
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Mode
+  * @{
+  */
+/* Please refer to the electrical characteristics in the device datasheet for
+   the power consumption values */
+#define COMP_Mode_Fast                     ((uint32_t)0x00000000)  /*!< High Speed */
+#ifdef AT32F421xx
+#define COMP_Mode_Medium                   COMP_CTRLSTS_COMP1MDE_0 /*!< Low power mode */
+#define COMP_Mode_Slow                     COMP_CTRLSTS_COMP1MDE_1 /*!< Low power mode */
+#define COMP_Mode_Very_Slow                COMP_CTRLSTS_COMP1MDE /*!< Low power mode */
+#define IS_COMP_MODE(MODE)    (((MODE) == COMP_Mode_Fast)      || \
+                               ((MODE) == COMP_Mode_Medium)    || \
+                               ((MODE) == COMP_Mode_Slow)      || \
+                               ((MODE) == COMP_Mode_Very_Slow))
+#else
+#define COMP_Mode_Slow                     COMP_CTRLSTS_COMP1MDE /*!< Low power mode */
+#define IS_COMP_MODE(MODE)    (((MODE) == COMP_Mode_Fast)    || \
+                               ((MODE) == COMP_Mode_Slow))
+#endif
+
+/**
+  * @}
+  */
+  
+/** @defgroup COMP_SCAL_BRG
+  * @{
+  */
+/* Please refer to the electrical characteristics in the device datasheet for
+   the SCAL and BRG */
+#define COMP_SCAL_BRG_00            ((uint32_t)0x00000000)
+#define COMP_SCAL_BRG_10            COMP_CTRLSTS_COMP1SCALEN
+#define COMP_SCAL_BRG_11            (COMP_CTRLSTS_COMP1SCALEN | COMP_CTRLSTS_COMP1BRGEN)
+
+#define IS_COMP_SCAL_BRG(MODE)    (((SCAL_BRG) == COMP_SCAL_BRG_00)    || \
+                                   ((SCAL_BRG) == COMP_SCAL_BRG_10)    || \
+                                   ((SCAL_BRG) == COMP_SCAL_BRG_11))
+/**
+  * @}
+  */
+  
+/** @defgroup COMP_OutputLevel
+  * @{
+  */ 
+/* When output polarity is not inverted, comparator output is high when
+   the non-inverting input is at a higher voltage than the inverting input */
+#define COMP_OutputState_High                   COMP_CTRLSTS_COMP1OUT
+/* When output polarity is not inverted, comparator output is low when
+   the non-inverting input is at a lower voltage than the inverting input*/
+#define COMP_OutputState_Low                    ((uint32_t)0x00000000)
+
+/**
+  * @}
+  */ 
+
+#ifdef AT32F421xx
+/** @defgroup COMP_High_Pulse_Filter
+  * @{
+  */        
+  
+#define IS_COMP_HighPulseCnt(HighPulse)          ((HighPulse) <= 0x3F)
+/**
+  * @}
+  */
+  
+/** @defgroup COMP_Low_Pulse_Filter
+  * @{
+  */        
+  
+#define IS_COMP_LowPulseCnt(LowPulse)            ((LowPulse) <= 0x3F)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Blanking
+  * @{
+  */
+/* Please refer to the electrical characteristics in the device datasheet for
+   the blanking source */
+#define COMP_Blanking_None                       ((uint32_t)0x00000000)
+#define COMP_Blanking_TMR1OC4                    ((uint32_t)0x00040000)
+#define COMP_Blanking_TMR3OC3                    ((uint32_t)0x000C0000)
+#define COMP_Blanking_TMR15OC2                   ((uint32_t)0x00100000)
+#define COMP_Blanking_TMR15OC1                   ((uint32_t)0x00180000)
+
+#define IS_COMP_BLANKING(Blanking)    (((Blanking) == COMP_Blanking_None)       || \
+                                       ((Blanking) == COMP_Blanking_TMR1OC4)    || \
+                                       ((Blanking) == COMP_Blanking_TMR3OC3)    || \
+                                       ((Blanking) == COMP_Blanking_TMR15OC2)   || \
+                                       ((Blanking) == COMP_Blanking_TMR15OC1))
+/**
+  * @}
+  */
+#endif
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the COMP configuration to the default reset state ****/
+void COMP_Reset(void);
+
+/* Initialization and Configuration functions *********************************/
+void COMP_Init(uint32_t COMP_Selection, COMP_InitType* COMP_InitStruct);
+void COMP_SelectINPInput(uint32_t COMP_Selection, uint32_t COMP_INPInput);
+void COMP_StructInit(COMP_InitType* COMP_InitStruct);
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
+void COMP_SwitchCmd(FunctionalState NewState);
+uint32_t COMP_GetOutputState(uint32_t COMP_Selection);
+
+#ifdef AT32F415
+/* Window mode control function ***********************************************/
+void COMP_WindowCmd(FunctionalState NewState);
+#endif
+
+/* COMP configuration locking function ****************************************/
+void COMP_LockConfig(uint32_t COMP_Selection);
+
+#ifdef AT32F421xx
+/* COMP configuration glitch filter ****************************************/
+void COMP_FilterConfig(uint16_t COMP_HighPulseCnt, uint16_t COMP_LowPulseCnt, FunctionalState NewState);
+
+/* COMP configuration blanking source ****************************************/
+void COMP_BlankingConfig(uint32_t Blank_Selection);
+
+/* COMP configuration SCAL BRG ****************************************/
+void COMP_SCAL_BRGConfig(uint32_t SCAL_BRG);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4XX_COMP_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+

StdPeriph_Driver/inc/at32f4xx_crc.h

@@ -0,0 +1,82 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_crc.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx CRC header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_CRC_H
+#define __AT32F4XX_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/** @defgroup CRC_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions
+  * @{
+  */
+void CRC_SetIDTReg(uint8_t IDValue);
+uint8_t CRC_GetIDTReg(void);
+void CRC_ResetDT(void);
+uint32_t CRC_CalculateCRC(uint32_t Data);
+uint32_t CRC_CalculateBlkCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_CRC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_dac.h

@@ -0,0 +1,268 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_dac.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx DAC header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_DAC_H
+#define __AT32F4XX_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/** @defgroup DAC_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  DAC Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t DAC_Trigger;                           /*!< Specifies the external trigger for the selected DAC channel.
+                                                       This parameter can be a value of @ref DAC_trigger_selection */
+                                                    
+    uint32_t DAC_WaveGeneration;                    /*!< Specifies whether DAC channel noise waves or triangle waves
+                                                       are generated, or whether no wave is generated.
+                                                       This parameter can be a value of @ref DAC_wave_generation */
+                                                    
+    uint32_t DAC_LFSRUnmask_TriangleAmplitude;      /*!< Specifies the LFSR mask for noise wave generation or
+                                                       the maximum amplitude triangle generation for the DAC channel.
+                                                       This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+                                                    
+    uint32_t DAC_OutputBuffer;                      /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                       This parameter can be a value of @ref DAC_output_buffer */
+} DAC_InitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DAC_trigger_selection
+  * @{
+  */
+
+#define DAC_Trigger_None                    ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_Trigger_TMR6_TRGO               ((uint32_t)0x00000004) /*!< TMR6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_TMR8_TRGO               ((uint32_t)0x0000000C) /*!< TMR8 TRGO selected as external conversion trigger for DAC channel
+                                                                      only in High-density devices*/
+#define DAC_Trigger_TMR7_TRGO               ((uint32_t)0x00000014) /*!< TMR7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_TMR5_TRGO               ((uint32_t)0x0000001C) /*!< TMR5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_TMR2_TRGO               ((uint32_t)0x00000024) /*!< TMR2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_TMR4_TRGO               ((uint32_t)0x0000002C) /*!< TMR4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_INT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software                ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER)             (((TRIGGER) == DAC_Trigger_None) || \
+                                             ((TRIGGER) == DAC_Trigger_TMR6_TRGO) || \
+                                             ((TRIGGER) == DAC_Trigger_TMR8_TRGO) || \
+                                             ((TRIGGER) == DAC_Trigger_TMR7_TRGO) || \
+                                             ((TRIGGER) == DAC_Trigger_TMR5_TRGO) || \
+                                             ((TRIGGER) == DAC_Trigger_TMR2_TRGO) || \
+                                             ((TRIGGER) == DAC_Trigger_TMR4_TRGO) || \
+                                             ((TRIGGER) == DAC_Trigger_Ext_INT9) || \
+                                             ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation
+  * @{
+  */
+
+#define DAC_WaveGeneration_None             ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise            ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle         ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE)          (((WAVE) == DAC_WaveGeneration_None) || \
+                                             ((WAVE) == DAC_WaveGeneration_Noise) || \
+                                             ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+  * @{
+  */
+
+#define DAC_LFSRUnmsk_Bit0                  ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmsk_Bits1_0               ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits2_0               ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits3_0               ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits4_0               ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits5_0               ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits6_0               ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits7_0               ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits8_0               ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits9_0               ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits10_0              ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits11_0              ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmp_1                   ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmp_3                   ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmp_7                   ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmp_15                  ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmp_31                  ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmp_63                  ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmp_127                 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmp_255                 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmp_511                 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmp_1023                ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmp_2047                ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmp_4095                ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)    (((VALUE) == DAC_LFSRUnmsk_Bit0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits1_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits2_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits3_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits4_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits5_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits6_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits7_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits8_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits9_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits10_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits11_0) || \
+                                                         ((VALUE) == DAC_TriangleAmp_1) || \
+                                                         ((VALUE) == DAC_TriangleAmp_3) || \
+                                                         ((VALUE) == DAC_TriangleAmp_7) || \
+                                                         ((VALUE) == DAC_TriangleAmp_15) || \
+                                                         ((VALUE) == DAC_TriangleAmp_31) || \
+                                                         ((VALUE) == DAC_TriangleAmp_63) || \
+                                                         ((VALUE) == DAC_TriangleAmp_127) || \
+                                                         ((VALUE) == DAC_TriangleAmp_255) || \
+                                                         ((VALUE) == DAC_TriangleAmp_511) || \
+                                                         ((VALUE) == DAC_TriangleAmp_1023) || \
+                                                         ((VALUE) == DAC_TriangleAmp_2047) || \
+                                                         ((VALUE) == DAC_TriangleAmp_4095))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer
+  * @{
+  */
+
+#define DAC_OutputBuffer_Enable             ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable            ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE)   (((STATE) == DAC_OutputBuffer_Enable) || \
+                                             ((STATE) == DAC_OutputBuffer_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection
+  * @{
+  */
+
+#define DAC_Channel_1                       ((uint32_t)0x00000000)
+#define DAC_Channel_2                       ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL)             (((CHANNEL) == DAC_Channel_1) || \
+                                             ((CHANNEL) == DAC_Channel_2))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignment
+  * @{
+  */
+
+#define DAC_Align_12b_Right                 ((uint32_t)0x00000000)
+#define DAC_Align_12b_Left                  ((uint32_t)0x00000004)
+#define DAC_Align_8b_Right                  ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN)                 (((ALIGN) == DAC_Align_12b_Right) || \
+                                             ((ALIGN) == DAC_Align_12b_Left) || \
+                                             ((ALIGN) == DAC_Align_8b_Right))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation
+  * @{
+  */
+
+#define DAC_Wave_Noise                      ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                   ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE)                   (((WAVE) == DAC_Wave_Noise) || \
+                                             ((WAVE) == DAC_Wave_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data
+  * @{
+  */
+
+#define IS_DAC_DATA(DATA)                   ((DATA) <= 0xFFF0)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions
+  * @{
+  */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+void DAC_Reset(void);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitType* DAC_InitStruct);
+void DAC_StructInit(DAC_InitType* DAC_InitStruct);
+void DAC_WaveGenerationCtrl(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_Ctrl(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DMACtrl(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCtrl(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCtrl(FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4XX_DAC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_dbgmcu.h

@@ -0,0 +1,162 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_dbgmcu.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx MCUDBG header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_MCUDBG_H
+#define __AT32F4XX_MCUDBG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MCUDBG
+  * @{
+  */
+
+/** @defgroup MCUDBG_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MCUDBG_Exported_Constants
+  * @{
+  */
+
+#define MCUDBG_SLEEP                        ((uint32_t)0x00000001)
+#define MCUDBG_STOP                         ((uint32_t)0x00000002)
+#define MCUDBG_STANDBY                      ((uint32_t)0x00000004)
+#define MCUDBG_IWDG_STOP                    ((uint32_t)0x00000100)
+#define MCUDBG_WWDG_STOP                    ((uint32_t)0x00000200)
+#define MCUDBG_TMR1_STOP                    ((uint32_t)0x00000400)
+#define MCUDBG_TMR3_STOP                    ((uint32_t)0x00001000)
+#define MCUDBG_I2C1_SMBUS_TIMEOUT           ((uint32_t)0x00008000)
+#define MCUDBG_I2C2_SMBUS_TIMEOUT           ((uint32_t)0x00010000)
+
+#if defined (AT32F403xx)
+#define MCUDBG_TMR2_STOP                    ((uint32_t)0x00000800)
+#define MCUDBG_TMR4_STOP                    ((uint32_t)0x00002000)
+#define MCUDBG_CAN1_STOP                    ((uint32_t)0x00004000)
+#define MCUDBG_TMR8_STOP                    ((uint32_t)0x00020000)
+#define MCUDBG_TMR5_STOP                    ((uint32_t)0x00040000)
+#define MCUDBG_TMR6_STOP                    ((uint32_t)0x00080000)
+#define MCUDBG_TMR7_STOP                    ((uint32_t)0x00100000)
+#define MCUDBG_TMR15_STOP                   ((uint32_t)0x00400000)
+#define MCUDBG_TMR12_STOP                   ((uint32_t)0x02000000)
+#define MCUDBG_TMR13_STOP                   ((uint32_t)0x04000000)
+#define MCUDBG_TMR14_STOP                   ((uint32_t)0x08000000)
+#define MCUDBG_TMR9_STOP                    ((uint32_t)0x10000000)
+#define MCUDBG_TMR10_STOP                   ((uint32_t)0x20000000)
+#define MCUDBG_TMR11_STOP                   ((uint32_t)0x40000000)
+#define MCUDBG_I2C3_SMBUS_TIMEOUT           ((uint32_t)0x80000000)
+#define IS_MCUDBG_PERIPH(PERIPH)            ((((PERIPH) & 0x01A000F8) == 0x00) && ((PERIPH) != 0x00))
+#endif
+
+#if defined (AT32F413xx)
+#define MCUDBG_TMR2_STOP                    ((uint32_t)0x00000800)
+#define MCUDBG_TMR4_STOP                    ((uint32_t)0x00002000)
+#define MCUDBG_CAN1_STOP                    ((uint32_t)0x00004000)
+#define MCUDBG_TMR8_STOP                    ((uint32_t)0x00020000)
+#define MCUDBG_TMR5_STOP                    ((uint32_t)0x00040000)
+#define MCUDBG_CAN2_STOP                    ((uint32_t)0x00200000)
+#define MCUDBG_TMR9_STOP                    ((uint32_t)0x10000000)
+#define MCUDBG_TMR10_STOP                   ((uint32_t)0x20000000)
+#define MCUDBG_TMR11_STOP                   ((uint32_t)0x40000000)
+#define IS_MCUDBG_PERIPH(PERIPH)            ((((PERIPH) & 0x8FD800F8) == 0x00) && ((PERIPH) != 0x00))
+#endif
+
+#if defined (AT32F415xx)
+#define MCUDBG_TMR2_STOP                    ((uint32_t)0x00000800)
+#define MCUDBG_TMR4_STOP                    ((uint32_t)0x00002000)
+#define MCUDBG_CAN1_STOP                    ((uint32_t)0x00004000)
+#define MCUDBG_TMR5_STOP                    ((uint32_t)0x00040000)
+#define MCUDBG_TMR9_STOP                    ((uint32_t)0x10000000)
+#define MCUDBG_TMR10_STOP                   ((uint32_t)0x20000000)
+#define MCUDBG_TMR11_STOP                   ((uint32_t)0x40000000)
+#define IS_MCUDBG_PERIPH(PERIPH)            ((((PERIPH) & 0x8FFE00F8) == 0x00) && ((PERIPH) != 0x00))
+#endif
+
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+#define MCUDBG_TMR2_STOP                    ((uint32_t)0x00000800)
+#define MCUDBG_TMR4_STOP                    ((uint32_t)0x00002000)
+#define MCUDBG_CAN1_STOP                    ((uint32_t)0x00004000)
+#define MCUDBG_TMR8_STOP                    ((uint32_t)0x00020000)
+#define MCUDBG_TMR5_STOP                    ((uint32_t)0x00040000)
+#define MCUDBG_TMR6_STOP                    ((uint32_t)0x00080000)
+#define MCUDBG_TMR7_STOP                    ((uint32_t)0x00100000)
+#define MCUDBG_CAN2_STOP                    ((uint32_t)0x00200000)
+#define MCUDBG_TMR12_STOP                   ((uint32_t)0x02000000)
+#define MCUDBG_TMR13_STOP                   ((uint32_t)0x04000000)
+#define MCUDBG_TMR14_STOP                   ((uint32_t)0x08000000)
+#define MCUDBG_TMR9_STOP                    ((uint32_t)0x10000000)
+#define MCUDBG_TMR10_STOP                   ((uint32_t)0x20000000)
+#define MCUDBG_TMR11_STOP                   ((uint32_t)0x40000000)
+#define MCUDBG_I2C3_SMBUS_TIMEOUT           ((uint32_t)0x80000000)
+#define IS_MCUDBG_PERIPH(PERIPH)            ((((PERIPH) & 0x01C000F8) == 0x00) && ((PERIPH) != 0x00))
+#endif
+
+#if defined (AT32F421xx)
+#define MCUDBG_ERTC_STOP                    ((uint32_t)0x00004000)
+#define MCUDBG_TMR6_STOP                    ((uint32_t)0x00080000)
+#define MCUDBG_ERTC_512_STOP                ((uint32_t)0x00200000)
+#define MCUDBG_TMR15_STOP                   ((uint32_t)0x00400000)
+#define MCUDBG_TMR16_STOP                   ((uint32_t)0x00800000)
+#define MCUDBG_TMR17_STOP                   ((uint32_t)0x01000000)
+#define MCUDBG_TMR14_STOP                   ((uint32_t)0x08000000)
+#define IS_MCUDBG_PERIPH(PERIPH)            ((((PERIPH) & 0xF61628F8) == 0x00) && ((PERIPH) != 0x00))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup MCUDBG_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MCUDBG_Exported_Functions
+  * @{
+  */
+
+uint32_t MCUDBG_GetRevID(void);
+uint32_t MCUDBG_GetDevID(void);
+void MCUDBG_PeriphDebugModeConfig(uint32_t MCUDBG_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_MCUDBG_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_dma.h

@@ -0,0 +1,622 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_dma.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx DMA header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_DMA_H
+#define __AT32F4XX_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  DMA Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t DMA_PeripheralBaseAddr;        /*!< Specifies the peripheral base address for DMAy Channelx. */
+                                            
+    uint32_t DMA_MemoryBaseAddr;            /*!< Specifies the memory base address for DMAy Channelx. */
+                                            
+    uint32_t DMA_Direction;                 /*!< Specifies if the peripheral is the source or destination.
+                                               This parameter can be a value of @ref DMA_data_transfer_direction */
+                                            
+    uint32_t DMA_BufferSize;                /*!< Specifies the buffer size, in data unit, of the specified Channel.
+                                               The data unit is equal to the configuration set in DMA_PeripheralDataWidth
+                                               or DMA_MemoryDataWidth members depending in the transfer direction. */
+                                            
+    uint32_t DMA_PeripheralInc;             /*!< Specifies whether the Peripheral address register is incremented or not.
+                                               This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+                                            
+    uint32_t DMA_MemoryInc;                 /*!< Specifies whether the memory address register is incremented or not.
+                                               This parameter can be a value of @ref DMA_memory_incremented_mode */
+                                            
+    uint32_t DMA_PeripheralDataWidth;       /*!< Specifies the Peripheral data width.
+                                               This parameter can be a value of @ref DMA_peripheral_data_size */
+                                            
+    uint32_t DMA_MemoryDataWidth;           /*!< Specifies the Memory data width.
+                                               This parameter can be a value of @ref DMA_memory_data_size */
+                                            
+    uint32_t DMA_Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
+                                               This parameter can be a value of @ref DMA_circular_normal_mode.
+                                               @note: The circular buffer mode cannot be used if the memory-to-memory
+                                                     data transfer is configured on the selected Channel */
+                                            
+    uint32_t DMA_Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
+                                               This parameter can be a value of @ref DMA_priority_level */
+                                            
+    uint32_t DMA_MTOM;                      /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                                               This parameter can be a value of @ref DMA_memory_to_memory */
+} DMA_InitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Constants
+  * @{
+  */
+#if defined (AT32F421xx)
+#define IS_DMA_ALL_PERIPH(PERIPH)           (((PERIPH) == DMA1_Channel1) || \
+                                             ((PERIPH) == DMA1_Channel2) || \
+                                             ((PERIPH) == DMA1_Channel3) || \
+                                             ((PERIPH) == DMA1_Channel4) || \
+                                             ((PERIPH) == DMA1_Channel5))
+#elif defined (AT32F413xx) || defined (AT32F415xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_DMA_ALL_PERIPH(PERIPH)           (((PERIPH) == DMA1_Channel1) || \
+                                             ((PERIPH) == DMA1_Channel2) || \
+                                             ((PERIPH) == DMA1_Channel3) || \
+                                             ((PERIPH) == DMA1_Channel4) || \
+                                             ((PERIPH) == DMA1_Channel5) || \
+                                             ((PERIPH) == DMA1_Channel6) || \
+                                             ((PERIPH) == DMA1_Channel7) || \
+                                             ((PERIPH) == DMA2_Channel1) || \
+                                             ((PERIPH) == DMA2_Channel2) || \
+                                             ((PERIPH) == DMA2_Channel3) || \
+                                             ((PERIPH) == DMA2_Channel4) || \
+                                             ((PERIPH) == DMA2_Channel5) || \
+                                             ((PERIPH) == DMA2_Channel6) || \
+                                             ((PERIPH) == DMA2_Channel7))
+#elif defined (AT32F403xx)
+#define IS_DMA_ALL_PERIPH(PERIPH)           (((PERIPH) == DMA1_Channel1) || \
+                                             ((PERIPH) == DMA1_Channel2) || \
+                                             ((PERIPH) == DMA1_Channel3) || \
+                                             ((PERIPH) == DMA1_Channel4) || \
+                                             ((PERIPH) == DMA1_Channel5) || \
+                                             ((PERIPH) == DMA1_Channel6) || \
+                                             ((PERIPH) == DMA1_Channel7) || \
+                                             ((PERIPH) == DMA2_Channel1) || \
+                                             ((PERIPH) == DMA2_Channel2) || \
+                                             ((PERIPH) == DMA2_Channel3) || \
+                                             ((PERIPH) == DMA2_Channel4) || \
+                                             ((PERIPH) == DMA2_Channel5))                                            
+#endif
+
+
+/** @defgroup DMA_flexible_channel
+  * @{
+  */
+#define Flex_Channel1          ((uint8_t)0x01)
+#define Flex_Channel2          ((uint8_t)0x02)
+#define Flex_Channel3          ((uint8_t)0x03)
+#define Flex_Channel4          ((uint8_t)0x04)
+#define Flex_Channel5          ((uint8_t)0x05)
+#define Flex_Channel6          ((uint8_t)0x06)
+#define Flex_Channel7          ((uint8_t)0x07)
+
+#define IS_DMA_ALL_CHANNELS(CHANNELS)     (((CHANNELS) == Flex_Channel1) || \
+                                           ((CHANNELS) == Flex_Channel2) || \
+                                           ((CHANNELS) == Flex_Channel3) || \
+                                           ((CHANNELS) == Flex_Channel4) || \
+                                           ((CHANNELS) == Flex_Channel5) || \
+                                           ((CHANNELS) == Flex_Channel6) || \
+                                           ((CHANNELS) == Flex_Channel7))
+
+/** @defgroup DMA_hardware_id
+  * @{
+  */
+#define DMA_FLEXIBLE_ADC1           ((uint8_t)0x01)
+#define DMA_FLEXIBLE_ADC3           ((uint8_t)0x03)
+#define DMA_FLEXIBLE_DAC1           ((uint8_t)0x05)
+#define DMA_FLEXIBLE_DAC2           ((uint8_t)0x06)
+#define DMA_FLEXIBLE_SPI1_RX        ((uint8_t)0x09)
+#define DMA_FLEXIBLE_SPI1_TX        ((uint8_t)0x0A)
+#define DMA_FLEXIBLE_SPI2_RX        ((uint8_t)0x0B)
+#define DMA_FLEXIBLE_SPI2_TX        ((uint8_t)0x0C)
+#define DMA_FLEXIBLE_SPI3_RX        ((uint8_t)0x0D)
+#define DMA_FLEXIBLE_SPI3_TX        ((uint8_t)0x0E)
+#define DMA_FLEXIBLE_SPI4_RX        ((uint8_t)0x0F)
+#define DMA_FLEXIBLE_SPI4_TX        ((uint8_t)0x10)
+#define DMA_FLEXIBLE_I2S2EXT_RX     ((uint8_t)0x11)
+#define DMA_FLEXIBLE_I2S2EXT_TX     ((uint8_t)0x12)
+#define DMA_FLEXIBLE_I2S3EXT_RX     ((uint8_t)0x13)
+#define DMA_FLEXIBLE_I2S3EXT_TX     ((uint8_t)0x14)
+#define DMA_FLEXIBLE_UART1_RX       ((uint8_t)0x19)
+#define DMA_FLEXIBLE_UART1_TX       ((uint8_t)0x1A)
+#define DMA_FLEXIBLE_UART2_RX       ((uint8_t)0x1B)
+#define DMA_FLEXIBLE_UART2_TX       ((uint8_t)0x1C)
+#define DMA_FLEXIBLE_UART3_RX       ((uint8_t)0x1D)
+#define DMA_FLEXIBLE_UART3_TX       ((uint8_t)0x1E)
+#define DMA_FLEXIBLE_UART4_RX       ((uint8_t)0x1F)
+#define DMA_FLEXIBLE_UART4_TX       ((uint8_t)0x20)
+#define DMA_FLEXIBLE_UART5_RX       ((uint8_t)0x21)
+#define DMA_FLEXIBLE_UART5_TX       ((uint8_t)0x22)
+#define DMA_FLEXIBLE_UART6_RX       ((uint8_t)0x23)
+#define DMA_FLEXIBLE_UART6_TX       ((uint8_t)0x24)
+#define DMA_FLEXIBLE_UART7_RX       ((uint8_t)0x25)
+#define DMA_FLEXIBLE_UART7_TX       ((uint8_t)0x26)
+#define DMA_FLEXIBLE_UART8_RX       ((uint8_t)0x27)
+#define DMA_FLEXIBLE_UART8_TX       ((uint8_t)0x28)
+#define DMA_FLEXIBLE_I2C1_RX        ((uint8_t)0x29)
+#define DMA_FLEXIBLE_I2C1_TX        ((uint8_t)0x2A)
+#define DMA_FLEXIBLE_I2C2_RX        ((uint8_t)0x2B)
+#define DMA_FLEXIBLE_I2C2_TX        ((uint8_t)0x2C)
+#define DMA_FLEXIBLE_I2C3_RX        ((uint8_t)0x2D)
+#define DMA_FLEXIBLE_I2C3_TX        ((uint8_t)0x2E)
+#define DMA_FLEXIBLE_SDIO1          ((uint8_t)0x31)
+#define DMA_FLEXIBLE_SDIO2          ((uint8_t)0x32)
+#define DMA_FLEXIBLE_TIM1_TRIG      ((uint8_t)0x35)
+#define DMA_FLEXIBLE_TIM1_COM       ((uint8_t)0x36)
+#define DMA_FLEXIBLE_TIM1_UP        ((uint8_t)0x37)
+#define DMA_FLEXIBLE_TIM1_CH1       ((uint8_t)0x38)
+#define DMA_FLEXIBLE_TIM1_CH2       ((uint8_t)0x39)
+#define DMA_FLEXIBLE_TIM1_CH3       ((uint8_t)0x3A)
+#define DMA_FLEXIBLE_TIM1_CH4       ((uint8_t)0x3B)
+#define DMA_FLEXIBLE_TIM2_TRIG      ((uint8_t)0x3D)
+#define DMA_FLEXIBLE_TIM2_UP        ((uint8_t)0x3F)
+#define DMA_FLEXIBLE_TIM2_CH1       ((uint8_t)0x40)
+#define DMA_FLEXIBLE_TIM2_CH2       ((uint8_t)0x41)
+#define DMA_FLEXIBLE_TIM2_CH3       ((uint8_t)0x42)
+#define DMA_FLEXIBLE_TIM2_CH4       ((uint8_t)0x43)
+#define DMA_FLEXIBLE_TIM3_TRIG      ((uint8_t)0x45)
+#define DMA_FLEXIBLE_TIM3_UP        ((uint8_t)0x47)
+#define DMA_FLEXIBLE_TIM3_CH1       ((uint8_t)0x48)
+#define DMA_FLEXIBLE_TIM3_CH2       ((uint8_t)0x49)
+#define DMA_FLEXIBLE_TIM3_CH3       ((uint8_t)0x4A)
+#define DMA_FLEXIBLE_TIM3_CH4       ((uint8_t)0x4B)
+#define DMA_FLEXIBLE_TIM4_TRIG      ((uint8_t)0x4D)
+#define DMA_FLEXIBLE_TIM4_UP        ((uint8_t)0x4F)
+#define DMA_FLEXIBLE_TIM4_CH1       ((uint8_t)0x50)
+#define DMA_FLEXIBLE_TIM4_CH2       ((uint8_t)0x51)
+#define DMA_FLEXIBLE_TIM4_CH3       ((uint8_t)0x52)
+#define DMA_FLEXIBLE_TIM4_CH4       ((uint8_t)0x53)
+#define DMA_FLEXIBLE_TIM5_TRIG      ((uint8_t)0x55)
+#define DMA_FLEXIBLE_TIM5_UP        ((uint8_t)0x57)
+#define DMA_FLEXIBLE_TIM5_CH1       ((uint8_t)0x58)
+#define DMA_FLEXIBLE_TIM5_CH2       ((uint8_t)0x59)
+#define DMA_FLEXIBLE_TIM5_CH3       ((uint8_t)0x5A)
+#define DMA_FLEXIBLE_TIM5_CH4       ((uint8_t)0x5B)
+#define DMA_FLEXIBLE_TIM6_UP        ((uint8_t)0x5F)
+#define DMA_FLEXIBLE_TIM7_UP        ((uint8_t)0x67)
+#define DMA_FLEXIBLE_TIM8_TRIG      ((uint8_t)0x6D)
+#define DMA_FLEXIBLE_TIM8_COM       ((uint8_t)0x6E)
+#define DMA_FLEXIBLE_TIM8_UP        ((uint8_t)0x6F)
+#define DMA_FLEXIBLE_TIM8_CH1       ((uint8_t)0x70)
+#define DMA_FLEXIBLE_TIM8_CH2       ((uint8_t)0x71)
+#define DMA_FLEXIBLE_TIM8_CH3       ((uint8_t)0x72)
+#define DMA_FLEXIBLE_TIM8_CH4       ((uint8_t)0x73)
+
+#define IS_DMA_ALL_HARDWARE_ID(HARDWARE_ID)     (((HARDWARE_ID) == DMA_FLEXIBLE_ADC1)     || ((HARDWARE_ID) == DMA_FLEXIBLE_ADC3)|| \
+												 ((HARDWARE_ID) == DMA_FLEXIBLE_DAC1)     || ((HARDWARE_ID) == DMA_FLEXIBLE_DAC2)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_SPI1_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_SPI1_TX)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_SPI2_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_SPI2_TX)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_SPI3_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_SPI3_TX)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_SPI4_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_SPI4_TX)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_I2S2EXT_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_I2S2EXT_TX)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_I2S3EXT_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_I2S3EXT_TX)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART1_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART1_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART2_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART2_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART3_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART3_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART4_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART4_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART5_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART5_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART6_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART6_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART7_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART7_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART8_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART8_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_I2C1_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_I2C1_TX)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_I2C2_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_I2C2_TX)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_I2C3_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_I2C3_TX)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_SDIO1)    || ((HARDWARE_ID) == DMA_FLEXIBLE_SDIO2)    || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_TRIG)|| ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_COM) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_UP)  || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_CH1) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_CH2) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_CH3) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_CH4) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM2_TRIG)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM2_UP)  || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM2_CH1) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM2_CH2) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM2_CH3) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM2_CH4) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM3_TRIG)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM3_UP)  || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM3_CH1) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM3_CH2) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM3_CH3) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM3_CH4) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM4_TRIG)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM4_UP)  || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM4_CH1) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM4_CH2) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM4_CH3) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM4_CH4) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM5_TRIG)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM5_UP)  || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM5_CH1) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM5_CH2) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM5_CH3) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM5_CH4) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM6_UP)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM7_UP)  || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_TRIG)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_COM) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_UP)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_CH1) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_CH2) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_CH3) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_CH4))
+
+#define DMA_FLEX_FUNCTION_EN                ((uint32_t)0X1000000)
+
+/** @defgroup DMA_data_transfer_direction
+  * @{
+  */
+
+#define DMA_DIR_PERIPHERALDST               ((uint32_t)0x00000010)
+#define DMA_DIR_PERIPHERALSRC               ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR)                     (((DIR) == DMA_DIR_PERIPHERALDST) || \
+                                             ((DIR) == DMA_DIR_PERIPHERALSRC))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_incremented_mode
+  * @{
+  */
+
+#define DMA_PERIPHERALINC_ENABLE            ((uint32_t)0x00000040)
+#define DMA_PERIPHERALINC_DISABLE           ((uint32_t)0x00000000)
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE)  (((STATE) == DMA_PERIPHERALINC_ENABLE) || \
+                                             ((STATE) == DMA_PERIPHERALINC_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_incremented_mode
+  * @{
+  */
+
+#define DMA_MEMORYINC_ENABLE                ((uint32_t)0x00000080)
+#define DMA_MEMORYINC_DISABLE               ((uint32_t)0x00000000)
+#define IS_DMA_MEMORY_INC_STATE(STATE)      (((STATE) == DMA_MEMORYINC_ENABLE) || \
+                                             ((STATE) == DMA_MEMORYINC_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_data_size
+  * @{
+  */
+
+#define DMA_PERIPHERALDATAWIDTH_BYTE        ((uint32_t)0x00000000)
+#define DMA_PERIPHERALDATAWIDTH_HALFWORD    ((uint32_t)0x00000100)
+#define DMA_PERIPHERALDATAWIDTH_WORD        ((uint32_t)0x00000200)
+#define IS_DMA_PERIPHERAL_DATA_WIDTH(WIDTH) (((WIDTH) == DMA_PERIPHERALDATAWIDTH_BYTE) || \
+                                             ((WIDTH) == DMA_PERIPHERALDATAWIDTH_HALFWORD) || \
+                                             ((WIDTH) == DMA_PERIPHERALDATAWIDTH_WORD))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_data_size
+  * @{
+  */
+
+#define DMA_MEMORYDATAWIDTH_BYTE            ((uint32_t)0x00000000)
+#define DMA_MEMORYDATAWIDTH_HALFWORD        ((uint32_t)0x00000400)
+#define DMA_MEMORYDATAWIDTH_WORD            ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_WIDTH(WIDTH)     (((WIDTH) == DMA_MEMORYDATAWIDTH_BYTE) || \
+                                             ((WIDTH) == DMA_MEMORYDATAWIDTH_HALFWORD) || \
+                                             ((WIDTH) == DMA_MEMORYDATAWIDTH_WORD))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_circular_normal_mode
+  * @{
+  */
+
+#define DMA_MODE_CIRCULAR                   ((uint32_t)0x00000020)
+#define DMA_MODE_NORMAL                     ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE)                   (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_priority_level
+  * @{
+  */
+
+#define DMA_PRIORITY_VERYHIGH               ((uint32_t)0x00003000)
+#define DMA_PRIORITY_HIGH                   ((uint32_t)0x00002000)
+#define DMA_PRIORITY_MEDIUM                 ((uint32_t)0x00001000)
+#define DMA_PRIORITY_LOW                    ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY)           (((PRIORITY) == DMA_PRIORITY_VERYHIGH) || \
+                                             ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+                                             ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                             ((PRIORITY) == DMA_PRIORITY_LOW))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_to_memory
+  * @{
+  */
+
+#define DMA_MEMTOMEM_ENABLE                 ((uint32_t)0x00004000)
+#define DMA_MEMTOMEM_DISABLE                ((uint32_t)0x00000000)
+#define IS_DMA_MTOM_STATE(STATE)            (((STATE) == DMA_MEMTOMEM_ENABLE) || ((STATE) == DMA_MEMTOMEM_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupts_definition
+  * @{
+  */
+
+#define DMA_INT_TC                          ((uint32_t)0x00000002)
+#define DMA_INT_HT                          ((uint32_t)0x00000004)
+#define DMA_INT_ERR                         ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_INT(INT)              ((((INT) & 0xFFFFFFF1) == 0x00) && ((INT) != 0x00))
+
+#define DMA1_INT_GL1                        ((uint32_t)0x00000001)
+#define DMA1_INT_TC1                        ((uint32_t)0x00000002)
+#define DMA1_INT_HT1                        ((uint32_t)0x00000004)
+#define DMA1_INT_ERR1                       ((uint32_t)0x00000008)
+#define DMA1_INT_GL2                        ((uint32_t)0x00000010)
+#define DMA1_INT_TC2                        ((uint32_t)0x00000020)
+#define DMA1_INT_HT2                        ((uint32_t)0x00000040)
+#define DMA1_INT_ERR2                       ((uint32_t)0x00000080)
+#define DMA1_INT_GL3                        ((uint32_t)0x00000100)
+#define DMA1_INT_TC3                        ((uint32_t)0x00000200)
+#define DMA1_INT_HT3                        ((uint32_t)0x00000400)
+#define DMA1_INT_ERR3                       ((uint32_t)0x00000800)
+#define DMA1_INT_GL4                        ((uint32_t)0x00001000)
+#define DMA1_INT_TC4                        ((uint32_t)0x00002000)
+#define DMA1_INT_HT4                        ((uint32_t)0x00004000)
+#define DMA1_INT_ERR4                       ((uint32_t)0x00008000)
+#define DMA1_INT_GL5                        ((uint32_t)0x00010000)
+#define DMA1_INT_TC5                        ((uint32_t)0x00020000)
+#define DMA1_INT_HT5                        ((uint32_t)0x00040000)
+#define DMA1_INT_ERR5                       ((uint32_t)0x00080000)
+#define DMA1_INT_GL6                        ((uint32_t)0x00100000)
+#define DMA1_INT_TC6                        ((uint32_t)0x00200000)
+#define DMA1_INT_HT6                        ((uint32_t)0x00400000)
+#define DMA1_INT_ERR6                       ((uint32_t)0x00800000)
+#define DMA1_INT_GL7                        ((uint32_t)0x01000000)
+#define DMA1_INT_TC7                        ((uint32_t)0x02000000)
+#define DMA1_INT_HT7                        ((uint32_t)0x04000000)
+#define DMA1_INT_ERR7                       ((uint32_t)0x08000000)
+
+#define DMA2_INT_GL1                        ((uint32_t)0x10000001)
+#define DMA2_INT_TC1                        ((uint32_t)0x10000002)
+#define DMA2_INT_HT1                        ((uint32_t)0x10000004)
+#define DMA2_INT_ERR1                       ((uint32_t)0x10000008)
+#define DMA2_INT_GL2                        ((uint32_t)0x10000010)
+#define DMA2_INT_TC2                        ((uint32_t)0x10000020)
+#define DMA2_INT_HT2                        ((uint32_t)0x10000040)
+#define DMA2_INT_ERR2                       ((uint32_t)0x10000080)
+#define DMA2_INT_GL3                        ((uint32_t)0x10000100)
+#define DMA2_INT_TC3                        ((uint32_t)0x10000200)
+#define DMA2_INT_HT3                        ((uint32_t)0x10000400)
+#define DMA2_INT_ERR3                       ((uint32_t)0x10000800)
+#define DMA2_INT_GL4                        ((uint32_t)0x10001000)
+#define DMA2_INT_TC4                        ((uint32_t)0x10002000)
+#define DMA2_INT_HT4                        ((uint32_t)0x10004000)
+#define DMA2_INT_ERR4                       ((uint32_t)0x10008000)
+#define DMA2_INT_GL5                        ((uint32_t)0x10010000)
+#define DMA2_INT_TC5                        ((uint32_t)0x10020000)
+#define DMA2_INT_HT5                        ((uint32_t)0x10040000)
+#define DMA2_INT_ERR5                       ((uint32_t)0x10080000)
+#define DMA2_INT_GL6                        ((uint32_t)0x10100000)
+#define DMA2_INT_TC6                        ((uint32_t)0x10200000)
+#define DMA2_INT_HT6                        ((uint32_t)0x10400000)
+#define DMA2_INT_ERR6                       ((uint32_t)0x10800000)
+#define DMA2_INT_GL7                        ((uint32_t)0x11000000)
+#define DMA2_INT_TC7                        ((uint32_t)0x12000000)
+#define DMA2_INT_HT7                        ((uint32_t)0x14000000)
+#define DMA2_INT_ERR7                       ((uint32_t)0x18000000)
+
+#define IS_DMA_CLEAR_INT(INT)               (((((INT) & 0xF0000000) == 0x00) || (((INT) & 0xE0000000) == 0x00)) && ((INT) != 0x00))
+
+#define IS_DMA_GET_INT(INT)                 (((INT) == DMA1_INT_GL1) || ((INT) == DMA1_INT_TC1) || \
+                                             ((INT) == DMA1_INT_HT1) || ((INT) == DMA1_INT_ERR1) || \
+                                             ((INT) == DMA1_INT_GL2) || ((INT) == DMA1_INT_TC2) || \
+                                             ((INT) == DMA1_INT_HT2) || ((INT) == DMA1_INT_ERR2) || \
+                                             ((INT) == DMA1_INT_GL3) || ((INT) == DMA1_INT_TC3) || \
+                                             ((INT) == DMA1_INT_HT3) || ((INT) == DMA1_INT_ERR3) || \
+                                             ((INT) == DMA1_INT_GL4) || ((INT) == DMA1_INT_TC4) || \
+                                             ((INT) == DMA1_INT_HT4) || ((INT) == DMA1_INT_ERR4) || \
+                                             ((INT) == DMA1_INT_GL5) || ((INT) == DMA1_INT_TC5) || \
+                                             ((INT) == DMA1_INT_HT5) || ((INT) == DMA1_INT_ERR5) || \
+                                             ((INT) == DMA1_INT_GL6) || ((INT) == DMA1_INT_TC6) || \
+                                             ((INT) == DMA1_INT_HT6) || ((INT) == DMA1_INT_ERR6) || \
+                                             ((INT) == DMA1_INT_GL7) || ((INT) == DMA1_INT_TC7) || \
+                                             ((INT) == DMA1_INT_HT7) || ((INT) == DMA1_INT_ERR7) || \
+                                             ((INT) == DMA2_INT_GL1) || ((INT) == DMA2_INT_TC1) || \
+                                             ((INT) == DMA2_INT_HT1) || ((INT) == DMA2_INT_ERR1) || \
+                                             ((INT) == DMA2_INT_GL2) || ((INT) == DMA2_INT_TC2) || \
+                                             ((INT) == DMA2_INT_HT2) || ((INT) == DMA2_INT_ERR2) || \
+                                             ((INT) == DMA2_INT_GL3) || ((INT) == DMA2_INT_TC3) || \
+                                             ((INT) == DMA2_INT_HT3) || ((INT) == DMA2_INT_ERR3) || \
+                                             ((INT) == DMA2_INT_GL4) || ((INT) == DMA2_INT_TC4) || \
+                                             ((INT) == DMA2_INT_HT4) || ((INT) == DMA2_INT_ERR4) || \
+                                             ((INT) == DMA2_INT_GL5) || ((INT) == DMA2_INT_TC5) || \
+                                             ((INT) == DMA2_INT_HT5) || ((INT) == DMA2_INT_ERR5)|| \
+                                             ((INT) == DMA2_INT_GL6) || ((INT) == DMA2_INT_TC6) || \
+                                             ((INT) == DMA2_INT_HT6) || ((INT) == DMA2_INT_ERR6) || \
+                                             ((INT) == DMA2_INT_GL7) || ((INT) == DMA2_INT_TC7) || \
+                                             ((INT) == DMA2_INT_HT7) || ((INT) == DMA2_INT_ERR7))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flags_definition
+  * @{
+  */
+#define DMA1_FLAG_GL1                       ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1                       ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1                       ((uint32_t)0x00000004)
+#define DMA1_FLAG_ERR1                      ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2                       ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2                       ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2                       ((uint32_t)0x00000040)
+#define DMA1_FLAG_ERR2                      ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3                       ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3                       ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3                       ((uint32_t)0x00000400)
+#define DMA1_FLAG_ERR3                      ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4                       ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4                       ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4                       ((uint32_t)0x00004000)
+#define DMA1_FLAG_ERR4                      ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5                       ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5                       ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5                       ((uint32_t)0x00040000)
+#define DMA1_FLAG_ERR5                      ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6                       ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6                       ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6                       ((uint32_t)0x00400000)
+#define DMA1_FLAG_ERR6                      ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7                       ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7                       ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7                       ((uint32_t)0x04000000)
+#define DMA1_FLAG_ERR7                      ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1                       ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1                       ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1                       ((uint32_t)0x10000004)
+#define DMA2_FLAG_ERR1                      ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2                       ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2                       ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2                       ((uint32_t)0x10000040)
+#define DMA2_FLAG_ERR2                      ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3                       ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3                       ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3                       ((uint32_t)0x10000400)
+#define DMA2_FLAG_ERR3                      ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4                       ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4                       ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4                       ((uint32_t)0x10004000)
+#define DMA2_FLAG_ERR4                      ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5                       ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5                       ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5                       ((uint32_t)0x10040000)
+#define DMA2_FLAG_ERR5                      ((uint32_t)0x10080000)
+#define DMA2_FLAG_GL6                       ((uint32_t)0x10100000)
+#define DMA2_FLAG_TC6                       ((uint32_t)0x10200000)
+#define DMA2_FLAG_HT6                       ((uint32_t)0x10400000)
+#define DMA2_FLAG_ERR6                      ((uint32_t)0x10800000)
+#define DMA2_FLAG_GL7                       ((uint32_t)0x11000000)
+#define DMA2_FLAG_TC7                       ((uint32_t)0x12000000)
+#define DMA2_FLAG_HT7                       ((uint32_t)0x14000000)
+#define DMA2_FLAG_ERR7                      ((uint32_t)0x18000000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG)             (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xE0000000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG)               (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+                                             ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_ERR1) || \
+                                             ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+                                             ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_ERR2) || \
+                                             ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+                                             ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_ERR3) || \
+                                             ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+                                             ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_ERR4) || \
+                                             ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+                                             ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_ERR5) || \
+                                             ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+                                             ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_ERR6) || \
+                                             ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+                                             ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_ERR7) || \
+                                             ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+                                             ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_ERR1) || \
+                                             ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+                                             ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_ERR2) || \
+                                             ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+                                             ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_ERR3) || \
+                                             ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+                                             ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_ERR4) || \
+                                             ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+                                             ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_ERR5)|| \
+                                             ((FLAG) == DMA2_FLAG_GL6) || ((FLAG) == DMA2_FLAG_TC6) || \
+                                             ((FLAG) == DMA2_FLAG_HT6) || ((FLAG) == DMA2_FLAG_ERR6) || \
+                                             ((FLAG) == DMA2_FLAG_GL7) || ((FLAG) == DMA2_FLAG_TC7) || \
+                                             ((FLAG) == DMA2_FLAG_HT7) || ((FLAG) == DMA2_FLAG_ERR7))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Buffer_Size
+  * @{
+  */
+
+#define IS_DMA_BUFFER_SIZE(SIZE)            (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions
+  * @{
+  */
+ITStatus DMA_GetITStatus(uint32_t DMAy_INT);
+void DMA_ClearITPendingBit(uint32_t DMAy_INT);
+void DMA_Flexible_Config(DMA_Type *DMAx,uint8_t Flex_Channelx,uint8_t Hardware_ID);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_Type* DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+void DMA_ChannelEnable(DMA_Channel_Type* DMAy_Channelx, FunctionalState NewState);
+void DMA_INTConfig(DMA_Channel_Type* DMAy_Channelx, uint32_t DMA_INT, FunctionalState NewState);
+void DMA_SetCurrDataCounter(DMA_Channel_Type* DMAy_Channelx, uint16_t DataNumber);
+void DMA_Reset(DMA_Channel_Type* DMAy_Channelx);
+void DMA_Init(DMA_Channel_Type* DMAy_Channelx, DMA_InitType* DMA_InitStruct);
+void DMA_DefaultInitParaConfig(DMA_InitType* DMA_InitStruct);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4XX_DMA_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_ertc.h

@@ -0,0 +1,868 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_ertc.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx ERTC header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_ERTC_H
+#define __AT32F4XX_ERTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ERTC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  ERTC Init structures definition  
+  */ 
+typedef struct
+{
+  uint32_t ERTC_HourFormat;   /*!< Specifies the ERTC Hour Format.
+                             This parameter can be a value of @ref RTC_Hour_Formats */
+  
+  uint32_t ERTC_AsynchPrediv; /*!< Specifies the ERTC Asynchronous Predivider value.
+                             This parameter must be set to a value lower than 0x7F */
+  
+  uint32_t ERTC_SynchPrediv;  /*!< Specifies the ERTC Synchronous Predivider value.
+                             This parameter must be set to a value lower than 0x7FFF */
+}ERTC_InitType;
+
+/** 
+  * @brief  ERTC Time structure definition  
+  */
+typedef struct
+{
+  uint8_t ERTC_Hours;    /*!< Specifies the ERTC Time Hour.
+                        This parameter must be set to a value in the 0-12 range
+                        if the ERTC_HourFormat_12 is selected or 0-23 range if
+                        the ERTC_HourFormat_24 is selected. */
+
+  uint8_t ERTC_Minutes;  /*!< Specifies the ERTC Time Minutes.
+                        This parameter must be set to a value in the 0-59 range. */
+  
+  uint8_t ERTC_Seconds;  /*!< Specifies the ERTC Time Seconds.
+                        This parameter must be set to a value in the 0-59 range. */
+
+  uint8_t ERTC_AMPM;      /*!< Specifies the ERTC AM/PM Time.
+                        This parameter can be a value of @ref RTC_AM_PM_Definitions */
+}ERTC_TimeType; 
+
+/** 
+  * @brief  ERTC Date structure definition  
+  */
+typedef struct
+{
+  uint8_t ERTC_WeekDay; /*!< Specifies the ERTC Date WeekDay.
+                        This parameter can be a value of @ref RTC_WeekDay_Definitions */
+  
+  uint8_t ERTC_Month;   /*!< Specifies the ERTC Date Month (in BCD format).
+                        This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+  uint8_t ERTC_Date;     /*!< Specifies the ERTC Date.
+                        This parameter must be set to a value in the 1-31 range. */
+  
+  uint8_t ERTC_Year;     /*!< Specifies the ERTC Date Year.
+                        This parameter must be set to a value in the 0-99 range. */
+}ERTC_DateType;
+
+/** 
+  * @brief  ERTC Alarm structure definition  
+  */
+typedef struct
+{
+  ERTC_TimeType ERTC_AlarmTime;     /*!< Specifies the ERTC Alarm Time members. */
+
+  uint32_t ERTC_AlarmMask;            /*!< Specifies the ERTC Alarm Masks.
+                                     This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+  uint32_t ERTC_AlarmDateWeekSel;  /*!< Specifies the ERTC Alarm is on Date or WeekDay.
+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+  
+  uint8_t ERTC_AlarmDateWeek;      /*!< Specifies the ERTC Alarm Date/WeekDay.
+                                     If the Alarm Date is selected, this parameter
+                                     must be set to a value in the 1-31 range.
+                                     If the Alarm WeekDay is selected, this 
+                                     parameter can be a value of @ref RTC_WeekDay_Definitions */
+}ERTC_AlarmType;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */ 
+
+
+/** @defgroup RTC_Hour_Formats 
+  * @{
+  */ 
+#define ERTC_HourFormat_24              ((uint32_t)0x00000000)
+#define ERTC_HourFormat_12              ((uint32_t)0x00000040)
+#define IS_ERTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == ERTC_HourFormat_12) || \
+                                         ((FORMAT) == ERTC_HourFormat_24))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Asynchronous_Predivider 
+  * @{
+  */ 
+#define IS_ERTC_ASYNCH_PRDIV(PRDIV)   ((PRDIV) <= 0x7F)
+ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Synchronous_Predivider 
+  * @{
+  */ 
+#define IS_ERTC_SYNCH_PRDIV(PRDIV)    ((PRDIV) <= 0x7FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Definitions 
+  * @{
+  */ 
+#define IS_ERTC_HOUR12(HOUR)            (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_ERTC_HOUR24(HOUR)            ((HOUR) <= 23)
+#define IS_ERTC_MINUTES(MINUTES)        ((MINUTES) <= 59)
+#define IS_ERTC_SECONDS(SECONDS)        ((SECONDS) <= 59)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_AM_PM_Definitions 
+  * @{
+  */ 
+#define ERTC_H12_AM                     ((uint8_t)0x00)
+#define ERTC_H12_PM                     ((uint8_t)0x40)
+#define IS_ERTC_H12(AMPM) (((AMPM) == ERTC_H12_AM) || ((AMPM) == ERTC_H12_PM))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Year_Date_Definitions 
+  * @{
+  */ 
+#define IS_ERTC_YEAR(YEAR)              ((YEAR) <= 99)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Month_Date_Definitions 
+  * @{
+  */ 
+
+/* Coded in BCD format */
+#define ERTC_Month_JAN                  ((uint8_t)0x01)
+#define ERTC_Month_FEB                  ((uint8_t)0x02)
+#define ERTC_Month_MAR                  ((uint8_t)0x03)
+#define ERTC_Month_APR                  ((uint8_t)0x04)
+#define ERTC_Month_MAY                  ((uint8_t)0x05)
+#define ERTC_Month_JUN                  ((uint8_t)0x06)
+#define ERTC_Month_JUL                  ((uint8_t)0x07)
+#define ERTC_Month_AUG                  ((uint8_t)0x08)
+#define ERTC_Month_SEP                  ((uint8_t)0x09)
+#define ERTC_Month_OCT                  ((uint8_t)0x10)
+#define ERTC_Month_NOV                  ((uint8_t)0x11)
+#define ERTC_Month_DEC                  ((uint8_t)0x12)
+#define IS_ERTC_MONTH(MONTH)            (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_ERTC_DATE(DATE)              (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_WeekDay_Definitions 
+  * @{
+  */ 
+  
+#define ERTC_Week_MON                   ((uint8_t)0x01)
+#define ERTC_Week_TUES                  ((uint8_t)0x02)
+#define ERTC_Week_WED                   ((uint8_t)0x03)
+#define ERTC_Week_THUR                  ((uint8_t)0x04)
+#define ERTC_Week_FRI                   ((uint8_t)0x05)
+#define ERTC_Week_SAT                   ((uint8_t)0x06)
+#define ERTC_Week_SUN                   ((uint8_t)0x07)
+#define IS_ERTC_WEEK(WEEK)      (((WEEK) == ERTC_Week_MON) || \
+                                 ((WEEK) == ERTC_Week_TUES) || \
+                                 ((WEEK) == ERTC_Week_WED) || \
+                                 ((WEEK) == ERTC_Week_THUR) || \
+                                 ((WEEK) == ERTC_Week_FRI) || \
+                                 ((WEEK) == ERTC_Week_SAT) || \
+                                 ((WEEK) == ERTC_Week_SUN))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Alarm_Definitions
+  * @{
+  */ 
+#define IS_ERTC_ALARM_DATE_WEEK_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_ERTC_ALARM_DATE_WEEK_WEEK(WEEK) (((WEEK) == ERTC_Week_MON) || \
+                                                    ((WEEK) == ERTC_Week_TUES) || \
+                                                    ((WEEK) == ERTC_Week_WED) || \
+                                                    ((WEEK) == ERTC_Week_THUR) || \
+                                                    ((WEEK) == ERTC_Week_FRI) || \
+                                                    ((WEEK) == ERTC_Week_SAT) || \
+                                                    ((WEEK) == ERTC_Week_SUN))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions 
+  * @{
+  */ 
+#define ERTC_AlarmDateWeekSel_Date       ((uint32_t)0x00000000)
+#define ERTC_AlarmDateWeekSel_Week       ((uint32_t)0x40000000)
+
+#define IS_ERTC_ALARM_DATE_WEEK_SEL(SEL) (((SEL) == ERTC_AlarmDateWeekSel_Date) || \
+                                            ((SEL) == ERTC_AlarmDateWeekSel_Week))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmMask_Definitions 
+  * @{
+  */ 
+#define ERTC_AlarmMask_None                ((uint32_t)0x00000000)
+#define ERTC_AlarmMask_DateWeek            ((uint32_t)0x80000000)
+#define ERTC_AlarmMask_Hours               ((uint32_t)0x00800000)
+#define ERTC_AlarmMask_Minutes             ((uint32_t)0x00008000)
+#define ERTC_AlarmMask_Seconds             ((uint32_t)0x00000080)
+#define ERTC_AlarmMask_All                 ((uint32_t)0x80808080)
+#define IS_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarms_Definitions 
+  * @{
+  */ 
+#define ERTC_AlA                       ((uint32_t)0x00000100)
+#define ERTC_AlB                       ((uint32_t)0x00000200)
+#define IS_ERTC_ALARM(ALARM)     (((ALARM) == ERTC_AlA) || ((ALARM) == ERTC_AlB))
+#define IS_ERTC_CMD_ALARM(ALARM) (((ALARM) & (ERTC_AlA | ERTC_AlB)) != (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+  /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+  * @{
+  */ 
+#define ERTC_AlarmSubSecondMask_All          ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. 
+                                                                       There is no comparison on sub seconds 
+                                                                       for Alarm */
+#define ERTC_AlarmSubSecondMask_SBS14_1      ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm 
+                                                                       comparison. Only SS[0] is compared. */
+#define ERTC_AlarmSubSecondMask_SBS14_2      ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm 
+                                                                       comparison. Only SS[1:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_3      ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm 
+                                                                       comparison. Only SS[2:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_4      ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm 
+                                                                       comparison. Only SS[3:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_5      ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm 
+                                                                       comparison. Only SS[4:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_6      ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm 
+                                                                       comparison. Only SS[5:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_7      ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm 
+                                                                       comparison. Only SS[6:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_8      ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm 
+                                                                       comparison. Only SS[7:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_9      ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm 
+                                                                       comparison. Only SS[8:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_10     ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm 
+                                                                       comparison. Only SS[9:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_11     ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm 
+                                                                       comparison. Only SS[10:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_12     ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm 
+                                                                       comparison.Only SS[11:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_13     ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm 
+                                                                       comparison. Only SS[12:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14        ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm 
+                                                                       comparison.Only SS[13:0] are compared */
+#define ERTC_AlarmSubSecondMask_None         ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match 
+                                                                       to activate alarm. */
+#define IS_ERTC_ALARM_SUB_SECOND_MASK(MASK)  (((MASK) == ERTC_AlarmSubSecondMask_All) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_1) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_2) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_3) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_4) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_5) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_6) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_7) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_8) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_9) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_10) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_11) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_12) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_13) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_None))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+  * @{
+  */ 
+
+#define IS_ERTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Wakeup_Timer_Definitions 
+  * @{
+  */ 
+#define ERTC_WakeUpClockSelect_RTCCLK_Div16        ((uint32_t)0x00000000)
+#define ERTC_WakeUpClockSelect_RTCCLK_Div8         ((uint32_t)0x00000001)
+#define ERTC_WakeUpClockSelect_RTCCLK_Div4         ((uint32_t)0x00000002)
+#define ERTC_WakeUpClockSelect_RTCCLK_Div2         ((uint32_t)0x00000003)
+#define ERTC_WakeUpClockSelect_CK_SPRE_16bits      ((uint32_t)0x00000004)
+#define ERTC_WakeUpClockSelect_CK_SPRE_17bits      ((uint32_t)0x00000006)
+#define IS_ERTC_WAKEUP_CLOCK_SELECT(CLOCK) (((CLOCK) == ERTC_WakeUpClockSelect_RTCCLK_Div16) || \
+                                    ((CLOCK) == ERTC_WakeUpClockSelect_RTCCLK_Div8) || \
+                                    ((CLOCK) == ERTC_WakeUpClockSelect_RTCCLK_Div4) || \
+                                    ((CLOCK) == ERTC_WakeUpClockSelect_RTCCLK_Div2) || \
+                                    ((CLOCK) == ERTC_WakeUpClockSelect_CK_SPRE_16bits) || \
+                                    ((CLOCK) == ERTC_WakeUpClockSelect_CK_SPRE_17bits))
+#define IS_ERTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Stamp_Edges_definitions 
+  * @{
+  */ 
+#define ERTC_TimeStampEdge_Rising          ((uint32_t)0x00000000)
+#define ERTC_TimeStampEdge_Falling         ((uint32_t)0x00000008)
+#define IS_ERTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == ERTC_TimeStampEdge_Rising) || \
+                                     ((EDGE) == ERTC_TimeStampEdge_Falling))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_selection_Definitions 
+  * @{
+  */ 
+#define ERTC_Output_Disable             ((uint32_t)0x00000000)
+#define ERTC_Output_AlarmA              ((uint32_t)0x00200000)
+#define ERTC_Output_AlarmB              ((uint32_t)0x00400000)
+#define ERTC_Output_WakeUp              ((uint32_t)0x00600000)
+ 
+#define IS_ERTC_OUTPUT(OUTPUT) (((OUTPUT) == ERTC_Output_Disable) || \
+                               ((OUTPUT) == ERTC_Output_AlarmA) || \
+                               ((OUTPUT) == ERTC_Output_AlarmB) || \
+                               ((OUTPUT) == ERTC_Output_WakeUp))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_Polarity_Definitions 
+  * @{
+  */ 
+#define ERTC_OutputPolarity_High           ((uint32_t)0x00000000)
+#define ERTC_OutputPolarity_Low            ((uint32_t)0x00100000)
+#define IS_ERTC_OUTPUT_OPOL(OPOL) (((OPOL) == ERTC_OutputPolarity_High) || \
+                                ((OPOL) == ERTC_OutputPolarity_Low))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Digital_Calibration_Definitions 
+  * @{
+  */ 
+#define ERTC_DataCalSign_Positive            ((uint32_t)0x00000000) 
+#define ERTC_DataCalSign_Negative            ((uint32_t)0x00000080)
+#define IS_ERTC_DATACAL_SIGN(SIGN) (((SIGN) == ERTC_DataCalSign_Positive) || \
+                                 ((SIGN) == ERTC_DataCalSign_Negative))
+#define IS_ERTC_DATACAL_VALUE(VALUE) ((VALUE) < 0x20)
+
+/**
+  * @}
+  */ 
+
+ /** @defgroup RTC_Calib_Output_selection_Definitions 
+  * @{
+  */ 
+#define ERTC_CalOutput_512Hz            ((uint32_t)0x00000000) 
+#define ERTC_CalOutput_1Hz              ((uint32_t)0x00080000)
+#define IS_ERTC_CAL_OUTPUT(OUTPUT)  (((OUTPUT) == ERTC_CalOutput_512Hz) || \
+                                      ((OUTPUT) == ERTC_CalOutput_1Hz))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_period_Definitions 
+  * @{
+  */ 
+#define ERTC_SmoothCalPeriod_32sec   ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
+                                                             period is 32s,  else 2exp20 RTCCLK seconds */
+#define ERTC_SmoothCalPeriod_16sec   ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibration 
+                                                             period is 16s, else 2exp19 RTCCLK seconds */
+#define ERTC_SmoothCalPeriod_8sec    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 8s, else 2exp18 RTCCLK seconds */
+#define IS_ERTC_SMOOTH_CAL_PERIOD(PERIOD) (((PERIOD) == ERTC_SmoothCalPeriod_32sec) || \
+                                             ((PERIOD) == ERTC_SmoothCalPeriod_16sec) || \
+                                             ((PERIOD) == ERTC_SmoothCalPeriod_8sec))
+                                          
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions 
+  * @{
+  */ 
+#define ERTC_SmoothCalAddPulses_Set    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added  
+                                                                during a X -second window = Y - CALM[8:0]. 
+                                                                 with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define ERTC_SmoothCalAddPulses_Reset  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
+                                                                 during a 32-second window =   CALM[8:0]. */
+#define IS_ERTC_SMOOTH_CAL_ADD(ADD) (((ADD) == ERTC_SmoothCalAddPulses_Set) || \
+                                         ((ADD) == ERTC_SmoothCalAddPulses_Reset))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions 
+  * @{
+  */ 
+#define  IS_ERTC_SMOOTH_CAL_VALUE(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_DayLightSaving_Definitions 
+  * @{
+  */ 
+#define ERTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
+#define ERTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
+#define IS_ERTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == ERTC_DayLightSaving_SUB1H) || \
+                                      ((SAVE) == ERTC_DayLightSaving_ADD1H))
+
+#define ERTC_StoreOperation_Reset        ((uint32_t)0x00000000)
+#define ERTC_StoreOperation_Set          ((uint32_t)0x00040000)
+#define IS_ERTC_STORE_OPERATION(OPERATION) (((OPERATION) == ERTC_StoreOperation_Reset) || \
+                                           ((OPERATION) == ERTC_StoreOperation_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Trigger_Definitions 
+  * @{
+  */ 
+#define ERTC_TamperTrig_RisingEdge            ((uint32_t)0x00000000)
+#define ERTC_TamperTrig_FallingEdge           ((uint32_t)0x00000001)
+#define ERTC_TamperTrig_LowLevel              ((uint32_t)0x00000000)
+#define ERTC_TamperTrig_HighLevel             ((uint32_t)0x00000001)
+#define IS_ERTC_TAMPER_TRIG(TRIG) (((TRIG) == ERTC_TamperTrig_RisingEdge) || \
+                                        ((TRIG) == ERTC_TamperTrig_FallingEdge) || \
+                                        ((TRIG) == ERTC_TamperTrig_LowLevel) || \
+                                        ((TRIG) == ERTC_TamperTrig_HighLevel)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Filter_Definitions 
+  * @{
+  */ 
+#define ERTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define ERTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2 
+                                                          consecutive samples at the active level */
+#define ERTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4 
+                                                          consecutive samples at the active level */
+#define ERTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8 
+                                                          consecutive samples at the active level. */
+#define IS_ERTC_TAMPER_FILTER(FILTER) (((FILTER) == ERTC_TamperFilter_Disable) || \
+                                      ((FILTER) == ERTC_TamperFilter_2Sample) || \
+                                      ((FILTER) == ERTC_TamperFilter_4Sample) || \
+                                      ((FILTER) == ERTC_TamperFilter_8Sample))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions 
+  * @{
+  */ 
+#define ERTC_TamperSamplingFreq_CLK_Div32768  ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 32768 */
+#define ERTC_TamperSamplingFreq_CLK_Div16384  ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
+                                                                            with a frequency =  RTCCLK / 16384 */
+#define ERTC_TamperSamplingFreq_CLK_Div8192   ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 8192  */
+#define ERTC_TamperSamplingFreq_CLK_Div4096   ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 4096  */
+#define ERTC_TamperSamplingFreq_CLK_Div2048   ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 2048  */
+#define ERTC_TamperSamplingFreq_CLK_Div1024   ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 1024  */
+#define ERTC_TamperSamplingFreq_CLK_Div512    ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 512   */
+#define ERTC_TamperSamplingFreq_CLK_Div256    ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 256   */
+#define IS_ERTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div32768) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div16384) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div8192) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div4096) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div2048) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div1024) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div512) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div256))
+
+/**
+  * @}
+  */
+
+  /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions 
+  * @{
+  */ 
+#define ERTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 1 RTCCLK cycle */
+#define ERTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 2 RTCCLK cycles */
+#define ERTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 4 RTCCLK cycles */
+#define ERTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 8 RTCCLK cycles */
+
+#define IS_ERTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == ERTC_TamperPrechargeDuration_1RTCCLK) || \
+                                                    ((DURATION) == ERTC_TamperPrechargeDuration_2RTCCLK) || \
+                                                    ((DURATION) == ERTC_TamperPrechargeDuration_4RTCCLK) || \
+                                                    ((DURATION) == ERTC_TamperPrechargeDuration_8RTCCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Pins_Definitions 
+  * @{
+  */ 
+#define ERTC_TAMP_1 ERTC_TPAF_TM1E
+#define ERTC_TAMP_2 ERTC_TPAF_TM2E
+#define IS_ERTC_TAMP(TAMP) (((TAMP) == ERTC_TAMP_1) || ((TAMP) == ERTC_TAMP_2))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Pin_Selection 
+  * @{
+  */ 
+#define ERTC_TAMPPIN_Default       ((uint32_t)0x00000000)
+#define ERTC_TAMPPIN_Pos1          ((uint32_t)0x00010000)
+#define IS_ERTC_TAMP_PIN(PIN)      (((PIN) == ERTC_TAMPPIN_Default) || \
+                                    ((PIN) == ERTC_TAMPPIN_Pos1))
+/* Legacy Defines */
+#define ERTC_TAMPPIN_PC13           ERTC_TAMPPIN_Default
+#define ERTC_TAMPPIN_PI8            ERTC_TAMPPIN_Pos1
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_TimeStamp_Pin_Selection 
+  * @{
+  */ 
+#define ERTC_TimeStampPin_PC13              ((uint32_t)0x00000000)
+#define ERTC_TimeStampPin_PI8               ((uint32_t)0x00020000)
+#define IS_ERTC_TIMESTAMP_PIN(PIN) (((PIN) == ERTC_TimeStampPin_PC13) || \
+                                   ((PIN) == ERTC_TimeStampPin_PI8))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_Type_ALARM_OUT 
+  * @{
+  */ 
+#define ERTC_OutputType_OpenDrain           ((uint32_t)0x00000000)
+#define ERTC_OutputType_PushPull            ((uint32_t)0x00040000)
+#define IS_ERTC_OUTPUT_TYPE(TYPE) (((TYPE) == ERTC_OutputType_OpenDrain) || \
+                                  ((TYPE) == ERTC_OutputType_PushPull))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions
+  * @{
+  */ 
+#define ERTC_ShiftAdd1S_Reset      ((uint32_t)0x00000000)
+#define ERTC_ShiftAdd1S_Set        ((uint32_t)0x80000000)
+#define IS_ERTC_SHIFT_ADD1S(SEL) (((SEL) == ERTC_ShiftAdd1S_Reset) || \
+                                 ((SEL) == ERTC_ShiftAdd1S_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value
+  * @{
+  */ 
+#define IS_ERTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Backup_Registers_Definitions 
+  * @{
+  */
+
+#define ERTC_BKP_DT0                       ((uint32_t)0x00000000)
+#define ERTC_BKP_DT1                       ((uint32_t)0x00000001)
+#define ERTC_BKP_DT2                       ((uint32_t)0x00000002)
+#define ERTC_BKP_DT3                       ((uint32_t)0x00000003)
+#define ERTC_BKP_DT4                       ((uint32_t)0x00000004)
+#define ERTC_BKP_DT5                       ((uint32_t)0x00000005)
+#define ERTC_BKP_DT6                       ((uint32_t)0x00000006)
+#define ERTC_BKP_DT7                       ((uint32_t)0x00000007)
+#define ERTC_BKP_DT8                       ((uint32_t)0x00000008)
+#define ERTC_BKP_DT9                       ((uint32_t)0x00000009)
+#define ERTC_BKP_DT10                      ((uint32_t)0x0000000A)
+#define ERTC_BKP_DT11                      ((uint32_t)0x0000000B)
+#define ERTC_BKP_DT12                      ((uint32_t)0x0000000C)
+#define ERTC_BKP_DT13                      ((uint32_t)0x0000000D)
+#define ERTC_BKP_DT14                      ((uint32_t)0x0000000E)
+#define ERTC_BKP_DT15                      ((uint32_t)0x0000000F)
+#define ERTC_BKP_DT16                      ((uint32_t)0x00000010)
+#define ERTC_BKP_DT17                      ((uint32_t)0x00000011)
+#define ERTC_BKP_DT18                      ((uint32_t)0x00000012)
+#define ERTC_BKP_DT19                      ((uint32_t)0x00000013)
+#define IS_ERTC_BKP(BKP)                  (((BKP) == ERTC_BKP_DT0) || \
+                                           ((BKP) == ERTC_BKP_DT1) || \
+                                           ((BKP) == ERTC_BKP_DT2) || \
+                                           ((BKP) == ERTC_BKP_DT3) || \
+                                           ((BKP) == ERTC_BKP_DT4) || \
+                                           ((BKP) == ERTC_BKP_DT5) || \
+                                           ((BKP) == ERTC_BKP_DT6) || \
+                                           ((BKP) == ERTC_BKP_DT7) || \
+                                           ((BKP) == ERTC_BKP_DT8) || \
+                                           ((BKP) == ERTC_BKP_DT9) || \
+                                           ((BKP) == ERTC_BKP_DT10) || \
+                                           ((BKP) == ERTC_BKP_DT11) || \
+                                           ((BKP) == ERTC_BKP_DT12) || \
+                                           ((BKP) == ERTC_BKP_DT13) || \
+                                           ((BKP) == ERTC_BKP_DT14) || \
+                                           ((BKP) == ERTC_BKP_DT15) || \
+                                           ((BKP) == ERTC_BKP_DT16) || \
+                                           ((BKP) == ERTC_BKP_DT17) || \
+                                           ((BKP) == ERTC_BKP_DT18) || \
+                                           ((BKP) == ERTC_BKP_DT19))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Input_parameter_format_definitions 
+  * @{
+  */ 
+#define ERTC_Format_BIN                    ((uint32_t)0x000000000)
+#define ERTC_Format_BCD                    ((uint32_t)0x000000001)
+#define IS_ERTC_FORMAT(FORMAT) (((FORMAT) == ERTC_Format_BIN) || ((FORMAT) == ERTC_Format_BCD))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Flags_Definitions 
+  * @{
+  */ 
+#define ERTC_FLAG_RECALPDF                 ((uint32_t)0x00010000)
+#define ERTC_FLAG_TP1F                     ((uint32_t)0x00002000)
+#define ERTC_FLAG_TP2F                     ((uint32_t)0x00004000) 
+#define ERTC_FLAG_TSOF                     ((uint32_t)0x00001000)
+#define ERTC_FLAG_TSF                      ((uint32_t)0x00000800)
+#define ERTC_FLAG_WATF                     ((uint32_t)0x00000400)
+#define ERTC_FLAG_ALBF                     ((uint32_t)0x00000200)
+#define ERTC_FLAG_ALAF                     ((uint32_t)0x00000100)
+#define ERTC_FLAG_INITF                    ((uint32_t)0x00000040)
+#define ERTC_FLAG_RSF                      ((uint32_t)0x00000020)
+#define ERTC_FLAG_INITS                    ((uint32_t)0x00000010)
+#define ERTC_FLAG_SFP                      ((uint32_t)0x00000008)
+#define ERTC_FLAG_WATWF                    ((uint32_t)0x00000004)
+#define ERTC_FLAG_ALBWF                    ((uint32_t)0x00000002)
+#define ERTC_FLAG_ALAWF                    ((uint32_t)0x00000001)
+#define IS_ERTC_GET_FLAG(FLAG) (((FLAG) == ERTC_FLAG_TSOF) || ((FLAG) == ERTC_FLAG_TSF) || \
+                                ((FLAG) == ERTC_FLAG_WATF) || ((FLAG) == ERTC_FLAG_ALBF) || \
+                                ((FLAG) == ERTC_FLAG_ALAF) || ((FLAG) == ERTC_FLAG_INITF) || \
+                                ((FLAG) == ERTC_FLAG_RSF) || ((FLAG) == ERTC_FLAG_WATWF) || \
+                                ((FLAG) == ERTC_FLAG_ALBWF) || ((FLAG) == ERTC_FLAG_ALAWF) || \
+                                ((FLAG) == ERTC_FLAG_TP1F) || ((FLAG) == ERTC_FLAG_RECALPDF) || \
+                                ((FLAG) == ERTC_FLAG_TP2F) ||((FLAG) == ERTC_FLAG_SFP))
+#define IS_ERTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Interrupts_Definitions 
+  * @{
+  */ 
+#define ERTC_INT_TS                         ((uint32_t)0x00008000)
+#define ERTC_INT_WAT                        ((uint32_t)0x00004000)
+#define ERTC_INT_ALB                        ((uint32_t)0x00002000)
+#define ERTC_INT_ALA                        ((uint32_t)0x00001000)
+#define ERTC_INT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define ERTC_INT_TAMP1                      ((uint32_t)0x00020000)
+#define ERTC_INT_TAMP2                      ((uint32_t)0x00040000)
+
+#define IS_ERTC_CONFIG_INT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
+#define IS_ERTC_GET_INT(IT) (((IT) == ERTC_INT_TS) || ((IT) == ERTC_INT_WAT) || \
+                           ((IT) == ERTC_INT_ALB) || ((IT) == ERTC_INT_ALA) || \
+                           ((IT) == ERTC_INT_TAMP1) || ((IT) == ERTC_INT_TAMP2))
+#define IS_ERTC_CLEAR_INT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF90FFF) == (uint32_t)RESET))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Legacy 
+  * @{
+  */ 
+#define ERTC_DigitalCalConfig  ERTC_CoarseCalConfig
+#define ERTC_DigitalCalCmd     ERTC_CoarseCalCmd
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the ERTC configuration to the default reset state *****/
+ErrorStatus ERTC_Reset(void);
+
+/* Interrupts and flags management functions **********************************/
+void ERTC_INTConfig(uint32_t ERTC_INT, FunctionalState NewState);
+FlagStatus ERTC_GetFlagStatus(uint32_t ERTC_FLAG);
+void ERTC_ClearFlag(uint32_t ERTC_FLAG);
+ITStatus ERTC_GetINTStatus(uint32_t ERTC_INT);
+void ERTC_ClearINTPendingBINT(uint32_t ERTC_INT);
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus ERTC_Init(ERTC_InitType* ERTC_InitStruct);
+void ERTC_StructInit(ERTC_InitType* ERTC_InitStruct);
+void ERTC_WriteProtectionCmd(FunctionalState NewState);
+ErrorStatus ERTC_EnterInitMode(void);
+void ERTC_ExitInitMode(void);
+ErrorStatus ERTC_WaitForSynchro(void);
+ErrorStatus ERTC_RefClockCmd(FunctionalState NewState);
+void ERTC_BypassShadowCmd(FunctionalState NewState);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus ERTC_SetTimeValue(uint32_t ERTC_Format, ERTC_TimeType* ERTC_TimeStruct);
+void ERTC_TimeStructInit(ERTC_TimeType* ERTC_TimeStruct);
+void ERTC_GetTimeValue(uint32_t ERTC_Format, ERTC_TimeType* ERTC_TimeStruct);
+uint32_t ERTC_GetSubSecondValue(void);
+ErrorStatus ERTC_SetDateValue(uint32_t ERTC_Format, ERTC_DateType* ERTC_DateStruct);
+void ERTC_DateStructInit(ERTC_DateType* ERTC_DateStruct);
+void ERTC_GetDateValue(uint32_t ERTC_Format, ERTC_DateType* ERTC_DateStruct);
+
+/* Daylight Saving configuration functions ************************************/
+void ERTC_DayLightSavingConfig(uint32_t ERTC_DayLightSaving, uint32_t ERTC_StoreOperation);
+uint32_t ERTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void ERTC_OutputConfig(uint32_t ERTC_Output, uint32_t ERTC_OutputPolarity);
+
+/* Digital Calibration configuration functions *********************************/
+ErrorStatus ERTC_CoarseCalConfig(uint32_t ERTC_CalSign, uint32_t Value);
+ErrorStatus ERTC_CoarseCalCmd(FunctionalState NewState);
+void ERTC_CalOutputCmd(FunctionalState NewState);
+void ERTC_CalOutputConfig(uint32_t ERTC_CalOutput);
+ErrorStatus ERTC_SmoothCalConfig(uint32_t ERTC_SmoothCalPeriod, 
+                                  uint32_t ERTC_SmoothCalPlusPulses,
+                                  uint32_t ERTC_SmouthCalMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void ERTC_TimeStampCmd(uint32_t ERTC_TimeStampEdge, FunctionalState NewState);
+void ERTC_GetTimeStamp(uint32_t ERTC_Format, ERTC_TimeType* ERTC_StampTimeStruct,
+                                      ERTC_DateType* ERTC_StampDateStruct);
+uint32_t ERTC_GetTimeStampSubSecond(void);
+
+/* Tampers configuration functions ********************************************/
+void ERTC_TamperTriggerConfig(uint32_t ERTC_Tamper, uint32_t ERTC_TamperTrigger);
+void ERTC_TamperCmd(uint32_t ERTC_Tamper, FunctionalState NewState);
+void ERTC_TamperFilterConfig(uint32_t ERTC_TamperFilter);
+void ERTC_TamperSamplingFreqConfig(uint32_t ERTC_TamperSamplingFreq);
+void ERTC_TamperPinsPrechargeDuration(uint32_t ERTC_TamperPrechargeDuration);
+void ERTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void ERTC_TamperPullUpCmd(FunctionalState NewState);
+
+/* Backup Data Registers configuration functions ******************************/
+void ERTC_WriteBackupRegister(uint32_t ERTC_BKP_DT, uint32_t Data);
+uint32_t ERTC_ReadBackupRegister(uint32_t ERTC_BKP_DT);
+
+/* ERTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
+   functions ******************************************************************/
+void ERTC_TamperPinSelection(uint32_t ERTC_TamperPin);
+void ERTC_TimeStampPinSelection(uint32_t ERTC_TimeStampPin);
+void ERTC_OutputTypeConfig(uint32_t ERTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus ERTC_SynchroShiftConfig(uint32_t ERTC_ShiftAdd1S, uint32_t ERTC_ShiftSubFS);
+
+/* Alarms (Alarm A and Alarm B) configuration functions  **********************/
+void ERTC_SetAlarmValue(uint32_t ERTC_Format, uint32_t ERTC_Alarm, ERTC_AlarmType* ERTC_AlarmStruct);
+void ERTC_AlarmStructInit(ERTC_AlarmType* ERTC_AlarmStruct);
+void ERTC_GetAlarmValue(uint32_t ERTC_Format, uint32_t ERTC_Alarm, ERTC_AlarmType* ERTC_AlarmStruct);
+ErrorStatus ERTC_AlarmCmd(uint32_t ERTC_Alarm, FunctionalState NewState);
+void ERTC_AlarmSubSecondConfig(uint32_t ERTC_Alarm, uint32_t ERTC_AlarmSubSecondValue, uint32_t ERTC_AlarmSubSecondMask);
+uint32_t ERTC_GetAlarmSubSecond(uint32_t ERTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/
+void ERTC_WakeUpClockConfig(uint32_t ERTC_WakeUpClock);
+void ERTC_SetWakeUpCounter(uint32_t ERTC_WakeUpCounter);
+uint32_t ERTC_GetWakeUpCounter(void);
+ErrorStatus ERTC_WakeUpCmd(FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4XX_RCC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 

StdPeriph_Driver/inc/at32f4xx_exti.h

@@ -0,0 +1,207 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_exti.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx EXTI header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_EXTI_H
+#define __AT32F4XX_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  EXTI mode enumeration
+  */
+
+typedef enum
+{
+    EXTI_Mode_Interrupt = 0x00,
+    EXTI_Mode_Event = 0x04
+} EXTIMode_Type;
+
+#define IS_EXTI_MODE(MODE)                  (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+  * @brief  EXTI Trigger enumeration
+  */
+
+typedef enum
+{
+    EXTI_Trigger_Rising = 0x08,
+    EXTI_Trigger_Falling = 0x0C,
+    EXTI_Trigger_Rising_Falling = 0x10
+} EXTITrigger_Type;
+
+#define IS_EXTI_TRIGGER(TRIGGER)            (((TRIGGER) == EXTI_Trigger_Rising) || \
+                                             ((TRIGGER) == EXTI_Trigger_Falling) || \
+                                             ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+  * @brief  EXTI Init Structure definition
+  */
+
+typedef struct
+{
+    uint32_t EXTI_Line;                     /*!< Specifies the EXTI lines to be enabled or disabled.
+                                                  This parameter can be any combination of @ref EXTI_Lines */
+                                            
+    EXTIMode_Type EXTI_Mode;                /*!< Specifies the mode for the EXTI lines.
+                                                  This parameter can be a value of @ref EXTIMode_Type */
+                                            
+    EXTITrigger_Type EXTI_Trigger;          /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                                  This parameter can be a value of @ref EXTIMode_Type */
+
+    FunctionalState EXTI_LineEnable;        /*!< Specifies the new state of the selected EXTI lines.
+                                                  This parameter can be set either to ENABLE or DISABLE */
+} EXTI_InitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Lines
+  * @{
+  */
+
+#define EXTI_Line0                          ((uint32_t)0x000001)  /*!< External interrupt line 0 */
+#define EXTI_Line1                          ((uint32_t)0x000002)  /*!< External interrupt line 1 */
+#define EXTI_Line2                          ((uint32_t)0x000004)  /*!< External interrupt line 2 */
+#define EXTI_Line3                          ((uint32_t)0x000008)  /*!< External interrupt line 3 */
+#define EXTI_Line4                          ((uint32_t)0x000010)  /*!< External interrupt line 4 */
+#define EXTI_Line5                          ((uint32_t)0x000020)  /*!< External interrupt line 5 */
+#define EXTI_Line6                          ((uint32_t)0x000040)  /*!< External interrupt line 6 */
+#define EXTI_Line7                          ((uint32_t)0x000080)  /*!< External interrupt line 7 */
+#define EXTI_Line8                          ((uint32_t)0x000100)  /*!< External interrupt line 8 */
+#define EXTI_Line9                          ((uint32_t)0x000200)  /*!< External interrupt line 9 */
+#define EXTI_Line10                         ((uint32_t)0x000400)  /*!< External interrupt line 10 */
+#define EXTI_Line11                         ((uint32_t)0x000800)  /*!< External interrupt line 11 */
+#define EXTI_Line12                         ((uint32_t)0x001000)  /*!< External interrupt line 12 */
+#define EXTI_Line13                         ((uint32_t)0x002000)  /*!< External interrupt line 13 */
+#define EXTI_Line14                         ((uint32_t)0x004000)  /*!< External interrupt line 14 */
+#define EXTI_Line15                         ((uint32_t)0x008000)  /*!< External interrupt line 15 */
+#define EXTI_Line16                         ((uint32_t)0x010000)  /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17                         ((uint32_t)0x020000)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18                         ((uint32_t)0x040000)  /*!< External interrupt line 18 Connected to the USB Device FS Wakeup from suspend event */
+#define EXTI_Line19                         ((uint32_t)0x080000)  /*!< External interrupt line 19 Connected to the COMP1*/
+#ifdef AT32F421xx
+	#define EXTI_Line20                         ((uint32_t)0x100000)  /*!< External interrupt line 20 */
+  #define EXTI_Line21                         ((uint32_t)0x200000)  /*!< External interrupt line 21 Connected to the COMP1*/
+#endif
+#ifdef AT32F415xx
+  #define EXTI_Line20                         ((uint32_t)0x100000)  /*!< External interrupt line 20 Connected to the COMP2*/
+  #define EXTI_Line21                         ((uint32_t)0x200000)  /*!< External interrupt line 20 Connected to the RTC Temper_Pin and Temper_Stamp*/
+  #define EXTI_Line22                         ((uint32_t)0x400000)  /*!< External interrupt line 20 Connected to the RTC Wakeup*/
+#endif
+
+#ifdef AT32F421xx
+  #define IS_EXTI_LINE(LINE)                  ((((LINE) & (uint32_t)0xFFC00000) == 0x00) && ((LINE) != (uint16_t)0x00))
+  #define IS_GET_EXTI_LINE(LINE)              (((LINE) == EXTI_Line0)  || ((LINE) == EXTI_Line1) || \
+                                             ((LINE) == EXTI_Line2)  || ((LINE) == EXTI_Line3) || \
+                                             ((LINE) == EXTI_Line4)  || ((LINE) == EXTI_Line5) || \
+                                             ((LINE) == EXTI_Line6)  || ((LINE) == EXTI_Line7) || \
+                                             ((LINE) == EXTI_Line8)  || ((LINE) == EXTI_Line9) || \
+                                             ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                                             ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                                             ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                                             ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                                             ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+                                             ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21))
+#elif defined AT32F415xx
+  #define IS_EXTI_LINE(LINE)                  ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
+  #define IS_GET_EXTI_LINE(LINE)              (((LINE) == EXTI_Line0)  || ((LINE) == EXTI_Line1) || \
+                                             ((LINE) == EXTI_Line2)  || ((LINE) == EXTI_Line3) || \
+                                             ((LINE) == EXTI_Line4)  || ((LINE) == EXTI_Line5) || \
+                                             ((LINE) == EXTI_Line6)  || ((LINE) == EXTI_Line7) || \
+                                             ((LINE) == EXTI_Line8)  || ((LINE) == EXTI_Line9) || \
+                                             ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                                             ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                                             ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                                             ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                                             ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+                                             ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
+                                             ((LINE) == EXTI_Line22))
+#else
+  #define IS_EXTI_LINE(LINE)                  ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
+  #define IS_GET_EXTI_LINE(LINE)              (((LINE) == EXTI_Line0)  || ((LINE) == EXTI_Line1) || \
+                                             ((LINE) == EXTI_Line2)  || ((LINE) == EXTI_Line3) || \
+                                             ((LINE) == EXTI_Line4)  || ((LINE) == EXTI_Line5) || \
+                                             ((LINE) == EXTI_Line6)  || ((LINE) == EXTI_Line7) || \
+                                             ((LINE) == EXTI_Line8)  || ((LINE) == EXTI_Line9) || \
+                                             ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                                             ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                                             ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                                             ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                                             ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions
+  * @{
+  */
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetIntStatus(uint32_t EXTI_Line);
+void EXTI_ClearIntPendingBit(uint32_t EXTI_Line);
+void EXTI_GenerateSWInt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_Reset(void);
+void EXTI_Init(EXTI_InitType* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitType* EXTI_InitStruct);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_EXTI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_flash.h

@@ -0,0 +1,428 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_flash.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx FMC header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_FLASH_H
+#define __AT32F4XX_FLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Status
+  */
+
+typedef enum
+{
+    FLASH_BSY = 1,
+    FLASH_PGRM_FLR,
+    FLASH_WRPRT_FLR,
+    FLASH_PRC_DONE,
+    FLASH_TIMEOUT
+} FLASH_Status;
+
+/**
+  * @brief  BANK3 SEL
+  */
+
+typedef enum
+{
+    E_BANK3_SEL_ESMT_SP=0,
+    E_BANK3_SEL_GENERAL_CFGQE,
+    E_BANK3_SEL_GENERAL,
+}T_BANK3_SEL;
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Option_Bytes_Write_Protection
+  * @{
+  */
+
+/* Values to be used with AT32F4xx Medium-density devices */
+#define FLASH_WRPRT_PAGE_0to3               ((uint32_t)0x00000001) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 0 to 3 */
+#define FLASH_WRPRT_PAGE_4to7               ((uint32_t)0x00000002) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 4 to 7 */
+#define FLASH_WRPRT_PAGE_8to11              ((uint32_t)0x00000004) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 8 to 11 */
+#define FLASH_WRPRT_PAGE_12to15             ((uint32_t)0x00000008) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 12 to 15 */
+#define FLASH_WRPRT_PAGE_16to19             ((uint32_t)0x00000010) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 16 to 19 */
+#define FLASH_WRPRT_PAGE_20to23             ((uint32_t)0x00000020) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 20 to 23 */
+#define FLASH_WRPRT_PAGE_24to27             ((uint32_t)0x00000040) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 24 to 27 */
+#define FLASH_WRPRT_PAGE_28to31             ((uint32_t)0x00000080) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 28 to 31 */
+#define FLASH_WRPRT_PAGE_32to35             ((uint32_t)0x00000100) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 32 to 35 */
+#define FLASH_WRPRT_PAGE_36to39             ((uint32_t)0x00000200) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 36 to 39 */
+#define FLASH_WRPRT_PAGE_40to43             ((uint32_t)0x00000400) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 40 to 43 */
+#define FLASH_WRPRT_PAGE_44to47             ((uint32_t)0x00000800) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 44 to 47 */
+#define FLASH_WRPRT_PAGE_48to51             ((uint32_t)0x00001000) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 48 to 51 */
+#define FLASH_WRPRT_PAGE_52to55             ((uint32_t)0x00002000) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 52 to 55 */
+#define FLASH_WRPRT_PAGE_56to59             ((uint32_t)0x00004000) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 56 to 59 */
+#define FLASH_WRPRT_PAGE_60to63             ((uint32_t)0x00008000) /*!< AT32F4xx Medium-density and AT32F421xx devices: Write protection of page 60 to 63 */
+#define FLASH_WRPRT_PAGE_64to67             ((uint32_t)0x00010000) /*!< AT32F4xx Medium-density devices: Write protection of page 64 to 67 */
+#define FLASH_WRPRT_PAGE_68to71             ((uint32_t)0x00020000) /*!< AT32F4xx Medium-density devices: Write protection of page 68 to 71 */
+#define FLASH_WRPRT_PAGE_72to75             ((uint32_t)0x00040000) /*!< AT32F4xx Medium-density devices: Write protection of page 72 to 75 */
+#define FLASH_WRPRT_PAGE_76to79             ((uint32_t)0x00080000) /*!< AT32F4xx Medium-density devices: Write protection of page 76 to 79 */
+#define FLASH_WRPRT_PAGE_80to83             ((uint32_t)0x00100000) /*!< AT32F4xx Medium-density devices: Write protection of page 80 to 83 */
+#define FLASH_WRPRT_PAGE_84to87             ((uint32_t)0x00200000) /*!< AT32F4xx Medium-density devices: Write protection of page 84 to 87 */
+#define FLASH_WRPRT_PAGE_88to91             ((uint32_t)0x00400000) /*!< AT32F4xx Medium-density devices: Write protection of page 88 to 91 */
+#define FLASH_WRPRT_PAGE_92to95             ((uint32_t)0x00800000) /*!< AT32F4xx Medium-density devices: Write protection of page 92 to 95 */
+#define FLASH_WRPRT_PAGE_96to99             ((uint32_t)0x01000000) /*!< AT32F4xx Medium-density devices: Write protection of page 96 to 99 */
+#define FLASH_WRPRT_PAGE_100to103           ((uint32_t)0x02000000) /*!< AT32F4xx Medium-density devices: Write protection of page 100 to 103 */
+#define FLASH_WRPRT_PAGE_104to107           ((uint32_t)0x04000000) /*!< AT32F4xx Medium-density devices: Write protection of page 104 to 107 */
+#define FLASH_WRPRT_PAGE_108to111           ((uint32_t)0x08000000) /*!< AT32F4xx Medium-density devices: Write protection of page 108 to 111 */
+#define FLASH_WRPRT_PAGE_112to115           ((uint32_t)0x10000000) /*!< AT32F4xx Medium-density devices: Write protection of page 112 to 115 */
+#define FLASH_WRPRT_PAGE_116to119           ((uint32_t)0x20000000) /*!< AT32F4xx Medium-density devices: Write protection of page 115 to 119 */
+#define FLASH_WRPRT_PAGE_120to123           ((uint32_t)0x40000000) /*!< AT32F4xx Medium-density devices: Write protection of page 120 to 123 */
+#define FLASH_WRPRT_PAGE_124to127           ((uint32_t)0x80000000) /*!< AT32F4xx Medium-density devices: Write protection of page 124 to 127 */
+
+/* Values to be used with AT32F4xx High-density, XL-density and AT32F415xx devices */
+#define FLASH_WRPRT_PAGE_0to1               ((uint32_t)0x00000001) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 0 to 1 */
+#define FLASH_WRPRT_PAGE_2to3               ((uint32_t)0x00000002) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 2 to 3 */
+#define FLASH_WRPRT_PAGE_4to5               ((uint32_t)0x00000004) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 4 to 5 */
+#define FLASH_WRPRT_PAGE_6to7               ((uint32_t)0x00000008) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 6 to 7 */
+#define FLASH_WRPRT_PAGE_8to9               ((uint32_t)0x00000010) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 8 to 9 */
+#define FLASH_WRPRT_PAGE_10to11             ((uint32_t)0x00000020) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 10 to 11 */
+#define FLASH_WRPRT_PAGE_12to13             ((uint32_t)0x00000040) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 12 to 13 */
+#define FLASH_WRPRT_PAGE_14to15             ((uint32_t)0x00000080) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 14 to 15 */
+#define FLASH_WRPRT_PAGE_16to17             ((uint32_t)0x00000100) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 16 to 17 */
+#define FLASH_WRPRT_PAGE_18to19             ((uint32_t)0x00000200) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 18 to 19 */
+#define FLASH_WRPRT_PAGE_20to21             ((uint32_t)0x00000400) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 20 to 21 */
+#define FLASH_WRPRT_PAGE_22to23             ((uint32_t)0x00000800) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 22 to 23 */
+#define FLASH_WRPRT_PAGE_24to25             ((uint32_t)0x00001000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 24 to 25 */
+#define FLASH_WRPRT_PAGE_26to27             ((uint32_t)0x00002000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 26 to 27 */
+#define FLASH_WRPRT_PAGE_28to29             ((uint32_t)0x00004000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 28 to 29 */
+#define FLASH_WRPRT_PAGE_30to31             ((uint32_t)0x00008000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 30 to 31 */
+#define FLASH_WRPRT_PAGE_32to33             ((uint32_t)0x00010000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 32 to 33 */
+#define FLASH_WRPRT_PAGE_34to35             ((uint32_t)0x00020000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 34 to 35 */
+#define FLASH_WRPRT_PAGE_36to37             ((uint32_t)0x00040000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 36 to 37 */
+#define FLASH_WRPRT_PAGE_38to39             ((uint32_t)0x00080000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 38 to 39 */
+#define FLASH_WRPRT_PAGE_40to41             ((uint32_t)0x00100000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 40 to 41 */
+#define FLASH_WRPRT_PAGE_42to43             ((uint32_t)0x00200000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 42 to 43 */
+#define FLASH_WRPRT_PAGE_44to45             ((uint32_t)0x00400000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 44 to 45 */
+#define FLASH_WRPRT_PAGE_46to47             ((uint32_t)0x00800000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 46 to 47 */
+#define FLASH_WRPRT_PAGE_48to49             ((uint32_t)0x01000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 48 to 49 */
+#define FLASH_WRPRT_PAGE_50to51             ((uint32_t)0x02000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 50 to 51 */
+#define FLASH_WRPRT_PAGE_52to53             ((uint32_t)0x04000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 52 to 53 */
+#define FLASH_WRPRT_PAGE_54to55             ((uint32_t)0x08000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 54 to 55 */
+#define FLASH_WRPRT_PAGE_56to57             ((uint32_t)0x10000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 56 to 57 */
+#define FLASH_WRPRT_PAGE_58to59             ((uint32_t)0x20000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 58 to 59 */
+#define FLASH_WRPRT_PAGE_60to61             ((uint32_t)0x40000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 60 to 61 */
+																		 
+#define FLASH_WRPRT_PAGE_62to63             ((uint32_t)0x80000000) /*!< AT32F415xx Medium-density devices: Write protection of page 62 to 63 */                                                                         
+#define FLASH_WRPRT_PAGE_62to127            ((uint32_t)0x80000000) /*!< AT32F4xx High-density, AT32F415xx Medium-density, High-density devices:
+                                                                         Write protection of page 62 to 127 */
+#define FLASH_WRPRT_PAGE_62to255            ((uint32_t)0x80000000) /*!< AT32F4xx High-density devices: Write protection of page 62 to 255 */                                                                         
+#define FLASH_WRPRT_PAGE_62to511            ((uint32_t)0x80000000) /*!< AT32F4xx XL-density devices: Write protection of page 62 to 511 */
+                                            
+#define FLASH_WRPRT_AllPAGES                ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+                                            
+#define IS_FLASH_WRPRT_PAGES(PAGES)         (((PAGES) != 0x00000000))
+                                            
+#define IS_FLASH_ADDR(ADDR)                 (((ADDR) >= 0x08000000) && ((ADDR) <= FLASH_BANK3_ADDR_MAX))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_IWatchdog
+  * @{
+  */
+
+#define UOB_SW_IWDG                         ((uint16_t)0x0001)  /*!< Software IWDG selected */
+#define UOB_HW_IWDG                         ((uint16_t)0x0000)  /*!< Hardware IWDG selected */
+#define IS_UOB_IWDG_CFG(CFG)                (((CFG) == UOB_SW_IWDG) || ((CFG) == UOB_HW_IWDG))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STOP
+  * @{
+  */
+
+#define UOB_NO_RST_STP                      ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define UOB_RST_STP                         ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+#define IS_UOB_STOP_CFG(CFG)                (((CFG) == UOB_NO_RST_STP) || ((CFG) == UOB_RST_STP))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STDBY
+  * @{
+  */
+
+#define UOB_NO_RST_STDBY                    ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define UOB_RST_STDBY                       ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+#define IS_UOB_STDBY_CFG(CFG)               (((CFG) == UOB_NO_RST_STDBY) || ((CFG) == UOB_RST_STDBY))
+
+#if defined(AT32F403xx) || defined(AT32F403Axx) || defined(AT32F407xx)
+/**
+  * @}
+  */
+/** @defgroup FLASH_Boot
+  * @{
+  */
+#define FLASH_BOOT_FROM_BANK1               ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
+                                                               and this parameter is selected the device will boot from Bank1(Default) */
+#define FLASH_BOOT_FROM_BANK2               ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
+                                                               and this parameter is selected the device will boot from Bank 2 or Bank 1,
+                                                               depending on the activation of the bank */
+#define IS_FLASH_BOOT_CFG(CFG)              (((CFG) == FLASH_BOOT_FROM_BANK1) || ((CFG) == FLASH_BOOT_FROM_BANK2))
+#endif
+/**
+  * @}
+  */
+/** @defgroup FLASH_Interrupts
+  * @{
+  */
+#define FLASH_INT_FLR                       ((uint32_t)0x00000400)  /*!< FPEC error interrupt source */
+#define FLASH_INT_PRCDN                     ((uint32_t)0x00001000)  /*!< End of FLASH Operation Interrupt source */
+#define FLASH_INT_BANK1_FLR                 FLASH_INT_FLR           /*!< FPEC BANK1 error interrupt source */
+#define FLASH_INT_BANK1_PRCDN               FLASH_INT_PRCDN         /*!< End of FLASH BANK1 Operation Interrupt source */
+#define FLASH_INT_BANK3                     ((uint32_t)0x40000000)
+#define FLASH_INT_BANK3_MASK                (~FLASH_INT_BANK3)
+#define FLASH_INT_BANK3_FLR                 ((uint32_t)0x40000400)  /*!< FPEC BANK1 error interrupt source */
+#define FLASH_INT_BANK3_PRCDN               ((uint32_t)0x40001000)  /*!< End of FLASH BANK1 Operation Interrupt source */
+
+
+
+#if defined(AT32F403xx) || defined(AT32F403Axx) || defined(AT32F407xx)
+#define FLASH_INT_BANK2                     ((uint32_t)0x80000000)
+#define FLASH_INT_BANK2_MASK                (~FLASH_INT_BANK2)
+#define FLASH_INT_BANK2_FLR                 ((uint32_t)0x80000400)  /*!< FPEC BANK2 error interrupt source */
+#define FLASH_INT_BANK2_PRCDN               ((uint32_t)0x80001000)  /*!< End of FLASH BANK2 Operation Interrupt source */
+#define IS_FLASH_INT(INT)                   ((((INT) & (uint32_t)0x3FFFEBFF) == 0x00000000) && (((INT) != 0x00000000)))
+#else
+#define IS_FLASH_INT(INT) ((((INT) & (uint32_t)0xBFFFEBFF) == 0x00000000) && (((INT) != 0x00000000)))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flags
+  * @{
+  */
+
+#define FLASH_FLAG_BSY                      ((uint32_t)0x00000001)  /*!< FLASH Busy flag */
+#define FLASH_FLAG_PRCDN                    ((uint32_t)0x00000020)  /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PRGMFLR                  ((uint32_t)0x00000004)  /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTFLR                 ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_UOBFLR                   ((uint32_t)0x00000001)  /*!< FLASH Option Byte error flag */
+
+#define FLASH_FLAG_BNK1_BSY                 FLASH_FLAG_BSY          /*!< FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BNK1_PRCDN               FLASH_FLAG_PRCDN        /*!< FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BNK1_PRGMFLR             FLASH_FLAG_PRGMFLR      /*!< FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BNK1_WRPRTFLR            FLASH_FLAG_WRPRTFLR     /*!< FLASH BANK1 Write protected error flag */
+
+#define FLASH_FLAG_BANK3                    ((uint32_t)0x40000000)
+#define FLASH_FLAG_BNK3_BSY                 ((uint32_t)0x40000001)  /*!< FLASH BANK3 Busy flag*/
+#define FLASH_FLAG_BNK3_PRCDN               ((uint32_t)0x40000020)  /*!< FLASH BANK3 End of Operation flag */
+#define FLASH_FLAG_BNK3_PRGMFLR             ((uint32_t)0x40000004)  /*!< FLASH BANK3 Program error flag */
+#define FLASH_FLAG_BNK3_WRPRTFLR            ((uint32_t)0x40000010)  /*!< FLASH BANK3 Write protected error flag */
+
+
+#if defined(AT32F403xx) || defined(AT32F403Axx) || defined(AT32F407xx)
+#define FLASH_FLAG_BANK2                    ((uint32_t)0x80000000)
+#define FLASH_FLAG_BNK2_BSY                 ((uint32_t)0x80000001)  /*!< FLASH BANK2 Busy flag */
+#define FLASH_FLAG_BNK2_PRCDN               ((uint32_t)0x80000020)  /*!< FLASH BANK2 End of Operation flag */
+#define FLASH_FLAG_BNK2_PRGMFLR             ((uint32_t)0x80000004)  /*!< FLASH BANK2 Program error flag */
+#define FLASH_FLAG_BNK2_WRPRTFLR            ((uint32_t)0x80000010)  /*!< FLASH BANK2 Write protected error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG)           ((((FLAG) & (uint32_t)0x3FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)             (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_PRGMFLR) || ((FLAG) == FLASH_FLAG_WRPRTFLR) || \
+                                             ((FLAG) == FLASH_FLAG_UOBFLR)|| \
+                                             ((FLAG) == FLASH_FLAG_BNK1_BSY) || ((FLAG) == FLASH_FLAG_BNK1_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_BNK1_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK1_WRPRTFLR) || \
+                                             ((FLAG) == FLASH_FLAG_BNK2_BSY) || ((FLAG) == FLASH_FLAG_BNK2_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_BNK2_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK2_WRPRTFLR) || \
+                                             ((FLAG) == FLASH_FLAG_BNK3_BSY) || ((FLAG) == FLASH_FLAG_BNK3_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_BNK3_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK3_WRPRTFLR))
+#else
+#define IS_FLASH_CLEAR_FLAG(FLAG)           ((((FLAG) & (uint32_t)0xBFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)             (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_PRGMFLR) || ((FLAG) == FLASH_FLAG_WRPRTFLR) || \
+                                             ((FLAG) == FLASH_FLAG_BNK1_BSY) || ((FLAG) == FLASH_FLAG_BNK1_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_BNK1_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK1_WRPRTFLR) || \
+                                             ((FLAG) == FLASH_FLAG_UOBFLR) || \
+                                             ((FLAG) == FLASH_FLAG_BNK3_BSY) || ((FLAG) == FLASH_FLAG_BNK3_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_BNK3_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK3_WRPRTFLR))
+#endif
+
+#define FLASH_BANK3_ADDR_MAX                  ((uint32_t)0x1FFEFFFF)
+#define IS_IN_FLASH_BANK3_RANGE(ADDR)         (((ADDR) >=EXT_FLASH_BASE) && ((ADDR) <= FLASH_BANK3_ADDR_MAX))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions
+  * @{
+  */
+
+/*------------ Functions used for all at32f4xx devices -----*/
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseUserOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_ProgramUserOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtect(uint32_t FLASH_Pages);
+FLASH_Status FLASH_ReadProtectConfig(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t UOB_IWDG, uint16_t UOB_STOP, uint16_t UOB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectStatus(void);
+FlagStatus FLASH_GetReadProtectStatus(void);
+void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForProcess(uint32_t Timeout);
+
+#if defined (AT32F415xx) || defined (AT32F421xx)
+/*------------ Functions used only for at32f415 devices -----*/
+FLASH_Status FLASH_SYS_AP(void);
+FlagStatus FLASH_GetOptionByteProtectStatus(void);
+FLASH_Status FLASH_RDPandOptionByteProtectEnable(void);
+void FLASH_OptionByteProtectDisable(void);
+#endif /* AT32F415xx || AT32F421xx */
+#if defined (AT32F421xx)
+FLASH_Status FLASH_SlibSysEnable(uint32_t Psw,uint8_t instr_start_page);
+#elif defined (AT32F415xx)
+FLASH_Status FLASH_SlibSysEnable(uint32_t Psw,uint8_t data_start_page);
+#endif
+
+/*------------ New function used for all at32f4xx devices -----*/
+void FLASH_UnlockBank1(void);
+void FLASH_LockBank1(void);
+FLASH_Status FLASH_EraseBank1AllPages(void);
+FLASH_Status FLASH_GetBank1Status(void);
+FLASH_Status FLASH_WaitForBank1Process(uint32_t Timeout);
+
+#if defined(AT32F403xx) || defined(AT32F403Axx) || defined(AT32F407xx)
+/*---- New Functions used only with at32f403_XL density devices -----*/
+void FLASH_UnlockBank2(void);
+void FLASH_LockBank2(void);
+FLASH_Status FLASH_EraseBank2AllPages(void);
+FLASH_Status FLASH_GetBank2Status(void);
+FLASH_Status FLASH_WaitForBank2Process(uint32_t Timeout);
+FLASH_Status FLASH_BootOptConfig(uint16_t FLASH_BOOT);
+#endif
+
+#if !defined (AT32F415xx) && !defined (AT32F421xx)
+/*---- New Functions for extrenal flash -----*/
+void FLASH_UnlockBank3(void);
+void FLASH_LockBank3(void);
+FLASH_Status FLASH_EraseBank3AllPages(void);
+FLASH_Status FLASH_GetBank3Status(void);
+FLASH_Status FLASH_WaitForBank3Process(uint32_t Timeout);
+void FLASH_Bank3EncEndAddrConfig(uint32_t EndAddress);
+#endif
+
+/*---- New Functions for SLIB -----*/
+#if defined (AT32F421xx)
+FLASH_Status FLASH_SlibMainEnable(uint32_t Psw, uint16_t StartPage, uint16_t InstrPage, uint16_t EndPage);
+#else
+FLASH_Status FLASH_SlibMainEnable(uint32_t Psw, uint16_t StartPage, uint16_t DataPage, uint16_t EndPage);
+#endif
+uint32_t FLASH_SlibDisable(uint32_t dwPsw);
+#if !defined (AT32F415xx) && !defined (AT32F421xx)
+uint32_t FLASH_GetSlibCurCnt(void);
+#endif
+uint8_t FLASH_GetSlibState(void);
+uint16_t FLASH_GetSlibStartPage(void);
+uint16_t FLASH_GetSlibDataStartPage(void);
+uint16_t FLASH_GetSlibInstrStartPage(void);
+uint16_t FLASH_GetSlibEndPage(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_FLASH_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_gpio.h

@@ -0,0 +1,696 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_gpio.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx GPIO header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_GPIO_H
+#define __AT32F4XX_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+#if defined (AT32F403xx) || defined (AT32F413xx) || \
+    defined (AT32F415xx) || defined (AT32F403Axx)|| \
+    defined (AT32F407xx)
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Types
+  * @{
+  */
+
+#if defined (AT32F413xx) || defined (AT32F415xx)
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOF))
+#elif defined AT32F403xx
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOE) || \
+                                    ((PERIPH) == GPIOF) || \
+                                    ((PERIPH) == GPIOG))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOE))
+#endif
+
+                                     
+/** 
+  * @brief  Output Maximum frequency selection  
+  */
+
+typedef enum
+{ 
+  GPIO_MaxSpeed_10MHz = 1,
+  GPIO_MaxSpeed_2MHz,
+  GPIO_MaxSpeed_50MHz = 2
+}GPIOMaxSpeed_Type;
+#define IS_GPIO_MAXSPEED(MAXSPEED) (((MAXSPEED) == GPIO_MaxSpeed_10MHz) ||\
+                                    ((MAXSPEED) == GPIO_MaxSpeed_2MHz)  || \
+                                    ((MAXSPEED) == GPIO_MaxSpeed_50MHz))
+
+/** 
+  * @brief  Configuration Mode enumeration  
+  */
+
+typedef enum
+{ GPIO_Mode_IN_ANALOG = 0x0,
+  GPIO_Mode_IN_FLOATING = 0x04,
+  GPIO_Mode_IN_PD = 0x28,
+  GPIO_Mode_IN_PU = 0x48,
+  GPIO_Mode_OUT_OD = 0x14,
+  GPIO_Mode_OUT_PP = 0x10,
+  GPIO_Mode_AF_OD = 0x1C,
+  GPIO_Mode_AF_PP = 0x18
+}GPIOMode_Type;
+
+#define IS_GPIO_MDE(MDE) (((MDE) == GPIO_Mode_IN_ANALOG) || ((MDE) == GPIO_Mode_IN_FLOATING) || \
+                          ((MDE) == GPIO_Mode_IN_PD)     || ((MDE) == GPIO_Mode_IN_PU)       || \
+                          ((MDE) == GPIO_Mode_OUT_OD)    || ((MDE) == GPIO_Mode_OUT_PP)      || \
+                          ((MDE) == GPIO_Mode_AF_OD)     || ((MDE) == GPIO_Mode_AF_PP))
+
+/** 
+  * @brief  GPIO Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t GPIO_Pins;               /*!< Specifies the GPIO pins to be configured.
+                                      This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOMaxSpeed_Type GPIO_MaxSpeed;  /*!< Specifies the speed for the selected pins.
+                                      This parameter can be a value of @ref GPIOMaxSpeed_Type */
+
+  GPIOMode_Type GPIO_Mode;          /*!< Specifies the operating mode for the selected pins.
+                                      This parameter can be a value of @ref GPIOMode_Type */
+}GPIO_InitType;
+
+
+/** 
+  * @brief  Bit_SET and Bit_RESET enumeration  
+  */
+
+typedef enum
+{ Bit_RESET = 0,
+  Bit_SET
+}BitState;
+
+#define IS_GPIO_BIT_STATE(STATE) (((STATE) == Bit_RESET) || ((STATE) == Bit_SET))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define 
+  * @{
+  */
+
+#define GPIO_Pins_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */
+#define GPIO_Pins_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */
+#define GPIO_Pins_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */
+#define GPIO_Pins_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */
+#define GPIO_Pins_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */
+#define GPIO_Pins_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */
+#define GPIO_Pins_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */
+#define GPIO_Pins_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */
+#define GPIO_Pins_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */
+#define GPIO_Pins_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */
+#define GPIO_Pins_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */
+#define GPIO_Pins_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */
+#define GPIO_Pins_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */
+#define GPIO_Pins_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */
+#define GPIO_Pins_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */
+#define GPIO_Pins_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */
+#define GPIO_Pins_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
+
+#define IS_GPIO_PINS(PINS) ((((PINS) & (uint16_t)0x00) == 0x00) && ((PINS) != (uint16_t)0x00))
+
+#define IS_GET_GPIO_PINS(PINS)      (((PINS) == GPIO_Pins_0)  || \
+                                     ((PINS) == GPIO_Pins_1)  || \
+                                     ((PINS) == GPIO_Pins_2)  || \
+                                     ((PINS) == GPIO_Pins_3)  || \
+                                     ((PINS) == GPIO_Pins_4)  || \
+                                     ((PINS) == GPIO_Pins_5)  || \
+                                     ((PINS) == GPIO_Pins_6)  || \
+                                     ((PINS) == GPIO_Pins_7)  || \
+                                     ((PINS) == GPIO_Pins_8)  || \
+                                     ((PINS) == GPIO_Pins_9)  || \
+                                     ((PINS) == GPIO_Pins_10) || \
+                                     ((PINS) == GPIO_Pins_11) || \
+                                     ((PINS) == GPIO_Pins_12) || \
+                                     ((PINS) == GPIO_Pins_13) || \
+                                     ((PINS) == GPIO_Pins_14) || \
+                                     ((PINS) == GPIO_Pins_15))
+
+/**
+  * @}
+  */
+
+#if defined (AT32F403xx) || defined (AT32F413xx)|| defined (AT32F415xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+/** @defgroup GPIO_Remap_define 
+  * @{
+  */
+  
+/** @defgroup AFIO_MAP_define
+  * @{
+  */
+#define GPIO_Remap01_SPI1           ((uint32_t)0x00000001)  /*!< SPI1 Alternate Function mapping 01 */
+#define GPIO_Remap_I2C1             ((uint32_t)0x00000002)  /*!< I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1           ((uint32_t)0x00000004)  /*!< USART1 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3    ((uint32_t)0x00000010)  /*!< USART3 Partial Alternate Function mapping */
+#define GPIO_PartialRemap_TMR1      ((uint32_t)0x00000040)  /*!< TMR1 Partial Alternate Function mapping */
+#define GPIO_PartialRemap1_TMR2     ((uint32_t)0x00000100)  /*!< TMR2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TMR2     ((uint32_t)0x00000200)  /*!< TMR2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TMR2         ((uint32_t)0x00000300)  /*!< TMR2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TMR3      ((uint32_t)0x00000800)  /*!< TMR3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TMR3         ((uint32_t)0x00000C00)  /*!< TMR3 Full Alternate Function mapping */
+#define GPIO_Remap1_CAN1            ((uint32_t)0x00004000)  /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01             ((uint32_t)0x00008000)  /*!< PD01 Alternate Function mapping */
+#define GPIO_Remap_TMR5CH4_LSI      ((uint32_t)0x00010000)  /*!< LSI connected to TMR5 Channel4 input capture for calibration */
+#define GPIO_Remap_ADC1_EXTRGINJ    ((uint32_t)0x00020000)  /*!< ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_EXTRGREG    ((uint32_t)0x00040000)  /*!< ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_SWJ_NoJNTRST     ((uint32_t)0x01000000)  /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable  ((uint32_t)0x02000000)  /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_AllDisable   ((uint32_t)0x04000000)  /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
+#ifdef AT32F403xx
+#define GPIO_Remap10_SPI1           ((uint32_t)0x80000000)  /*!< SPI1 Alternate Function mapping 10*/
+#define GPIO_Remap_USART2           ((uint32_t)0x00000008)  /*!< USART2 Alternate Function mapping */
+#define GPIO_FullRemap_USART3       ((uint32_t)0x00000030)  /*!< USART3 Full Alternate Function mapping */
+#define GPIO_FullRemap_TMR1         ((uint32_t)0x000000C0)  /*!< TMR1 Full Alternate Function mapping */
+#define GPIO_Remap_TMR4             ((uint32_t)0x00001000)  /*!< TMR4 Alternate Function mapping */
+#define GPIO_Remap2_CAN1            ((uint32_t)0x00006000)  /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap_ADC2_EXTRGINJ    ((uint32_t)0x00080000)  /*!< ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_EXTRGREG    ((uint32_t)0x00100000)  /*!< ADC2 External Trigger Regular Conversion remapping */
+#elif defined (AT32F413xx)
+#define GPIO_Remap_ADC2_EXTRGINJ    ((uint32_t)0x00080000)  /*!< ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_EXTRGREG    ((uint32_t)0x00100000)  /*!< ADC2 External Trigger Regular Conversion remapping */
+#elif defined (AT32F415xx)
+#define GPIO_PartialRemap2_USART3   ((uint32_t)0x00000020)  /*!< EXT_FLASH Alternate Function mapping*/
+#define GPIO_PartialRemap2_TMR1     ((uint32_t)0x00000080)  /*!< TMR1 Partial2 Alternate Function mapping */
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define GPIO_Remap_USART2           ((uint32_t)0x00000008)  /*!< USART2 Alternate Function mapping */
+#define GPIO_FullRemap_USART3       ((uint32_t)0x00000030)  /*!< USART3 Full Alternate Function mapping */
+#define GPIO_FullRemap_TMR1         ((uint32_t)0x000000C0)  /*!< TMR1 Full Alternate Function mapping */
+#define GPIO_Remap_TMR4             ((uint32_t)0x00001000)  /*!< TMR4 Alternate Function mapping */
+#define GPIO_Remap2_CAN1            ((uint32_t)0x00006000)  /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap_ADC2_EXTRGINJ    ((uint32_t)0x00080000)  /*!< ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_EXTRGREG    ((uint32_t)0x00100000)  /*!< ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ETH              ((uint32_t)0x00200000)  /*!< ETH Alternate Function mapping*/
+#define GPIO_Remap_CAN2             ((uint32_t)0x00400000)  /*!< CAN2 Alternate Function mapping*/
+#define GPIO_Remap_MII_RMII         ((uint32_t)0x00800000)  /*!< MII or RMII Alternate Function mapping */
+#define GPIO_Remap_SPI3             ((uint32_t)0x10000000)  /*!< SPI3 Alternate Function mapping*/
+#define GPIO_Remap_TMR2ITR1         ((uint32_t)0x20000000)  /*!< TMR2 internal trigger 1 Alternate remapping    */
+#define GPIO_Remap_PTP_PPS          ((uint32_t)0x40000000)  /*!< Ethernet PTP PPS Alternate Function remapping  */
+#endif
+/**
+  * @}
+  */
+  
+/** @defgroup AFIO_MAP2_define
+  * @{
+  */
+#ifdef AT32F403xx
+#define GPIO_Remap_TMR15            ((uint32_t)0x40000001)  /*!< TMR15 Alternate Function mapping  */
+#define GPIO_Remap_TMR9             ((uint32_t)0x40000020)  /*!< TMR9 Alternate Function mapping  */
+#define GPIO_Remap_TMR10            ((uint32_t)0x40000040)  /*!< TMR10 Alternate Function mapping  */
+#define GPIO_Remap_TMR11            ((uint32_t)0x40000080)  /*!< TMR11 Alternate Function mapping  */
+#define GPIO_Remap_TMR13            ((uint32_t)0x40000100)  /*!< TMR13 Alternate Function mapping  */
+#define GPIO_Remap_TMR14            ((uint32_t)0x40000200)  /*!< TMR14 Alternate Function mapping  */
+#define GPIO_Remap_XMC_NADV         ((uint32_t)0x40000400)  /*!< XMC_NADV Alternate Function mapping  */
+#define GPIO_Remap_SPI4             ((uint32_t)0x40020000)  /*!< SPI4 Alternate Function mapping*/
+#define GPIO_Remap_I2C3             ((uint32_t)0x40040000)  /*!< I2C3 Alternate Function mapping*/
+#define GPIO_Remap01_SDIO2          ((uint32_t)0x40080000)  /*!< SDIO2 Alternate Function mapping 01:CK/CMD Remaped None,D0~D3 Remaped to PA4~PA7*/
+#define GPIO_Remap10_SDIO2          ((uint32_t)0x40100000)  /*!< SDIO2 Alternate Function mapping 10:CK/CMD Remaped to PA2/PA3,D0~D3 Remaped None*/
+#define GPIO_Remap11_SDIO2          ((uint32_t)0x40180000)  /*!< SDIO2 Alternate Function mapping 11:CK/CMD Remaped to PA2/PA3,D0~D3 Remaped to PA4~PA7*/
+#define GPIO_Remap_EXT_FLASH        ((uint32_t)0x40200000)  /*!< EXT_FLASH Alternate Function mapping*/
+#elif defined (AT32F413xx)
+#define GPIO_Remap_EXT_FLASH        ((uint32_t)0x40200000)  /*!< EXT_FLASH Alternate Function mapping*/
+#elif defined (AT32F415xx)
+#define GPIO_Remap01_COMP           ((uint32_t)0x44000000)  /*!< COMP1/2 Alternate Function mapping 01: COMP1/2_OUT connect to PA6/7*/
+#define GPIO_Remap10_COMP           ((uint32_t)0x48000000)  /*!< COMP1/2 Alternate Function mapping 10: COMP1/2_OUT connect to PA11/12*/
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define GPIO_Remap_TMR9             ((uint32_t)0x40000020)  /*!< TMR9 Alternate Function mapping  */
+#define GPIO_Remap_XMC_NADV         ((uint32_t)0x40000400)  /*!< XMC_NADV Alternate Function mapping  */
+#define GPIO_Remap_SPI4             ((uint32_t)0x40020000)  /*!< SPI4 Alternate Function mapping*/
+#define GPIO_Remap_I2C3             ((uint32_t)0x40040000)  /*!< I2C3 Alternate Function mapping*/
+#define GPIO_Remap01_SDIO2          ((uint32_t)0x40080000)  /*!< SDIO2 Alternate Function mapping 01:CK/CMD Remaped None,D0~D3 Remaped to PA4~PA7*/
+#define GPIO_Remap10_SDIO2          ((uint32_t)0x40100000)  /*!< SDIO2 Alternate Function mapping 10:CK/CMD Remaped to PA2/PA3,D0~D3 Remaped None*/
+#define GPIO_Remap11_SDIO2          ((uint32_t)0x40180000)  /*!< SDIO2 Alternate Function mapping 11:CK/CMD Remaped to PA2/PA3,D0~D3 Remaped to PA4~PA7*/
+#define GPIO_Remap_EXT_FLASH        ((uint32_t)0x40200000)  /*!< EXT_FLASH Alternate Function mapping*/
+#endif
+/**
+  * @}
+  */
+  
+#ifdef AT32F403xx
+#define IS_GPIO_REMAP(REMAP)        (((REMAP) == GPIO_Remap01_SPI1)         || ((REMAP) == GPIO_Remap_I2C1)           || \
+                                     ((REMAP) == GPIO_Remap_USART1)         || ((REMAP) == GPIO_Remap_USART2)         || \
+                                     ((REMAP) == GPIO_PartialRemap_USART3)  || ((REMAP) == GPIO_FullRemap_USART3)     || \
+                                     ((REMAP) == GPIO_PartialRemap_TMR1)    || ((REMAP) == GPIO_FullRemap_TMR1)       || \
+                                     ((REMAP) == GPIO_PartialRemap1_TMR2)   || ((REMAP) == GPIO_PartialRemap2_TMR2)   || \
+                                     ((REMAP) == GPIO_FullRemap_TMR2)       || ((REMAP) == GPIO_PartialRemap_TMR3)    || \
+                                     ((REMAP) == GPIO_FullRemap_TMR3)       || ((REMAP) == GPIO_Remap_TMR4)           || \
+                                     ((REMAP) == GPIO_Remap1_CAN1)          || ((REMAP) == GPIO_Remap2_CAN1)          || \
+                                     ((REMAP) == GPIO_Remap_PD01)           || ((REMAP) == GPIO_Remap_TMR5CH4_LSI)    || \
+                                     ((REMAP) == GPIO_Remap_ADC1_EXTRGINJ)  || ((REMAP) == GPIO_Remap_ADC1_EXTRGREG)  || \
+                                     ((REMAP) == GPIO_Remap_ADC2_EXTRGINJ)  || ((REMAP) == GPIO_Remap_ADC2_EXTRGREG)  || \
+                                     ((REMAP) == GPIO_Remap_SWJ_NoJNTRST)   || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \
+                                     ((REMAP) == GPIO_Remap_SWJ_AllDisable) || ((REMAP) == GPIO_Remap10_SPI1)         || \
+                                     ((REMAP) == GPIO_Remap_TMR15)          || ((REMAP) == GPIO_Remap_TMR9)           || \
+                                     ((REMAP) == GPIO_Remap_TMR10)          || ((REMAP) == GPIO_Remap_TMR11)          || \
+                                     ((REMAP) == GPIO_Remap_TMR13)          || ((REMAP) == GPIO_Remap_TMR14)          || \
+                                     ((REMAP) == GPIO_Remap_XMC_NADV)       || ((REMAP) == GPIO_Remap_SPI4)           || \
+                                     ((REMAP) == GPIO_Remap_I2C3)           || ((REMAP) == GPIO_Remap01_SDIO2)        || \
+                                     ((REMAP) == GPIO_Remap10_SDIO2)        || ((REMAP) == GPIO_Remap11_SDIO2)        || \
+                                     ((REMAP) == GPIO_Remap_EXT_FLASH))
+#elif defined (AT32F413xx)
+#define IS_GPIO_REMAP(REMAP)        (((REMAP) == GPIO_Remap01_SPI1)         || ((REMAP) == GPIO_Remap_I2C1)           || \
+                                     ((REMAP) == GPIO_Remap_USART1)         || ((REMAP) == GPIO_PartialRemap_USART3)  || \
+                                     ((REMAP) == GPIO_PartialRemap_TMR1)    || ((REMAP) == GPIO_PartialRemap1_TMR2)   || \
+                                     ((REMAP) == GPIO_PartialRemap2_TMR2)   || ((REMAP) == GPIO_FullRemap_TMR2)       || \
+                                     ((REMAP) == GPIO_PartialRemap_TMR3)    || ((REMAP) == GPIO_FullRemap_TMR3)       || \
+                                     ((REMAP) == GPIO_Remap1_CAN1)          || ((REMAP) == GPIO_Remap_EXT_FLASH)      || \
+                                     ((REMAP) == GPIO_Remap_PD01)           || ((REMAP) == GPIO_Remap_TMR5CH4_LSI)    || \
+                                     ((REMAP) == GPIO_Remap_ADC1_EXTRGINJ)  || ((REMAP) == GPIO_Remap_ADC1_EXTRGREG)  || \
+                                     ((REMAP) == GPIO_Remap_ADC2_EXTRGINJ)  || ((REMAP) == GPIO_Remap_ADC2_EXTRGREG)  || \
+                                     ((REMAP) == GPIO_Remap_SWJ_NoJNTRST)   || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \
+                                     ((REMAP) == GPIO_Remap_SWJ_AllDisable))
+#elif defined (AT32F415xx)
+#define IS_GPIO_REMAP(REMAP)        (((REMAP) == GPIO_Remap01_SPI1)         || ((REMAP) == GPIO_Remap_I2C1)           || \
+                                     ((REMAP) == GPIO_Remap_USART1)         || ((REMAP) == GPIO_PartialRemap_USART3)  || \
+                                     ((REMAP) == GPIO_PartialRemap_TMR1)    || ((REMAP) == GPIO_PartialRemap1_TMR2)   || \
+                                     ((REMAP) == GPIO_PartialRemap2_TMR2)   || ((REMAP) == GPIO_FullRemap_TMR2)       || \
+                                     ((REMAP) == GPIO_PartialRemap_TMR3)    || ((REMAP) == GPIO_FullRemap_TMR3)       || \
+                                     ((REMAP) == GPIO_Remap1_CAN1)          || ((REMAP) == GPIO_Remap_PD01)           || \
+                                     ((REMAP) == GPIO_Remap_TMR5CH4_LSI)    || ((REMAP) == GPIO_Remap_ADC1_EXTRGINJ)  || \
+                                     ((REMAP) == GPIO_Remap_ADC1_EXTRGREG)  || ((REMAP) == GPIO_Remap_SWJ_NoJNTRST)   || \
+                                     ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| ((REMAP) == GPIO_Remap_SWJ_AllDisable) || \
+                                     ((REMAP) == GPIO_Remap01_COMP)         || ((REMAP) == GPIO_Remap10_COMP)         || \
+                                     ((REMAP) == GPIO_PartialRemap2_USART3) || ((REMAP) == GPIO_PartialRemap2_TMR1))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_GPIO_REMAP(REMAP)        (((REMAP) == GPIO_Remap01_SPI1)         || ((REMAP) == GPIO_Remap_I2C1)           || \
+                                     ((REMAP) == GPIO_Remap_USART1)         || ((REMAP) == GPIO_Remap_USART2)         || \
+                                     ((REMAP) == GPIO_PartialRemap_USART3)  || ((REMAP) == GPIO_FullRemap_USART3)     || \
+                                     ((REMAP) == GPIO_PartialRemap_TMR1)    || ((REMAP) == GPIO_FullRemap_TMR1)       || \
+                                     ((REMAP) == GPIO_PartialRemap1_TMR2)   || ((REMAP) == GPIO_PartialRemap2_TMR2)   || \
+                                     ((REMAP) == GPIO_FullRemap_TMR2)       || ((REMAP) == GPIO_PartialRemap_TMR3)    || \
+                                     ((REMAP) == GPIO_FullRemap_TMR3)       || ((REMAP) == GPIO_Remap_TMR4)           || \
+                                     ((REMAP) == GPIO_Remap1_CAN1)          || ((REMAP) == GPIO_Remap2_CAN1)          || \
+                                     ((REMAP) == GPIO_Remap_PD01)           || ((REMAP) == GPIO_Remap_TMR5CH4_LSI)    || \
+                                     ((REMAP) == GPIO_Remap_ADC1_EXTRGINJ)  || ((REMAP) == GPIO_Remap_ADC1_EXTRGREG)  || \
+                                     ((REMAP) == GPIO_Remap_ADC2_EXTRGINJ)  || ((REMAP) == GPIO_Remap_ADC2_EXTRGREG)  || \
+                                     ((REMAP) == GPIO_Remap_SWJ_NoJNTRST)   || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \
+                                     ((REMAP) == GPIO_Remap_SWJ_AllDisable) || ((REMAP) == GPIO_Remap_EXT_FLASH)      || \
+                                     ((REMAP) == GPIO_Remap_PTP_PPS)        || ((REMAP) == GPIO_Remap_TMR2ITR1)       || \
+                                     ((REMAP) == GPIO_Remap_SPI3)           || ((REMAP) == GPIO_Remap_MII_RMII)       || \
+                                     ((REMAP) == GPIO_Remap_CAN2)           || ((REMAP) == GPIO_Remap_ETH)            || \
+                                     ((REMAP) == GPIO_Remap_TMR9)           || ((REMAP) == GPIO_Remap_XMC_NADV)       || \
+                                     ((REMAP) == GPIO_Remap_SPI4)           || ((REMAP) == GPIO_Remap_I2C3)           || \
+                                     ((REMAP) == GPIO_Remap01_SDIO2)        || ((REMAP) == GPIO_Remap10_SDIO2)        || \
+                                     ((REMAP) == GPIO_Remap11_SDIO2))
+                                     
+#endif
+                              
+/**
+  * @}
+  */ 
+#endif
+
+#if !defined(AT32F403xx)
+
+#define AFIO_MAP3     0x00
+#define AFIO_MAP4     0x01
+#define AFIO_MAP5     0x02
+#define AFIO_MAP6     0x03
+#define AFIO_MAP7     0x04
+#if defined (AT32F415xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+#define AFIO_MAP8     0x05
+#endif
+
+#define BITS0         0x00
+#define BITS1         0x01
+#define BITS2         0x02
+#define BITS3         0x03
+#define BITS4         0x04
+#define BITS5         0x05
+#define BITS6         0x06
+#define BITS7         0x07
+
+#define OFFSET_MASK0  0xFFFFFFF0
+#define OFFSET_MASK1  0xFFFFFF0F
+#define OFFSET_MASK2  0xFFFFF0FF
+#define OFFSET_MASK3  0xFFFF0FFF
+#define OFFSET_MASK4  0xFFF0FFFF
+#define OFFSET_MASK5  0xFF0FFFFF
+#define OFFSET_MASK6  0xF0FFFFFF
+#define OFFSET_MASK7  0x0FFFFFFF
+
+/** @defgroup AFIO_MAP3_4_5_6_7_8_define 
+  * @{ 
+  */
+#define AFIO_MAP3_TMR9_0010         ((uint32_t)0x80000002)  /*!< TMR9 Alternate Function mapping  */
+#define AFIO_MAP3_TMR10_0010        ((uint32_t)0x80000012)  /*!< TMR10 Alternate Function mapping  */
+#define AFIO_MAP3_TMR11_0010        ((uint32_t)0x80000022)  /*!< TMR11 Alternate Function mapping  */
+
+#define AFIO_MAP4_TMR1_0001         ((uint32_t)0x80000081)  /*!< TMR1 Alternate Function mapping */
+#define AFIO_MAP4_TMR3_0010         ((uint32_t)0x800000A2)  /*!< TMR3 Alternate Function mapping 0010*/
+#define AFIO_MAP4_TMR3_0011         ((uint32_t)0x800000A3)  /*!< TMR3 Alternate Function mapping 0011*/
+#define AFIO_MAP4_TMR5_1000         ((uint32_t)0x800000C8)  /*!< TMR5 channel4 internal remap */
+
+#define AFIO_MAP5_USART5_0001       ((uint32_t)0x80000101)  /*!< USART5 Alternate Function mapping 0001*/
+#define AFIO_MAP5_I2C1_0001         ((uint32_t)0x80000111)  /*!< I2C1 Alternate Function mapping 0001*/
+#define AFIO_MAP5_I2C1_0010         ((uint32_t)0x80000112)  /*!< I2C1 Alternate Function mapping 0010*/
+#define AFIO_MAP5_I2C1_0011         ((uint32_t)0x80000113)  /*!< I2C1 Alternate Function mapping 0011*/
+#define AFIO_MAP5_I2C2_0001         ((uint32_t)0x80000121)  /*!< I2C2 Alternate Function mapping 0001*/
+#define AFIO_MAP5_I2C2_0010         ((uint32_t)0x80000122)  /*!< I2C2 Alternate Function mapping 0010*/
+#define AFIO_MAP5_I2C2_0011         ((uint32_t)0x80000123)  /*!< I2C2 Alternate Function mapping 0011*/
+#define AFIO_MAP5_I2C3_0001         ((uint32_t)0x80000131)  /*!< I2C3 Alternate Function mapping 0001*/
+#define AFIO_MAP5_SPI1_0001         ((uint32_t)0x80000141)  /*!< SPI1 Alternate Function mapping 0001*/
+#define AFIO_MAP5_SPI1_0010         ((uint32_t)0x80000142)  /*!< SPI1 Alternate Function mapping 0010*/
+#define AFIO_MAP5_SPI1_0011         ((uint32_t)0x80000143)  /*!< SPI1 Alternate Function mapping 0011*/
+#define AFIO_MAP5_SPI2_0001         ((uint32_t)0x80000151)  /*!< SPI2 Alternate Function mapping 0001*/
+#define AFIO_MAP5_SPI2_0010         ((uint32_t)0x80000152)  /*!< SPI2 Alternate Function mapping 0010*/
+#define AFIO_MAP5_SPI3_0001         ((uint32_t)0x80000161)  /*!< SPI3 Alternate Function mapping 0001*/
+#define AFIO_MAP5_SPI3_0010         ((uint32_t)0x80000162)  /*!< SPI3 Alternate Function mapping 0010*/
+#define AFIO_MAP5_SPI3_0011         ((uint32_t)0x80000163)  /*!< SPI3 Alternate Function mapping 0011*/
+#define AFIO_MAP5_SPI4_0001         ((uint32_t)0x80000171)  /*!< SPI4 Alternate Function mapping 0001*/
+#define AFIO_MAP5_SPI4_0010         ((uint32_t)0x80000172)  /*!< SPI4 Alternate Function mapping 0010*/
+#define AFIO_MAP5_SPI4_0011         ((uint32_t)0x80000173)  /*!< SPI4 Alternate Function mapping 0011*/
+
+#define AFIO_MAP6_CAN1_0010         ((uint32_t)0x80000182)  /*!< CAN1 Alternate Function mapping 0010*/
+#define AFIO_MAP6_CAN1_0011         ((uint32_t)0x80000183)  /*!< CAN1 Alternate Function mapping 0011*/
+#define AFIO_MAP6_CAN2_0001         ((uint32_t)0x80000191)  /*!< CAN2 Alternate Function mapping */
+#define AFIO_MAP6_SDIO_0100         ((uint32_t)0x800001A4)  /*!< SDIO Alternate Function mapping 100 */
+#define AFIO_MAP6_SDIO_0101         ((uint32_t)0x800001A5)  /*!< SDIO Alternate Function mapping 101 */
+#define AFIO_MAP6_SDIO_0110         ((uint32_t)0x800001A6)  /*!< SDIO Alternate Function mapping 110 */
+#define AFIO_MAP6_SDIO_0111         ((uint32_t)0x800001A7)  /*!< SDIO Alternate Function mapping 111 */
+#define AFIO_MAP6_SDIO2_0001        ((uint32_t)0x800001B1)  /*!< SDIO2 Alternate Function mapping 0001 */
+#define AFIO_MAP6_SDIO2_0010        ((uint32_t)0x800001B2)  /*!< SDIO2 Alternate Function mapping 0010 */
+#define AFIO_MAP6_SDIO2_0011        ((uint32_t)0x800001B3)  /*!< SDIO2 Alternate Function mapping 0011 */
+#define AFIO_MAP6_USART1_0001       ((uint32_t)0x800001C1)  /*!< USART1 Alternate Function mapping */
+#define AFIO_MAP6_USART2_0001       ((uint32_t)0x800001D1)  /*!< USART2 Alternate Function mapping */
+#define AFIO_MAP6_USART3_0001       ((uint32_t)0x800001E1)  /*!< USART3 Alternate Function mapping 0001*/
+#if defined (AT32F415xx)
+#define AFIO_MAP6_USART3_0010       ((uint32_t)0x800001E2)  /*!< USART3 Alternate Function mapping 0010*/
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define AFIO_MAP6_USART3_0011       ((uint32_t)0x800001E3)  /*!< USART3 Alternate Function mapping 0011*/
+#endif
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+#define AFIO_MAP6_UART4_0010        ((uint32_t)0x800001F2)  /*!< UART4 Alternate Function mapping */
+#else
+#define AFIO_MAP6_UART4_0001        ((uint32_t)0x800001F1)  /*!< UART4 Alternate Function mapping */
+#endif
+
+#define AFIO_MAP7_SPIF_1000         ((uint32_t)0x80000208)  /*!< Enable EXT_FLASH interface and bit[2:0] = 000 */ 
+#define AFIO_MAP7_SPIF_1001         ((uint32_t)0x80000209)  /*!< Enable EXT_FLASH interface and bit[2:0] = 001 */ 
+#define AFIO_MAP7_ADC1_0001         ((uint32_t)0x80000211)  /*!< ADC1 External Trigger Injected Conversion remapping */
+#define AFIO_MAP7_ADC1_0010         ((uint32_t)0x80000212)  /*!< ADC1 External Trigger Regular Conversion remapping */
+#define AFIO_MAP7_ADC1_0011         ((uint32_t)0x80000213)  /*!< ADC1 External Trigger Regular & Injected Conversion remapping */
+#define AFIO_MAP7_ADC2_0001         ((uint32_t)0x80000221)  /*!< ADC2 External Trigger Injected Conversion remapping */
+#define AFIO_MAP7_ADC2_0010         ((uint32_t)0x80000222)  /*!< ADC2 External Trigger Regular Conversion remapping */
+#define AFIO_MAP7_ADC2_0011         ((uint32_t)0x80000223)  /*!< ADC2 External Trigger Regular & Injected Conversion remapping */
+#define AFIO_MAP7_SWJTAG_0001       ((uint32_t)0x80000241)  /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define AFIO_MAP7_SWJTAG_0010       ((uint32_t)0x80000242)  /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAP7_SWJTAG_0100       ((uint32_t)0x80000244)  /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define AFIO_MAP7_PD01_0001         ((uint32_t)0x80000251)  /*!< PD0/PD1 mapping on OSC_IN/OSC_OUT */  
+#define AFIO_MAP7_XMC_0001          ((uint32_t)0x80000261)  /*!< XMC_NADV connect to Pin and bit[26:24] = 001 */
+#define AFIO_MAP7_XMC_0010          ((uint32_t)0x80000262)  /*!< XMC_NADV connect to Pin and bit[26:24] = 010 */
+#define AFIO_MAP7_XMC_1000          ((uint32_t)0x80000268)  /*!< XMC_NADV not using and bit[26:24] = 000 */
+#define AFIO_MAP7_XMC_1001          ((uint32_t)0x80000269)  /*!< XMC_NADV not using and bit[26:24] = 001 */
+#define AFIO_MAP7_XMC_1010          ((uint32_t)0x8000026A)  /*!< XMC_NADV not using and bit[26:24] = 010 */
+
+#define AFIO_MAP8_ETH_0001          ((uint32_t)0x800002C1)  /*!< ETH Alternate Function mapping 0001*/
+#define AFIO_MAP8_ETH_0100          ((uint32_t)0x800002C4)  /*!< ETH Alternate Function mapping 0100*/
+#define AFIO_MAP8_ETH_0101          ((uint32_t)0x800002C5)  /*!< ETH Alternate Function mapping 0101*/
+#define AFIO_MAP8_ETH_1000          ((uint32_t)0x800002C8)  /*!< ETH Alternate Function mapping 1000*/
+#define AFIO_MAP8_ETH_1001          ((uint32_t)0x800002C9)  /*!< ETH Alternate Function mapping 1001*/
+#define AFIO_MAP8_ETH_1100          ((uint32_t)0x800002CC)  /*!< ETH Alternate Function mapping 1100*/
+#define AFIO_MAP8_ETH_1101          ((uint32_t)0x800002CD)  /*!< ETH Alternate Function mapping 1101*/
+#define AFIO_MAP8_USART6_0001       ((uint32_t)0x800002D1)  /*!< USART6 Alternate Function mapping */
+#define AFIO_MAP8_UART7_0001        ((uint32_t)0x800002E1)  /*!< UART7 Alternate Function mapping */
+#define AFIO_MAP8_UART8_0001        ((uint32_t)0x800002F1)  /*!< UART8 Alternate Function mapping */
+
+#ifdef AT32F413xx
+#define AFIO_MAP4_TMR2_0001         ((uint32_t)0x80000091)  /*!< TMR2 Alternate Function mapping 1001*/
+#define AFIO_MAP4_TMR2_0010         ((uint32_t)0x80000092)  /*!< TMR2 Alternate Function mapping 1010*/
+#define AFIO_MAP4_TMR2_0011         ((uint32_t)0x80000093)  /*!< TMR2 Alternate Function mapping 1011*/
+#define AFIO_MAP4_TMR2_1001         ((uint32_t)0x80000099)  /*!< TMR2 Alternate Function mapping 1001*/
+#define AFIO_MAP4_TMR2_1010         ((uint32_t)0x8000009A)  /*!< TMR2 Alternate Function mapping 1010*/
+#define AFIO_MAP4_TMR2_1011         ((uint32_t)0x8000009B)  /*!< TMR2 Alternate Function mapping 1011*/
+#define AFIO_MAP4_TMR5_0001         ((uint32_t)0x800000C1)  /*!< TMR5 Alternate Function mapping 0001: CH1/CH2*/
+#define AFIO_MAP4_TMR5_1001         ((uint32_t)0x800000C9)  /*!< TMR5 Alternate Function mapping 1001: CH1/CH2+CH4 */
+#endif
+
+#ifdef AT32F415xx
+#define AFIO_MAP4_TMR1_0010         ((uint32_t)0x80000082)  /*!< TMR1 Alternate Function mapping 0010*/
+#define AFIO_MAP4_TMR2_0001         ((uint32_t)0x80000091)  /*!< TMR2 Alternate Function mapping 0001*/
+#define AFIO_MAP4_TMR2_0010         ((uint32_t)0x80000092)  /*!< TMR2 Alternate Function mapping 0010*/
+#define AFIO_MAP4_TMR2_0011         ((uint32_t)0x80000093)  /*!< TMR2 Alternate Function mapping 0011*/
+#define AFIO_MAP4_TMR5_0001         ((uint32_t)0x800000C1)  /*!< TMR5 Alternate Function mapping 0001: CH1/CH2*/
+#define AFIO_MAP4_TMR5_1001         ((uint32_t)0x800000C9)  /*!< TMR5 Alternate Function mapping 1001: CH1/CH2+CH4 */
+
+#define AFIO_MAP8_TMR1_BK1_00       ((uint32_t)0x80000280)  /*!< TMR1 BK1 input selection 00/01*/
+#define AFIO_MAP8_TMR1_BK1_10       ((uint32_t)0x80000282)  /*!< TMR1 BK1 input selection 10   */
+#define AFIO_MAP8_TMR1_BK1_11       ((uint32_t)0x80000283)  /*!< TMR1 BK1 input selection 11   */
+#define AFIO_MAP8_TMR1_CH1_00       ((uint32_t)0x80000290)  /*!< TMR1 CH1 input selection 00/01*/
+#define AFIO_MAP8_TMR1_CH1_10       ((uint32_t)0x80000298)  /*!< TMR1 CH1 input selection 10   */
+#define AFIO_MAP8_TMR1_CH1_11       ((uint32_t)0x8000029C)  /*!< TMR1 CH1 input selection 11   */
+#define AFIO_MAP8_TMR2_CH4_00       ((uint32_t)0x800002A0)  /*!< TMR2 CH4 input selection 00/01*/
+#define AFIO_MAP8_TMR2_CH4_10       ((uint32_t)0x800002A2)  /*!< TMR2 CH4 input selection 10   */
+#define AFIO_MAP8_TMR2_CH4_11       ((uint32_t)0x800002A3)  /*!< TMR2 CH4 input selection 11   */
+#define AFIO_MAP8_TMR3_CH1_00       ((uint32_t)0x800002B0)  /*!< TMR3 CH1 input selection 00/01*/
+#define AFIO_MAP8_TMR3_CH1_10       ((uint32_t)0x800002B8)  /*!< TMR3 CH1 input selection 10   */
+#define AFIO_MAP8_TMR3_CH1_11       ((uint32_t)0x800002BC)  /*!< TMR3 CH1 input selection 11   */
+#endif
+
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+#define AFIO_MAP4_TMR1_0011         ((uint32_t)0x80000083)  /*!< TMR1 Alternate Function mapping 0011*/
+#define AFIO_MAP4_TMR2_0001         ((uint32_t)0x80000091)  /*!< TMR2 Alternate Function mapping bit[5:4] = 01*/
+#define AFIO_MAP4_TMR2_0010         ((uint32_t)0x80000092)  /*!< TMR2 Alternate Function mapping bit[5:4] = 10*/
+#define AFIO_MAP4_TMR2_0011         ((uint32_t)0x80000093)  /*!< TMR2 Alternate Function mapping bit[5:4] = 11*/
+#define AFIO_MAP4_TIM2ITR1_1000     ((uint32_t)0x80000098)  /*!< ETH PTP as input to TMR2_ITR1 */
+#define AFIO_MAP4_TIM2ITR1_1100     ((uint32_t)0x8000009C)  /*!< USBDEV SOF as input to TMR2_ITR1 */
+#define AFIO_MAP4_TMR4_0001         ((uint32_t)0x800000B1)  /*!< TMR5 Alternate Function mapping 0001: CH1/CH2*/
+#endif
+
+#define IS_GREMAP(REMAP)            ((REMAP) > 0x80000000)
+
+#define IS_GPIO_GREMAP(REMAP)        (((REMAP) == AFIO_MAP3_TMR9_0010)    || ((REMAP) == AFIO_MAP3_TMR10_0010)    || \
+                                     ((REMAP) == AFIO_MAP3_TMR11_0010)    || ((REMAP) == AFIO_MAP4_TMR1_0001)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR2_0001)     || ((REMAP) == AFIO_MAP6_CAN1_0010)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR2_0010)     || ((REMAP) == AFIO_MAP6_CAN2_0001)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR2_0011)     || ((REMAP) == AFIO_MAP6_SDIO_0100)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR3_0010)     || ((REMAP) == AFIO_MAP6_SDIO_0101)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR3_0011)     || ((REMAP) == AFIO_MAP6_SDIO_0110)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR5_0001)     || ((REMAP) == AFIO_MAP6_SDIO_0111)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR5_1000)     || ((REMAP) == AFIO_MAP6_USART1_0001)   || \
+                                     ((REMAP) == AFIO_MAP4_TMR5_1001)     || ((REMAP) == AFIO_MAP6_USART3_0001)   || \
+                                     ((REMAP) == AFIO_MAP5_I2C1_0001)     || ((REMAP) == AFIO_MAP6_UART4_0001)    || \
+                                     ((REMAP) == AFIO_MAP5_I2C1_0011)     || ((REMAP) == AFIO_MAP7_SPIF_1000)     || \
+                                     ((REMAP) == AFIO_MAP5_I2C2_0001)     || ((REMAP) == AFIO_MAP7_SPIF_1001)     || \
+                                     ((REMAP) == AFIO_MAP5_I2C2_0010)     || ((REMAP) == AFIO_MAP7_ADC1_0001)     || \
+                                     ((REMAP) == AFIO_MAP5_I2C2_0011)     || ((REMAP) == AFIO_MAP7_ADC1_0010)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI1_0001)     || ((REMAP) == AFIO_MAP7_ADC2_0001)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI2_0001)     || ((REMAP) == AFIO_MAP7_ADC2_0010)     || \
+                                     ((REMAP) == AFIO_MAP7_SWJTAG_0010)   || ((REMAP) == AFIO_MAP7_SWJTAG_0001)   || \
+                                     ((REMAP) == AFIO_MAP7_SWJTAG_0100)   || ((REMAP) == AFIO_MAP7_PD01_0001)     || \
+                                     ((REMAP) == AFIO_MAP8_TMR1_BK1_00)   || ((REMAP) == AFIO_MAP8_TMR1_BK1_10)   || \
+                                     ((REMAP) == AFIO_MAP8_TMR1_BK1_11)   || ((REMAP) == AFIO_MAP8_TMR1_CH1_00)   || \
+                                     ((REMAP) == AFIO_MAP8_TMR1_CH1_10)   || ((REMAP) == AFIO_MAP8_TMR1_CH1_11)   || \
+                                     ((REMAP) == AFIO_MAP8_TMR2_CH4_00)   || ((REMAP) == AFIO_MAP8_TMR2_CH4_10)   || \
+                                     ((REMAP) == AFIO_MAP8_TMR2_CH4_11)   || ((REMAP) == AFIO_MAP8_TMR3_CH1_00)   || \
+                                     ((REMAP) == AFIO_MAP8_TMR3_CH1_10)   || ((REMAP) == AFIO_MAP8_TMR3_CH1_11)   || \
+                                     ((REMAP) == AFIO_MAP4_TMR1_0011)     || ((REMAP) == AFIO_MAP4_TMR4_0001)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR2_1001)     || ((REMAP) == AFIO_MAP4_TMR2_1010)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR2_1011)     || ((REMAP) == AFIO_MAP4_TMR2_1101)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR2_1110)     || ((REMAP) == AFIO_MAP4_TMR2_1111)     || \
+                                     ((REMAP) == AFIO_MAP5_USART5_0001)   || ((REMAP) == AFIO_MAP5_I2C3_0001)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI1_0010)     || ((REMAP) == AFIO_MAP5_SPI1_0011)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI2_0010)     || ((REMAP) == AFIO_MAP5_SPI3_0001)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI3_0010)     || ((REMAP) == AFIO_MAP5_SPI3_0011)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI4_0001)     || ((REMAP) == AFIO_MAP5_SPI4_0010)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI4_0011)     || ((REMAP) == AFIO_MAP6_CAN1_0011)     || \
+                                     ((REMAP) == AFIO_MAP6_SDIO2_0001)    || ((REMAP) == AFIO_MAP6_SDIO2_0010)    || \
+                                     ((REMAP) == AFIO_MAP6_SDIO2_0011)    || ((REMAP) == AFIO_MAP6_USART2_0001)   || \
+                                     ((REMAP) == AFIO_MAP6_USART3_0011)   || ((REMAP) == AFIO_MAP7_ADC1_0011)     || \
+                                     ((REMAP) == AFIO_MAP7_ADC2_0011)     || ((REMAP) == AFIO_MAP7_XMC_0001)      || \
+                                     ((REMAP) == AFIO_MAP7_XMC_0010)      || ((REMAP) == AFIO_MAP7_XMC_1001)      || \
+                                     ((REMAP) == AFIO_MAP7_XMC_1010)      || ((REMAP) == AFIO_MAP8_ETH_0001)      || \
+                                     ((REMAP) == AFIO_MAP8_ETH_0100)      || ((REMAP) == AFIO_MAP8_ETH_0101)      || \
+                                     ((REMAP) == AFIO_MAP8_ETH_1000)      || ((REMAP) == AFIO_MAP8_ETH_1001)      || \
+                                     ((REMAP) == AFIO_MAP8_ETH_1100)      || ((REMAP) == AFIO_MAP8_ETH_1101)      || \
+                                     ((REMAP) == AFIO_MAP8_USART6_0001)   || ((REMAP) == AFIO_MAP8_UART7_0001)    || \
+                                     ((REMAP) == AFIO_MAP8_UART8_0001)    || ((REMAP) == AFIO_MAP4_TIM2ITR1_1000) || \
+                                     ((REMAP) == AFIO_MAP4_TIM2ITR1_1100) || ((REMAP) == AFIO_MAP7_XMC_1000))
+                                     
+/**
+  * @}
+  */ 
+#endif
+
+/** @defgroup GPIO_Port_Sources 
+  * @{
+  */
+
+#define GPIO_PortSourceGPIOA       ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB       ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC       ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD       ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE       ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF       ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG       ((uint8_t)0x06)
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOE))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE)     (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOG))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Pin_sources 
+  * @{
+  */
+
+#define GPIO_PinsSource0            ((uint8_t)0x00)
+#define GPIO_PinsSource1            ((uint8_t)0x01)
+#define GPIO_PinsSource2            ((uint8_t)0x02)
+#define GPIO_PinsSource3            ((uint8_t)0x03)
+#define GPIO_PinsSource4            ((uint8_t)0x04)
+#define GPIO_PinsSource5            ((uint8_t)0x05)
+#define GPIO_PinsSource6            ((uint8_t)0x06)
+#define GPIO_PinsSource7            ((uint8_t)0x07)
+#define GPIO_PinsSource8            ((uint8_t)0x08)
+#define GPIO_PinsSource9            ((uint8_t)0x09)
+#define GPIO_PinsSource10           ((uint8_t)0x0A)
+#define GPIO_PinsSource11           ((uint8_t)0x0B)
+#define GPIO_PinsSource12           ((uint8_t)0x0C)
+#define GPIO_PinsSource13           ((uint8_t)0x0D)
+#define GPIO_PinsSource14           ((uint8_t)0x0E)
+#define GPIO_PinsSource15           ((uint8_t)0x0F)
+
+#define IS_GPIO_PINS_SOURCE(PINSSOURCE) (((PINSSOURCE) == GPIO_PinsSource0)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource1)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource2)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource3)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource4)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource5)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource6)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource7)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource8)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource9)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource10) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource11) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource12) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource13) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource14) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource15))
+
+/**
+  * @}
+  */
+                                             
+/** @defgroup Ethernet_Media_Interface 
+  * @{
+  */ 
+#define GPIO_ETH_MediaInterface_MII    ((uint32_t)0x00000000) 
+#define GPIO_ETH_MediaInterface_RMII   ((uint32_t)0x00000001)                                       
+
+#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
+                                                ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
+                                                
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions
+  * @{
+  */
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinsRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
+void GPIO_Reset(GPIO_Type* GPIOx);
+void GPIO_AFIOReset(void);
+void GPIO_Init(GPIO_Type* GPIOx, GPIO_InitType* GPIO_InitStruct);
+void GPIO_ResetBits(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin, BitState BitVal);
+void GPIO_Write(GPIO_Type* GPIOx, uint16_t PortVal);
+void GPIO_PinsLockConfig(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+#if defined (AT32F403Axx) || defined (AT32F407xx) 
+void GPIO_PinsEnhanceSlewRate(GPIO_Type* GPIOx, uint16_t GPIO_Pin, FunctionalState NewState);
+void GPIO_PinsHugeDriven(GPIO_Type* GPIOx, uint16_t GPIO_Pin, FunctionalState NewState);
+#endif
+void GPIO_StructInit(GPIO_InitType* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_Type* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_Type* GPIOx);
+void GPIO_SetBits(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+
+#endif /* AT32F403xx || AT32F413xx || AT32F415xx
+          AT32F403Axx|| AT32F407xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_GPIO_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_gpio_ex.h

@@ -0,0 +1,351 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_gpio_ex.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx GPIO extended header file
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_GPIO_EX_H
+#define __AT32F4XX_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+#if defined (AT32F421xx)
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Types
+  * @{
+  */
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOF))
+
+                                     
+/** 
+  * @brief  Output Maximum frequency selection  
+  */
+
+typedef enum
+{
+  GPIO_MaxSpeed_10MHz = 1,
+  GPIO_MaxSpeed_2MHz,
+  GPIO_MaxSpeed_50MHz = 2
+}GPIOMaxSpeed_Type;
+
+#define IS_GPIO_MAXSPEED(MAXSPEED) (((MAXSPEED) == GPIO_MaxSpeed_10MHz) ||\
+                                    ((MAXSPEED) == GPIO_MaxSpeed_2MHz)  || \
+                                    ((MAXSPEED) == GPIO_MaxSpeed_50MHz))
+
+/** 
+  * @brief  Configuration Mode enumeration  
+  */
+
+typedef enum
+{
+  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode              */
+  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode             */
+  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
+  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog In/Out Mode      */
+}GPIOMode_Type;
+
+#define IS_GPIO_MDE(MDE) (((MDE) == GPIO_Mode_IN) || ((MDE) == GPIO_Mode_OUT) || \
+                          ((MDE) == GPIO_Mode_AF) || ((MDE) == GPIO_Mode_AN))
+
+/** 
+  * @brief Output_type_enumeration
+  */
+typedef enum
+{
+  GPIO_OutType_PP = 0x00,
+  GPIO_OutType_OD = 0x01
+}GPIOOut_Type;
+
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OutType_PP) || ((OTYPE) == GPIO_OutType_OD))
+
+/** 
+  * @brief Configuration_Pull-Up_Pull-Down_enumeration 
+  */
+typedef enum
+{
+  GPIO_Pull_NOPULL = 0x00,
+  GPIO_Pull_PU     = 0x01,
+  GPIO_Pull_PD     = 0x02
+}GPIOPull_Type;
+
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_Pull_NOPULL) || ((PUPD) == GPIO_Pull_PU) || \
+                            ((PUPD) == GPIO_Pull_PD))
+
+/** 
+  * @brief  GPIO Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t GPIO_Pins;               /*!< Specifies the GPIO pins to be configured.
+                                      This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOMaxSpeed_Type GPIO_MaxSpeed;  /*!< Specifies the speed for the selected pins.
+                                      This parameter can be a value of @ref GPIOMaxSpeed_Type */
+
+  GPIOMode_Type GPIO_Mode;          /*!< Specifies the operating mode for the selected pins.
+                                      This parameter can be a value of @ref GPIOMode_Type */
+
+  GPIOOut_Type GPIO_OutType;   /*!< Specifies the operating output type for the selected pins.
+                                       This parameter can be a value of @ref GPIOOut_Type  */
+
+  GPIOPull_Type GPIO_Pull;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                                       This parameter can be a value of @ref GPIOPull_Type   */
+}GPIO_InitType;
+
+
+/** 
+  * @brief  Bit_SET and Bit_RESET enumeration  
+  */
+
+typedef enum
+{
+  Bit_RESET = 0,
+  Bit_SET
+}BitState;
+
+#define IS_GPIO_BIT_STATE(STATE) (((STATE) == Bit_RESET) || ((STATE) == Bit_SET))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define 
+  * @{
+  */
+
+#define GPIO_Pins_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */
+#define GPIO_Pins_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */
+#define GPIO_Pins_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */
+#define GPIO_Pins_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */
+#define GPIO_Pins_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */
+#define GPIO_Pins_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */
+#define GPIO_Pins_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */
+#define GPIO_Pins_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */
+#define GPIO_Pins_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */
+#define GPIO_Pins_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */
+#define GPIO_Pins_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */
+#define GPIO_Pins_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */
+#define GPIO_Pins_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */
+#define GPIO_Pins_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */
+#define GPIO_Pins_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */
+#define GPIO_Pins_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */
+#define GPIO_Pins_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
+
+#define IS_GPIO_PINS(PINS) ((((PINS) & (uint16_t)0x00) == 0x00) && ((PINS) != (uint16_t)0x00))
+
+#define IS_GET_GPIO_PINS(PINS)      (((PINS) == GPIO_Pins_0)  || \
+                                     ((PINS) == GPIO_Pins_1)  || \
+                                     ((PINS) == GPIO_Pins_2)  || \
+                                     ((PINS) == GPIO_Pins_3)  || \
+                                     ((PINS) == GPIO_Pins_4)  || \
+                                     ((PINS) == GPIO_Pins_5)  || \
+                                     ((PINS) == GPIO_Pins_6)  || \
+                                     ((PINS) == GPIO_Pins_7)  || \
+                                     ((PINS) == GPIO_Pins_8)  || \
+                                     ((PINS) == GPIO_Pins_9)  || \
+                                     ((PINS) == GPIO_Pins_10) || \
+                                     ((PINS) == GPIO_Pins_11) || \
+                                     ((PINS) == GPIO_Pins_12) || \
+                                     ((PINS) == GPIO_Pins_13) || \
+                                     ((PINS) == GPIO_Pins_14) || \
+                                     ((PINS) == GPIO_Pins_15))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIO_Port_Sources 
+  * @{
+  */
+
+#define GPIO_PortSourceGPIOA       ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB       ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC       ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOF       ((uint8_t)0x05)
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOC))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE)     (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOF))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Pin_sources 
+  * @{
+  */
+
+#define GPIO_PinsSource0            ((uint8_t)0x00)
+#define GPIO_PinsSource1            ((uint8_t)0x01)
+#define GPIO_PinsSource2            ((uint8_t)0x02)
+#define GPIO_PinsSource3            ((uint8_t)0x03)
+#define GPIO_PinsSource4            ((uint8_t)0x04)
+#define GPIO_PinsSource5            ((uint8_t)0x05)
+#define GPIO_PinsSource6            ((uint8_t)0x06)
+#define GPIO_PinsSource7            ((uint8_t)0x07)
+#define GPIO_PinsSource8            ((uint8_t)0x08)
+#define GPIO_PinsSource9            ((uint8_t)0x09)
+#define GPIO_PinsSource10           ((uint8_t)0x0A)
+#define GPIO_PinsSource11           ((uint8_t)0x0B)
+#define GPIO_PinsSource12           ((uint8_t)0x0C)
+#define GPIO_PinsSource13           ((uint8_t)0x0D)
+#define GPIO_PinsSource14           ((uint8_t)0x0E)
+#define GPIO_PinsSource15           ((uint8_t)0x0F)
+
+#define IS_GPIO_PINS_SOURCE(PINSSOURCE) (((PINSSOURCE) == GPIO_PinsSource0)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource1)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource2)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource3)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource4)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource5)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource6)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource7)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource8)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource9)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource10) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource11) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource12) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource13) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource14) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource15))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Alternate_function_selection_define 
+  * @{
+  */
+
+/** 
+  * @brief  AF 0 selection
+  */
+#define GPIO_AF_0            ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17,
+                                                MCO, SWDAT, SWCLK, TIM14, BOOT,
+                                                USART1, CEC, IR_OUT, SPI2 */
+/** 
+  * @brief  AF 1 selection
+  */
+#define GPIO_AF_1            ((uint8_t)0x01) /* USART2, CEC, Tim3, USART1, USART2,
+                                                EVENTOUT, I2C1, I2C2, TIM15 */
+/** 
+  * @brief  AF 2 selection
+  */
+#define GPIO_AF_2            ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17 */
+/** 
+  * @brief  AF 3 selection
+  */
+#define GPIO_AF_3            ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */
+
+/** 
+  * @brief  AF 4 selection
+  */
+#define GPIO_AF_4            ((uint8_t)0x04) /* TIM14 */
+/** 
+  * @brief  AF 5 selection
+  */
+#define GPIO_AF_5            ((uint8_t)0x05) /* TIM16, TIM17 */
+
+/** 
+  * @brief  AF 6 selection
+  */
+#define GPIO_AF_6            ((uint8_t)0x06) /* EVENTOUT */
+/** 
+  * @brief  AF 7 selection
+  */
+#define GPIO_AF_7            ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */
+
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \
+                          ((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \
+                          ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \
+                          ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7))
+                          
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions
+  * @{
+  */
+
+void GPIO_Reset(GPIO_Type* GPIOx);
+void GPIO_Init(GPIO_Type* GPIOx, GPIO_InitType* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitType* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_Type* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_Type* GPIOx);
+void GPIO_SetBits(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin, BitState BitVal);
+void GPIO_Write(GPIO_Type* GPIOx, uint16_t PortVal);
+void GPIO_PinsLockConfig(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+void GPIO_PinsEnhanceSlewRate(GPIO_Type* GPIOx, uint16_t GPIO_Pin, FunctionalState NewState);
+void GPIO_PinsHugeDriven(GPIO_Type* GPIOx, uint16_t GPIO_Pin, FunctionalState NewState);
+void GPIO_PinAFConfig(GPIO_Type* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+#if defined (AT32F421PF4P7) || defined (AT32F421PF8P7)
+void GPIO_F421PFxP7_LowPower(void);
+#endif /* AT32F421PF4P7 || AT32F421PF8P7 */
+#endif /* AT32F421xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_GPIO_EX_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_i2c.h

@@ -0,0 +1,683 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_i2c.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx I2C header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_I2C_H
+#define __AT32F4XX_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  I2C Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t I2C_BitRate;           /*!< Specifies the clock frequency.
+                                         This parameter must be set to a value lower than 400kHz */
+
+    uint16_t I2C_Mode;              /*!< Specifies the I2C mode.
+                                         This parameter can be a value of @ref I2C_mode */
+
+    uint16_t I2C_FmDutyCycle;       /*!< Specifies the I2C fast mode duty cycle.
+                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+    uint16_t I2C_OwnAddr1;          /*!< Specifies the first device own address.
+                                         This parameter can be a 7-bit or 10-bit address. */
+
+    uint16_t I2C_Ack;               /*!< Enables or disables the acknowledgement.
+                                         This parameter can be a value of @ref I2C_acknowledgement */
+
+    uint16_t I2C_AddrMode;          /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref I2C_acknowledged_address */
+} I2C_InitType;
+
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_Exported_Constants
+  * @{
+  */
+
+#if defined (AT32F413xx) || defined (AT32F415xx) || defined (AT32F421xx)
+#define IS_I2C_ALL_PERIPH(PERIPH)       (((PERIPH) == I2C1) || \
+                                         ((PERIPH) == I2C2))
+#elif defined (AT32F403xx) || defined (AT32F403Axx) || \
+      defined (AT32F407xx)
+#define IS_I2C_ALL_PERIPH(PERIPH)       (((PERIPH) == I2C1) || \
+                                         ((PERIPH) == I2C2) || \
+                                         ((PERIPH) == I2C3))
+#endif
+
+/** @defgroup I2C_mode
+  * @{
+  */
+
+#define I2C_Mode_I2CDevice              ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
+#define IS_I2C_MODE(MODE)               (((MODE) == I2C_Mode_I2CDevice) || \
+                                         ((MODE) == I2C_Mode_SMBusDevice) || \
+                                         ((MODE) == I2C_Mode_SMBusHost))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode
+  * @{
+  */
+
+#define I2C_FmDutyCycle_16_9            ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_FmDutyCycle_2_1             ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_FM_DUTY_CYCLE(CYCLE)     (((CYCLE) == I2C_FmDutyCycle_16_9) || \
+                                         ((CYCLE) == I2C_FmDutyCycle_2_1))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledgement
+  * @{
+  */
+
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE)         (((STATE) == I2C_Ack_Enable) || \
+                                         ((STATE) == I2C_Ack_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_transfer_direction
+  * @{
+  */
+
+#define  I2C_Direction_Transmit         ((uint8_t)0x00)
+#define  I2C_Direction_Receive          ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION)     (((DIRECTION) == I2C_Direction_Transmit) || \
+                                         ((DIRECTION) == I2C_Direction_Receive))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledged_address
+  * @{
+  */
+
+#define I2C_AddrMode_7bit               ((uint16_t)0x4000)
+#define I2C_AddrMode_10bit              ((uint16_t)0xC000)
+#define IS_I2C_ADDR_MODE(MODE)          (((MODE) == I2C_AddrMode_7bit) || \
+                                         ((MODE) == I2C_AddrMode_10bit))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_registers
+  * @{
+  */
+
+#define I2C_Register_CTRL1              ((uint8_t)0x00)
+#define I2C_Register_CTRL2              ((uint8_t)0x04)
+#define I2C_Register_OADDR1             ((uint8_t)0x08)
+#define I2C_Register_OADDR2             ((uint8_t)0x0C)
+#define I2C_Register_DT                 ((uint8_t)0x10)
+#define I2C_Register_STS1               ((uint8_t)0x14)
+#define I2C_Register_STS2               ((uint8_t)0x18)
+#define I2C_Register_CLKCTRL            ((uint8_t)0x1C)
+#define I2C_Register_TMRISE             ((uint8_t)0x20)
+#define IS_I2C_REGISTER(REGISTER)       (((REGISTER) == I2C_Register_CTRL1)  || \
+                                         ((REGISTER) == I2C_Register_CTRL2)  || \
+                                         ((REGISTER) == I2C_Register_OADDR1) || \
+                                         ((REGISTER) == I2C_Register_OADDR2) || \
+                                         ((REGISTER) == I2C_Register_DT)     || \
+                                         ((REGISTER) == I2C_Register_STS1)   || \
+                                         ((REGISTER) == I2C_Register_STS2)   || \
+                                         ((REGISTER) == I2C_Register_CLKCTRL)|| \
+                                         ((REGISTER) == I2C_Register_TMRISE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_SMBus_alert_pin_level
+  * @{
+  */
+
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
+#define IS_I2C_SMBUS_ALERT(ALERT)       (((ALERT) == I2C_SMBusAlert_Low) || \
+                                         ((ALERT) == I2C_SMBusAlert_High))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_PEC_position
+  * @{
+  */
+
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POSITION(POSITION)   (((POSITION) == I2C_PECPosition_Next) || \
+                                         ((POSITION) == I2C_PECPosition_Current))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NCAK_position
+  * @{
+  */
+
+#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
+                                         ((POSITION) == I2C_NACKPosition_Current))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_interrupts_definition
+  * @{
+  */
+
+#define I2C_INT_BUF                     ((uint16_t)0x0400)
+#define I2C_INT_EVT                     ((uint16_t)0x0200)
+#define I2C_INT_ERR                     ((uint16_t)0x0100)
+#define IS_I2C_CONFIG_INT(INT)          ((((INT) & (uint16_t)0xF8FF) == 0x00) && ((INT) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_interrupts_definition
+  * @{
+  */
+
+#define I2C_INT_SMBALERTF               ((uint32_t)0x01008000)
+#define I2C_INT_TIMOUT                  ((uint32_t)0x01004000)
+#define I2C_INT_PECERR                  ((uint32_t)0x01001000)
+#define I2C_INT_OVRUN                   ((uint32_t)0x01000800)
+#define I2C_INT_ACKFAIL                 ((uint32_t)0x01000400)
+#define I2C_INT_ARLOST                  ((uint32_t)0x01000200)
+#define I2C_INT_BUSERR                  ((uint32_t)0x01000100)
+#define I2C_INT_TDE                     ((uint32_t)0x06000080)
+#define I2C_INT_RDNE                    ((uint32_t)0x06000040)
+#define I2C_INT_STOPF                   ((uint32_t)0x02000010)
+#define I2C_INT_ADDR10F                 ((uint32_t)0x02000008)
+#define I2C_INT_BTFF                    ((uint32_t)0x02000004)
+#define I2C_INT_ADDRF                   ((uint32_t)0x02000002)
+#define I2C_INT_STARTF                  ((uint32_t)0x02000001)
+
+#define IS_I2C_CLEAR_INT(INT)           ((((INT) & (uint16_t)0x20FF) == 0x00) && ((INT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_INT(INT)             (((INT) == I2C_INT_SMBALERTF) || ((INT) == I2C_INT_TIMOUT) || \
+                                         ((INT) == I2C_INT_PECERR)    || ((INT) == I2C_INT_OVRUN)  || \
+                                         ((INT) == I2C_INT_ACKFAIL)   || ((INT) == I2C_INT_ARLOST) || \
+                                         ((INT) == I2C_INT_BUSERR)    || ((INT) == I2C_INT_TDE)    || \
+                                         ((INT) == I2C_INT_RDNE)      || ((INT) == I2C_INT_STOPF)  || \
+                                         ((INT) == I2C_INT_ADDR10F)   || ((INT) == I2C_INT_BTFF)   || \
+                                         ((INT) == I2C_INT_ADDRF)     || ((INT) == I2C_INT_STARTF))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_flags_definition
+  * @{
+  */
+
+/**
+  * @brief  SR2 register flags
+  */
+
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOSTADDRF           ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFTADDRF           ((uint32_t)0x00200000)
+#define I2C_FLAG_GCADDRF                ((uint32_t)0x00100000)
+#define I2C_FLAG_TRF                    ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSYF                  ((uint32_t)0x00020000)
+#define I2C_FLAG_MSF                    ((uint32_t)0x00010000)
+
+/**
+  * @brief  SR1 register flags
+  */
+
+#define I2C_FLAG_SMBALERTF              ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMOUT                 ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
+#define I2C_FLAG_OVRUN                  ((uint32_t)0x10000800)
+#define I2C_FLAG_ACKFAIL                ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLOST                 ((uint32_t)0x10000200)
+#define I2C_FLAG_BUSERR                 ((uint32_t)0x10000100)
+#define I2C_FLAG_TDE                    ((uint32_t)0x10000080)
+#define I2C_FLAG_RDNE                   ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
+#define I2C_FLAG_ADDR10F                ((uint32_t)0x10000008)
+#define I2C_FLAG_BTFF                   ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDRF                  ((uint32_t)0x10000002)
+#define I2C_FLAG_STARTF                 ((uint32_t)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG)         ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG)           (((FLAG) == I2C_FLAG_DUALF)        || ((FLAG) == I2C_FLAG_SMBHOSTADDRF) || \
+                                         ((FLAG) == I2C_FLAG_SMBDEFTADDRF) || ((FLAG) == I2C_FLAG_GCADDRF)      || \
+                                         ((FLAG) == I2C_FLAG_TRF)          || ((FLAG) == I2C_FLAG_BUSYF)        || \
+                                         ((FLAG) == I2C_FLAG_MSF)          || ((FLAG) == I2C_FLAG_SMBALERTF)    || \
+                                         ((FLAG) == I2C_FLAG_TIMOUT)       || ((FLAG) == I2C_FLAG_PECERR)       || \
+                                         ((FLAG) == I2C_FLAG_OVRUN)        || ((FLAG) == I2C_FLAG_ACKFAIL)      || \
+                                         ((FLAG) == I2C_FLAG_ARLOST)       || ((FLAG) == I2C_FLAG_BUSERR)       || \
+                                         ((FLAG) == I2C_FLAG_TDE)          || ((FLAG) == I2C_FLAG_RDNE)         || \
+                                         ((FLAG) == I2C_FLAG_STOPF)        || ((FLAG) == I2C_FLAG_ADDR10F)      || \
+                                         ((FLAG) == I2C_FLAG_BTFF)         || ((FLAG) == I2C_FLAG_ADDRF)        || \
+                                         ((FLAG) == I2C_FLAG_STARTF))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Events
+  * @{
+  */
+
+/*========================================
+
+                     I2C Master Events (Events grouped in order of communication)
+                                                        ==========================================*/
+/**
+  * @brief  Communication start
+  *
+  * After sending the START condition (I2C_GenerateSTART() function) the master
+  * has to wait for this event. It means that the Start condition has been correctly
+  * released on the I2C bus (the bus is free, no other devices is communicating).
+  *
+  */
+/* --EV5 */
+#define  I2C_EVENT_MASTER_START_GENERATED               ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
+
+/**
+  * @brief  Address Acknowledge
+  *
+  * After checking on EV5 (start condition correctly released on the bus), the
+  * master sends the address of the slave(s) with which it will communicate
+  * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
+  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
+  * his address. If an acknowledge is sent on the bus, one of the following events will
+  * be set:
+  *
+  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_ADDRESS_WITH_RECEIVER
+  *     event is set.
+  *
+  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_ADDRESS | I2C_EVENT_MASTER_TRANSMITTER
+  *     is set
+  *
+  *  3) In case of 10-Bit addressing mode, the master (just after generating the START
+  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
+  *  function). Then master should wait on EV9. It means that the 10-bit addressing
+  *  header has been correctly sent on the bus. Then master should send the second part of
+  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
+  *  should wait for event EV6.
+  *
+  */
+
+/* --EV6 */
+#define  I2C_EVENT_MASTER_ADDRESS                       ((uint32_t)0x00070002)  /* BUSY, MSL, ADDR and TRF flags */
+#define  I2C_EVENT_MASTER_TRANSMITTER                   ((uint32_t)0x00000080)  /* TDE flags */
+#define  I2C_EVENT_MASTER_ADDRESS_WITH_RECEIVER         ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define  I2C_EVENT_MASTER_ADDRESS10_GENERATED           ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
+
+/**
+  * @brief Communication events
+  *
+  * If a communication is established (START condition generated and slave address
+  * acknowledged) then the master has to check on one of the following events for
+  * communication procedures:
+  *
+  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
+  *    the data received from the slave (I2C_ReceiveData() function).
+  *
+  * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
+  *    function) then to wait on event EV8 or EV8_2.
+  *    These two events are similar:
+  *     - EV8 means that the data has been written in the data register and is
+  *       being shifted out.
+  *     - EV8_2 means that the data has been physically shifted out and output
+  *       on the bus.
+  *     In most cases, using EV8 is sufficient for the application.
+  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
+  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission
+  *     (before Stop condition generation).
+  *
+  *  @note In case the  user software does not guarantee that this event EV7 is
+  *  managed before the current byte end of transfer, then user may check on EV7
+  *  and BTF flag at the same time (ie. (I2C_EVENT_MASTER_DATA_RECEIVED | I2C_FLAG_BTFF)).
+  *  In this case the communication may be slower.
+  *
+  */
+
+/* Master RECEIVER mode -----------------------------*/
+/* --EV7 */
+#define  I2C_EVENT_MASTER_DATA_RECEIVED                 ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVENT_MASTER_DATA_TRANSMITTING              ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define  I2C_EVENT_MASTER_DATA_TRANSMITTED              ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/*========================================
+
+                     I2C Slave Events (Events grouped in order of communication)
+                                                        ==========================================*/
+
+/**
+  * @brief  Communication start events
+  *
+  * Wait on one of these events at the start of the communication. It means that
+  * the I2C peripheral detected a Start condition on the bus (generated by master
+  * device) followed by the peripheral address. The peripheral generates an ACK
+  * condition on the bus (if the acknowledge feature is enabled through function
+  * I2C_AcknowledgeConfig()) and the events listed above are set :
+  *
+  * 1) In normal case (only one address managed by the slave), when the address
+  *   sent by the master matches the own address of the peripheral (configured by
+  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
+  *   (where XXX could be TRANSMITTER or RECEIVER).
+  *
+  * 2) In case the address sent by the master matches the second address of the
+  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled
+  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
+  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
+  *
+  * 3) In case the address sent by the master is General Call (address 0x00) and
+  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
+  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
+  *
+  */
+
+/* --EV1  (all the events below are variants of EV1) */
+/* 1) Case of One Single Address managed by the slave */
+#define  I2C_EVENT_SLAVE_ADDRESS_RECEIVER_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define  I2C_EVENT_SLAVE_ADDRESS_TRANSMITTER_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define  I2C_EVENT_SLAVE_SECONDADDRESS_RECEIVER_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
+#define  I2C_EVENT_SLAVE_SECONDADDRESS_TRANSMITTER_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
+
+/**
+  * @brief  Communication events
+  *
+  * Wait on one of these events when EV1 has already been checked and:
+  *
+  * - Slave RECEIVER mode:
+  *     - EV2: When the application is expecting a data byte to be received.
+  *     - EV4: When the application is expecting the end of the communication: master
+  *       sends a stop condition and data transmission is stopped.
+  *
+  * - Slave Transmitter mode:
+  *    - EV3: When a byte has been transmitted by the slave and the application is expecting
+  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_DATA_TRANSMITTED and
+  *      I2C_EVENT_SLAVE_DATA_TRANSMITTING are similar. The second one can optionally be
+  *      used when the user software doesn't guarantee the EV3 is managed before the
+  *      current byte end of transfer.
+  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission
+  *      shall end (before sending the STOP condition). In this case slave has to stop sending
+  *      data bytes and expect a Stop condition on the bus.
+  *
+  *  @note In case the  user software does not guarantee that the event EV2 is
+  *  managed before the current byte end of transfer, then user may check on EV2
+  *  and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_DATA_RECEIVED | I2C_FLAG_BTFF)).
+  * In this case the communication may be slower.
+  *
+  */
+
+/* Slave RECEIVER mode --------------------------*/
+/* --EV2 */
+#define  I2C_EVENT_SLAVE_DATA_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
+/* --EV4  */
+#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define  I2C_EVENT_SLAVE_DATA_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
+#define  I2C_EVENT_SLAVE_DATA_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define  I2C_EVENT_SLAVE_ACK_FAILURE_DETECTED              ((uint32_t)0x00000400)  /* AF flag */
+
+/*===========================      End of Events Description           ==========================================*/
+
+#define IS_I2C_EVENT(EVENT)     (((EVENT) == I2C_EVENT_SLAVE_ADDRESS_TRANSMITTER_MATCHED)                || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_ADDRESS_RECEIVER_MATCHED)                   || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_SECONDADDRESS_TRANSMITTER_MATCHED)          || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_SECONDADDRESS_RECEIVER_MATCHED)             || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED)                 || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_DATA_RECEIVED)                              || \
+                                 ((EVENT) == (I2C_EVENT_SLAVE_DATA_RECEIVED | I2C_FLAG_DUALF))           || \
+                                 ((EVENT) == (I2C_EVENT_SLAVE_DATA_RECEIVED | I2C_FLAG_GCADDRF))         || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_DATA_TRANSMITTED)                           || \
+                                 ((EVENT) == (I2C_EVENT_SLAVE_DATA_TRANSMITTED | I2C_FLAG_DUALF))        || \
+                                 ((EVENT) == (I2C_EVENT_SLAVE_DATA_TRANSMITTED | I2C_FLAG_GCADDRF))      || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED)                              || \
+                                 ((EVENT) == I2C_EVENT_MASTER_START_GENERATED)                           || \
+                                 ((EVENT) == I2C_EVENT_MASTER_ADDRESS)                                   || \
+                                 ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER)                               || \
+                                 ((EVENT) == I2C_EVENT_MASTER_ADDRESS_WITH_RECEIVER)                     || \
+                                 ((EVENT) == I2C_EVENT_MASTER_DATA_RECEIVED)                             || \
+                                 ((EVENT) == I2C_EVENT_MASTER_DATA_TRANSMITTED)                          || \
+                                 ((EVENT) == I2C_EVENT_MASTER_DATA_TRANSMITTING)                         || \
+                                 ((EVENT) == I2C_EVENT_MASTER_ADDRESS10_GENERATED)                       || \
+                                 ((EVENT) == (I2C_EVENT_MASTER_ADDRESS | I2C_EVENT_MASTER_TRANSMITTER))  || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE_DETECTED))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_own_address1
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)       ((ADDRESS1) <= 0x3FF)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_clock_speed
+  * @{
+  */
+
+#define IS_I2C_BIT_RATE(RATE)               (((RATE) >= 0x1) && ((RATE) <= 400000))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions
+  * @{
+  */
+
+void I2C_DeInit(I2C_Type* I2Cx);
+void I2C_Init(I2C_Type* I2Cx, I2C_InitType* I2C_InitStruct);
+void I2C_StructInit(I2C_InitType* I2C_InitStruct);
+void I2C_Cmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_Type* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_INTConfig(I2C_Type* I2Cx, uint16_t I2C_INT, FunctionalState NewState);
+void I2C_SendData(I2C_Type* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_Type* I2Cx);
+void I2C_Send7bitAddress(I2C_Type* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_Type* I2Cx, uint8_t I2C_Register);
+void I2C_SoftwareResetCmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_NACKPositionConfig(I2C_Type* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_SMBusAlertConfig(I2C_Type* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_TransmitPEC(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_Type* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_Type* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_Type* I2Cx);
+void I2C_ARPCmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_Type* I2Cx, uint16_t I2C_DutyCycle);
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ *                         I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ *  depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ *    Using I2C_CheckEvent() function:
+ *    It compares the status registers (SR1 and SR2) content to a given event
+ *    (can be the combination of one or more flags).
+ *    It returns SUCCESS if the current status includes the given flags
+ *    and returns ERROR if one or more flags are missing in the current status.
+ *    - When to use:
+ *      - This function is suitable for most applications as well as for startup
+ *      activity since the events are fully described in the product reference manual
+ *      (RM0008).
+ *      - It is also suitable for users who need to define their own events.
+ *    - Limitations:
+ *      - If an error occurs (ie. error flags are set besides to the monitored flags),
+ *        the I2C_CheckEvent() function may return SUCCESS despite the communication
+ *        hold or corrupted real state.
+ *        In this case, it is advised to use error interrupts to monitor the error
+ *        events and handle them in the interrupt IRQ handler.
+ *
+ *        @note
+ *        For error management, it is advised to use the following functions:
+ *          - I2C_INTConfig() to configure and enable the error interrupts (I2C_INT_ERR).
+ *          - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ *            Where x is the peripheral instance (I2C1, I2C2 ...)
+ *          - I2C_GetFlagStatus() or I2C_GetINTStatus() to be called into I2Cx_ER_IRQHandler()
+ *            in order to determine which error occurred.
+ *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+ *            and/or I2C_GenerateStop() in order to clear the error flag and source,
+ *            and return to correct communication status.
+ *
+ *
+ *  2) Advanced state monitoring:
+ *     Using the function I2C_GetLastEvent() which returns the image of both status
+ *     registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ *     by 16 bits and concatenated to Status Register 1).
+ *     - When to use:
+ *       - This function is suitable for the same applications above but it allows to
+ *         overcome the limitations of I2C_GetFlagStatus() function (see below).
+ *         The returned value could be compared to events already defined in the
+ *         library (at32f4xx_i2c.h) or to custom values defined by user.
+ *       - This function is suitable when multiple flags are monitored at the same time.
+ *       - At the opposite of I2C_CheckEvent() function, this function allows user to
+ *         choose when an event is accepted (when all events flags are set and no
+ *         other flags are set or just when the needed flags are set like
+ *         I2C_CheckEvent() function).
+ *     - Limitations:
+ *       - User may need to define his own events.
+ *       - Same remark concerning the error management is applicable for this
+ *         function if user decides to check only regular communication flags (and
+ *         ignores error flags).
+ *
+ *
+ *  3) Flag-based state monitoring:
+ *     Using the function I2C_GetFlagStatus() which simply returns the status of
+ *     one single flag (ie. I2C_FLAG_RDNE ...).
+ *     - When to use:
+ *        - This function could be used for specific applications or in debug phase.
+ *        - It is suitable when only one flag checking is needed (most I2C events
+ *          are monitored through multiple flags).
+ *     - Limitations:
+ *        - When calling this function, the Status register is accessed. Some flags are
+ *          cleared when the status register is accessed. So checking the status
+ *          of one Flag, may clear other ones.
+ *        - Function may need to be called twice or more in order to monitor one
+ *          single event.
+ *
+ */
+
+/**
+ *
+ *  1) Basic state monitoring
+ *******************************************************************************
+ */
+ErrorStatus I2C_CheckEvent(I2C_Type* I2Cx, uint32_t I2C_EVENT);
+/**
+ *
+ *  2) Advanced state monitoring
+ *******************************************************************************
+ */
+uint32_t I2C_GetLastEvent(I2C_Type* I2Cx);
+/**
+ *
+ *  3) Flag-based state monitoring
+ *******************************************************************************
+ */
+FlagStatus I2C_GetFlagStatus(I2C_Type* I2Cx, uint32_t I2C_FLAG);
+/**
+ *
+ *******************************************************************************
+ */
+
+void I2C_ClearFlag(I2C_Type* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetINTStatus(I2C_Type* I2Cx, uint32_t I2C_INT);
+void I2C_ClearITPendingBit(I2C_Type* I2Cx, uint32_t I2C_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4XX_I2C_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_iwdg.h

@@ -0,0 +1,127 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_iwdg.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx IWDG header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_IWDG_H
+#define __AT32F4XX_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup IWDG
+  * @{
+  */
+
+/** @defgroup IWDG_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup IWDG_WriteAccess
+  * @{
+  */
+
+#define IWDG_KeyRegWrite_Enable             ((uint16_t)0x5555)
+#define IWDG_KeyRegWrite_Disable            ((uint16_t)0x0000)
+#define IS_IWDG_KEY_REG_WRITE(WRITE)        (((WRITE) == IWDG_KeyRegWrite_Enable) || \
+                                             ((WRITE) == IWDG_KeyRegWrite_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_prescaler
+  * @{
+  */
+
+#define IWDG_Psc_4                          ((uint8_t)0x00)
+#define IWDG_Psc_8                          ((uint8_t)0x01)
+#define IWDG_Psc_16                         ((uint8_t)0x02)
+#define IWDG_Psc_32                         ((uint8_t)0x03)
+#define IWDG_Psc_64                         ((uint8_t)0x04)
+#define IWDG_Psc_128                        ((uint8_t)0x05)
+#define IWDG_Psc_256                        ((uint8_t)0x06)
+#define IS_IWDG_PSC(PSC)                    (((PSC) == IWDG_Psc_4)  || \
+                                             ((PSC) == IWDG_Psc_8)  || \
+                                             ((PSC) == IWDG_Psc_16) || \
+                                             ((PSC) == IWDG_Psc_32) || \
+                                             ((PSC) == IWDG_Psc_64) || \
+                                             ((PSC) == IWDG_Psc_128)|| \
+                                             ((PSC) == IWDG_Psc_256))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag
+  * @{
+  */
+
+#define IWDG_FLAG_PSCF                      ((uint16_t)0x0001)
+#define IWDG_FLAG_RLDF                      ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG)                  (((FLAG) == IWDG_FLAG_PSCF) || ((FLAG) == IWDG_FLAG_RLDF))
+#define IS_IWDG_RLD(RLD)                      ((RLD) <= 0xFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Functions
+  * @{
+  */
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+void IWDG_KeyRegWrite(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_IWDG_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_pwr.h

@@ -0,0 +1,170 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_pwr.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx PWR header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_PWR_H
+#define __AT32F4XX_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Constants
+  * @{
+  */
+
+/** @defgroup PVD_detection_level
+  * @{
+  */
+
+#define PWR_PVDS_2V2                        ((uint32_t)0x00000000)
+#define PWR_PVDS_2V3                        ((uint32_t)0x00000020)
+#define PWR_PVDS_2V4                        ((uint32_t)0x00000040)
+#define PWR_PVDS_2V5                        ((uint32_t)0x00000060)
+#define PWR_PVDS_2V6                        ((uint32_t)0x00000080)
+#define PWR_PVDS_2V7                        ((uint32_t)0x000000A0)
+#define PWR_PVDS_2V8                        ((uint32_t)0x000000C0)
+#define PWR_PVDS_2V9                        ((uint32_t)0x000000E0)
+#define IS_PWR_PVD_LEVEL(LEVEL)             (((LEVEL) == PWR_PVDS_2V2) || ((LEVEL) == PWR_PVDS_2V3)|| \
+                                             ((LEVEL) == PWR_PVDS_2V4) || ((LEVEL) == PWR_PVDS_2V5)|| \
+                                             ((LEVEL) == PWR_PVDS_2V6) || ((LEVEL) == PWR_PVDS_2V7)|| \
+                                             ((LEVEL) == PWR_PVDS_2V8) || ((LEVEL) == PWR_PVDS_2V9))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry 
+  * @{
+  */
+
+#define PWR_SLEEPEntry_WFI              ((uint8_t)0x01)
+#define PWR_SLEEPEntry_WFE              ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
+
+/** @defgroup Regulator_state_is_STOP_mode
+  * @{
+  */
+#define PWR_Regulator_ON                    ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower              ((uint32_t)0x00000001)
+
+#if defined (AT32F421xx)
+#define PWR_Regulator_LowPower_Extra        ((uint32_t)0x00000021)
+#define IS_PWR_REGULATOR(REGULATOR)         (((REGULATOR) == PWR_Regulator_ON) || \
+                                             ((REGULATOR) == PWR_Regulator_LowPower) || \
+                                             ((REGULATOR) == PWR_Regulator_LowPower_Extra))
+#else
+#define IS_PWR_REGULATOR(REGULATOR)         (((REGULATOR) == PWR_Regulator_ON) || \
+                                             ((REGULATOR) == PWR_Regulator_LowPower))
+#endif
+                                             
+/**
+  * @}
+  */
+
+/** @defgroup STOP_mode_entry
+  * @{
+  */
+
+#define PWR_STOPEntry_WFI                   ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE                   ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY)            (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag
+  * @{
+  */
+
+#define PWR_FLAG_WUF                        ((uint32_t)0x00000001)
+#define PWR_FLAG_SBF                        ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO                       ((uint32_t)0x00000004)
+#define IS_PWR_GET_FLAG(FLAG)               (((FLAG) == PWR_FLAG_WUF) || ((FLAG) == PWR_FLAG_SBF) || \
+                                             ((FLAG) == PWR_FLAG_PVDO))
+
+#define IS_PWR_CLEAR_FLAG(FLAG)             (((FLAG) == PWR_FLAG_WUF) || ((FLAG) == PWR_FLAG_SBF))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions
+  * @{
+  */
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
+#if defined (AT32F403xx) || defined (AT32F413xx)
+    void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry);
+#else
+    void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+#endif
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+void PWR_Reset(void);
+void PWR_BackupAccessCtrl(FunctionalState NewState);
+void PWR_PVDCtrl(FunctionalState NewState);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinCtrl(FunctionalState NewState);
+#if defined (AT32F421xx)
+void PWR_WakeUpPinCtrl2(FunctionalState NewState);
+void PWR_WakeUpPinCtrl6(FunctionalState NewState);
+void PWR_WakeUpPinCtrl7(FunctionalState NewState);
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_PWR_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_rcc.h

@@ -0,0 +1,801 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_rcc.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx RCC header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_RCC_H
+#define __AT32F4XX_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/** @defgroup RCC_Exported_Types
+  * @{
+  */
+
+typedef struct
+{
+    uint32_t SYSCLK_Freq;     /*!< returns SYSCLK clock frequency expressed in Hz */
+    uint32_t AHBCLK_Freq;     /*!< returns HCLK clock frequency expressed in Hz */
+    uint32_t APB1CLK_Freq;    /*!< returns PCLK1 clock frequency expressed in Hz */
+    uint32_t APB2CLK_Freq;    /*!< returns PCLK2 clock frequency expressed in Hz */
+    uint32_t ADCCLK_Freq;     /*!< returns ADCCLK clock frequency expressed in Hz */
+} RCC_ClockType;
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup HSE_configuration
+  * @{
+  */
+
+#define RCC_HSE_DISABLE                 ((uint32_t)0x00000000)
+#define RCC_HSE_ENABLE                  ((uint32_t)0x00010000)
+#define RCC_HSE_BYPASS                  ((uint32_t)0x00040000)
+#define IS_RCC_HSE(HSE)                 (((HSE) == RCC_HSE_DISABLE) || \
+                                         ((HSE) == RCC_HSE_ENABLE)  || \
+                                         ((HSE) == RCC_HSE_BYPASS))
+
+/**
+  * @}
+  */
+
+/** @defgroup PLL_entry_clock_source
+  * @{
+  */
+
+#define RCC_PLLRefClk_HSI_Div2          ((uint32_t)0x00000000)
+
+#define RCC_PLLRefClk_HSE_Div1          ((uint32_t)0x00010000)
+#define RCC_PLLRefClk_HSE_Div2          ((uint32_t)0x00030000)
+#define IS_RCC_PLL_CFG(CFG)             (((CFG) == RCC_PLLRefClk_HSI_Div2) || \
+                                         ((CFG) == RCC_PLLRefClk_HSE_Div1) || \
+                                         ((CFG) == RCC_PLLRefClk_HSE_Div2))
+
+
+/**
+  * @}
+  */
+#define RCC_PLL_RANGE                   72000000
+/** @defgroup PLL_clock_range_setting
+  * @{
+  */
+#define RCC_Range_LessEqual_72Mhz       ((uint32_t)0x00000000)
+#define RCC_Range_GreatThan_72Mhz       ((uint32_t)0x80000000)
+#define IS_RCC_PLL_RANGE(CFG)           (((CFG) == RCC_Range_LessEqual_72Mhz) || \
+                                         ((CFG) == RCC_Range_GreatThan_72Mhz))
+/**
+  * @}
+  */
+/** @defgroup PLL_multiplication_factor
+  * @{
+  */
+#define RCC_PLLMult_2                   RCC_CFG_PLLMULT2
+#define RCC_PLLMult_3                   RCC_CFG_PLLMULT3
+#define RCC_PLLMult_4                   RCC_CFG_PLLMULT4
+#define RCC_PLLMult_5                   RCC_CFG_PLLMULT5
+#define RCC_PLLMult_6                   RCC_CFG_PLLMULT6
+#define RCC_PLLMult_7                   RCC_CFG_PLLMULT7
+#define RCC_PLLMult_8                   RCC_CFG_PLLMULT8
+#define RCC_PLLMult_9                   RCC_CFG_PLLMULT9
+#define RCC_PLLMult_10                  RCC_CFG_PLLMULT10
+#define RCC_PLLMult_11                  RCC_CFG_PLLMULT11
+#define RCC_PLLMult_12                  RCC_CFG_PLLMULT12
+#define RCC_PLLMult_13                  RCC_CFG_PLLMULT13
+#define RCC_PLLMult_14                  RCC_CFG_PLLMULT14
+#define RCC_PLLMult_15                  RCC_CFG_PLLMULT15
+#define RCC_PLLMult_16                  RCC_CFG_PLLMULT16
+#define RCC_PLLMult_17                  RCC_CFG_PLLMULT17 
+#define RCC_PLLMult_18                  RCC_CFG_PLLMULT18 
+#define RCC_PLLMult_19                  RCC_CFG_PLLMULT19 
+#define RCC_PLLMult_20                  RCC_CFG_PLLMULT20 
+#define RCC_PLLMult_21                  RCC_CFG_PLLMULT21 
+#define RCC_PLLMult_22                  RCC_CFG_PLLMULT22 
+#define RCC_PLLMult_23                  RCC_CFG_PLLMULT23 
+#define RCC_PLLMult_24                  RCC_CFG_PLLMULT24 
+#define RCC_PLLMult_25                  RCC_CFG_PLLMULT25 
+#define RCC_PLLMult_26                  RCC_CFG_PLLMULT26 
+#define RCC_PLLMult_27                  RCC_CFG_PLLMULT27 
+#define RCC_PLLMult_28                  RCC_CFG_PLLMULT28 
+#define RCC_PLLMult_29                  RCC_CFG_PLLMULT29 
+#define RCC_PLLMult_30                  RCC_CFG_PLLMULT30 
+#define RCC_PLLMult_31                  RCC_CFG_PLLMULT31 
+#define RCC_PLLMult_32                  RCC_CFG_PLLMULT32 
+#define RCC_PLLMult_33                  RCC_CFG_PLLMULT33 
+#define RCC_PLLMult_34                  RCC_CFG_PLLMULT34 
+#define RCC_PLLMult_35                  RCC_CFG_PLLMULT35 
+#define RCC_PLLMult_36                  RCC_CFG_PLLMULT36 
+#define RCC_PLLMult_37                  RCC_CFG_PLLMULT37 
+#define RCC_PLLMult_38                  RCC_CFG_PLLMULT38 
+#define RCC_PLLMult_39                  RCC_CFG_PLLMULT39 
+#define RCC_PLLMult_40                  RCC_CFG_PLLMULT40 
+#define RCC_PLLMult_41                  RCC_CFG_PLLMULT41 
+#define RCC_PLLMult_42                  RCC_CFG_PLLMULT42 
+#define RCC_PLLMult_43                  RCC_CFG_PLLMULT43 
+#define RCC_PLLMult_44                  RCC_CFG_PLLMULT44 
+#define RCC_PLLMult_45                  RCC_CFG_PLLMULT45 
+#define RCC_PLLMult_46                  RCC_CFG_PLLMULT46 
+#define RCC_PLLMult_47                  RCC_CFG_PLLMULT47 
+#define RCC_PLLMult_48                  RCC_CFG_PLLMULT48 
+#define RCC_PLLMult_49                  RCC_CFG_PLLMULT49 
+#define RCC_PLLMult_50                  RCC_CFG_PLLMULT50 
+#define RCC_PLLMult_51                  RCC_CFG_PLLMULT51 
+#define RCC_PLLMult_52                  RCC_CFG_PLLMULT52 
+#define RCC_PLLMult_53                  RCC_CFG_PLLMULT53 
+#define RCC_PLLMult_54                  RCC_CFG_PLLMULT54 
+#define RCC_PLLMult_55                  RCC_CFG_PLLMULT55 
+#define RCC_PLLMult_56                  RCC_CFG_PLLMULT56 
+#define RCC_PLLMult_57                  RCC_CFG_PLLMULT57 
+#define RCC_PLLMult_58                  RCC_CFG_PLLMULT58 
+#define RCC_PLLMult_59                  RCC_CFG_PLLMULT59 
+#define RCC_PLLMult_60                  RCC_CFG_PLLMULT60 
+#define RCC_PLLMult_61                  RCC_CFG_PLLMULT61 
+#define RCC_PLLMult_62                  RCC_CFG_PLLMULT62 
+#define RCC_PLLMult_63                  RCC_CFG_PLLMULT63 
+#define RCC_PLLMult_64                  RCC_CFG_PLLMULT64 
+#define IS_RCC_PLL_MULT(MULT)           (((MULT) & (~RCC_CFG_PLLMULT)) == 0x00000000)
+
+#define RCC_GET_PLLMULT(MULT)           ((((MULT & RCC_CFG_PLLMULT_LB_MASK) >> RCC_CFG_PLLMULT_LB_POS) | \
+                                            ((MULT & RCC_CFG_PLLMULT_HB_MASK) >> (RCC_CFG_PLLMULT_HB_POS - RCC_CFG_PLLMULT_HB_OFFSET))) +\
+                                          ((((MULT & RCC_CFG_PLLMULT_HB_MASK)==0) && \
+                                            ((MULT & RCC_CFG_PLLMULT_LB_MASK)!=RCC_CFG_PLLMULT_LB_MASK) )? 2 : 1 ))
+											
+/**
+  * @}
+  */
+/** @defgroup System_clock_source
+  * @{
+  */
+
+#define RCC_SYSCLKSelction_HSI          ((uint32_t)0x00000000)
+#define RCC_SYSCLKSelction_HSE          ((uint32_t)0x00000001)
+#define RCC_SYSCLKSelction_PLL          ((uint32_t)0x00000002)
+#define IS_RCC_SYSCLK_CFG(CFG)          (((CFG) == RCC_SYSCLKSelction_HSI) || \
+                                         ((CFG) == RCC_SYSCLKSelction_HSE) || \
+                                         ((CFG) == RCC_SYSCLKSelction_PLL))
+/**
+  * @}
+  */
+
+/** @defgroup AHB_clock_source
+  * @{
+  */
+
+#define RCC_SYSCLK_Div1                 ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2                 ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4                 ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8                 ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16                ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64                ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128               ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256               ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512               ((uint32_t)0x000000F0)
+#define IS_RCC_AHBCLK(CLK)              (((CLK) == RCC_SYSCLK_Div1)   || ((CLK) == RCC_SYSCLK_Div2)   || \
+                                         ((CLK) == RCC_SYSCLK_Div4)   || ((CLK) == RCC_SYSCLK_Div8)   || \
+                                         ((CLK) == RCC_SYSCLK_Div16)  || ((CLK) == RCC_SYSCLK_Div64)  || \
+                                         ((CLK) == RCC_SYSCLK_Div128) || ((CLK) == RCC_SYSCLK_Div256) || \
+                                         ((CLK) == RCC_SYSCLK_Div512))
+/**
+  * @}
+  */
+
+/** @defgroup APB1_APB2_clock_source
+  * @{
+  */
+
+#define RCC_AHBCLK_Div1                 ((uint32_t)0x00000000)
+#define RCC_AHBCLK_Div2                 ((uint32_t)0x00000400)
+#define RCC_AHBCLK_Div4                 ((uint32_t)0x00000500)
+#define RCC_AHBCLK_Div8                 ((uint32_t)0x00000600)
+#define RCC_AHBCLK_Div16                ((uint32_t)0x00000700)
+#define IS_RCC_APBCLK(CLK)              (((CLK) == RCC_AHBCLK_Div1) || ((CLK) == RCC_AHBCLK_Div2) || \
+                                         ((CLK) == RCC_AHBCLK_Div4) || ((CLK) == RCC_AHBCLK_Div8) || \
+                                         ((CLK) == RCC_AHBCLK_Div16))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt_source
+  * @{
+  */
+
+#define RCC_INT_LSISTBL                 ((uint8_t)0x01)
+#define RCC_INT_LSESTBL                 ((uint8_t)0x02)
+#define RCC_INT_HSISTBL                 ((uint8_t)0x04)
+#define RCC_INT_HSESTBL                 ((uint8_t)0x08)
+#define RCC_INT_PLLSTBL                 ((uint8_t)0x10)
+#define RCC_INT_HSECFD                  ((uint8_t)0x80)
+
+#define IS_RCC_INT_EN(INT)              ((((INT) & (uint8_t)0xE0) == 0x00) && ((INT) != 0x00))
+#define IS_RCC_INT_STS(INT)             (((INT) == RCC_INT_LSISTBL) || ((INT) == RCC_INT_LSESTBL) || \
+                                         ((INT) == RCC_INT_HSISTBL) || ((INT) == RCC_INT_HSESTBL) || \
+                                         ((INT) == RCC_INT_PLLSTBL) || ((INT) == RCC_INT_HSECFD))
+#define IS_RCC_INT_CLR(INT)             ((((INT) & (uint8_t)0x60) == 0x00) && ((INT) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup USB_Device_clock_source
+  * @{
+  */
+#define RCC_USBCLKSelection_PLL_Div1_5   ((uint32_t)0x00000000)
+#define RCC_USBCLKSelection_PLL_Div1     ((uint32_t)0x00400000)
+#define RCC_USBCLKSelection_PLL_Div2_5   ((uint32_t)0x00800000)
+#define RCC_USBCLKSelection_PLL_Div2     ((uint32_t)0x00C00000)
+#define RCC_USBCLKSelection_PLL_Div3_5   ((uint32_t)0x08000000)
+#define RCC_USBCLKSelection_PLL_Div3     ((uint32_t)0x08400000)
+#define RCC_USBCLKSelection_PLL_Div4     ((uint32_t)0x08800000)
+
+#define IS_RCC_USBCLK_CFG(CFG)      (((CFG) == RCC_USBCLKSelection_PLL_Div1_5) || \
+                                     ((CFG) == RCC_USBCLKSelection_PLL_Div1)   || \
+                                     ((CFG) == RCC_USBCLKSelection_PLL_Div2_5) || \
+                                     ((CFG) == RCC_USBCLKSelection_PLL_Div2)   || \
+																		 ((CFG) == RCC_USBCLKSelection_PLL_Div3_5) || \
+																		 ((CFG) == RCC_USBCLKSelection_PLL_Div3)   || \
+																		 ((CFG) == RCC_USBCLKSelection_PLL_Div4))						
+/**
+  * @}
+  */
+
+/** @defgroup ADC_clock_source
+  * @{
+  */
+
+#define RCC_APB2CLK_Div2            ((uint32_t)0x00000000)
+#define RCC_APB2CLK_Div4            ((uint32_t)0x00004000)
+#define RCC_APB2CLK_Div6            ((uint32_t)0x00008000)
+#define RCC_APB2CLK_Div8            ((uint32_t)0x0000C000)
+#define RCC_APB2CLK_Div12           ((uint32_t)0x10004000)
+#define RCC_APB2CLK_Div16           ((uint32_t)0x1000C000)
+#define IS_RCC_ADCCLK(CLK)          (((CLK) == RCC_APB2CLK_Div2) || ((CLK) == RCC_APB2CLK_Div4) || \
+                                     ((CLK) == RCC_APB2CLK_Div6) || ((CLK) == RCC_APB2CLK_Div8) || \
+                                     ((CLK) == RCC_APB2CLK_Div12)|| ((CLK) == RCC_APB2CLK_Div16))
+/**
+  * @}
+  */
+
+/** @defgroup LSE_configuration
+  * @{
+  */
+
+#define RCC_LSE_DISABLE             ((uint8_t)0x00)
+#define RCC_LSE_ENABLE              ((uint8_t)0x01)
+#define RCC_LSE_BYPASS              ((uint8_t)0x04)
+#define IS_RCC_LSE(LSE)             (((LSE) == RCC_LSE_DISABLE) || ((LSE) == RCC_LSE_ENABLE) || \
+                                     ((LSE) == RCC_LSE_BYPASS))
+/**
+  * @}
+  */
+
+
+#if defined (AT32F415xx) || defined (AT32F421xx)
+/** @defgroup ERTC_clock_source
+  * @{
+  */
+#define RCC_ERTCCLKSelection_LSE             ((uint32_t)0x00000100)
+#define RCC_ERTCCLKSelection_LSI             ((uint32_t)0x00000200)
+#define RCC_ERTCCLKSelection_HSE_Div128      ((uint32_t)0x00000300)
+#define IS_RCC_ERTCCLK_SEL(SEL)              (((SEL) == RCC_ERTCCLKSelection_LSE) || \
+                                              ((SEL)  == RCC_ERTCCLKSelection_LSI) || \
+                                              ((SEL)  == RCC_ERTCCLKSelection_HSE_Div128))
+#else
+/** @defgroup RTC_clock_source
+  * @{
+  */
+#define RCC_RTCCLKSelection_LSE             ((uint32_t)0x00000100)
+#define RCC_RTCCLKSelection_LSI             ((uint32_t)0x00000200)
+#define RCC_RTCCLKSelection_HSE_Div128      ((uint32_t)0x00000300)
+#define IS_RCC_RTCCLK_SEL(SEL)              (((SEL) == RCC_RTCCLKSelection_LSE) || \
+                                              ((SEL) == RCC_RTCCLKSelection_LSI) || \
+                                              ((SEL) == RCC_RTCCLKSelection_HSE_Div128))
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup AHB_peripheral
+  * @{
+  */
+
+#define RCC_AHBPERIPH_DMA1          ((uint32_t)0x00000001)
+#define RCC_AHBPERIPH_SRAM          ((uint32_t)0x00000004)
+#define RCC_AHBPERIPH_FLASH         ((uint32_t)0x00000010)
+#define RCC_AHBPERIPH_CRC           ((uint32_t)0x00000040)
+
+
+#if !defined (AT32F421xx)
+#define RCC_AHBPERIPH_DMA2          ((uint32_t)0x00000002)
+#define RCC_AHBPERIPH_SDIO1         ((uint32_t)0x00000400)
+#endif
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+#define RCC_AHBPERIPH_XMC           ((uint32_t)0x00000100)
+#define RCC_AHBPERIPH_SDIO2         ((uint32_t)0x00000800)
+#endif
+
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+#define RCC_AHBPERIPH_ETHMAC        ((uint32_t)0x00004000)
+#define RCC_AHBPERIPH_ETHMACTX      ((uint32_t)0x00008000)
+#define RCC_AHBPERIPH_ETHMACRX      ((uint32_t)0x00010000)
+#define RCC_AHBPERIPH_ETHMACPTP     ((uint32_t)0x10000000)
+#elif defined (AT32F415xx)
+#define RCC_AHBPERIPH_USB           ((uint32_t)0x00001000)
+#elif defined (AT32F421xx)
+#define RCC_AHBPERIPH_GPIOA         ((uint32_t)0x00020000)
+#define RCC_AHBPERIPH_GPIOB         ((uint32_t)0x00040000)
+#define RCC_AHBPERIPH_GPIOC         ((uint32_t)0x00080000)
+#define RCC_AHBPERIPH_GPIOF         ((uint32_t)0x00400000)
+#endif
+
+#if defined (AT32F403xx)
+#define IS_RCC_AHB_PERIPH(PERIPH)   ((((PERIPH) & 0xFFFFF2A8) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F413xx)
+#define IS_RCC_AHB_PERIPH(PERIPH)   ((((PERIPH) & 0xFFFFFBA8) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F415xx)
+#define IS_RCC_AHB_PERIPH(PERIPH)   ((((PERIPH) & 0xFFFFEBA8) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_RCC_AHB_PERIPH(PERIPH)   ((((PERIPH) & 0xEFFE32A8) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F421xx)
+#define IS_RCC_AHB_PERIPH(PERIPH)   ((((PERIPH) & 0xFFB1FFAA) == 0x00) && ((PERIPH) != 0x00))
+#endif
+
+
+/**
+  * @}
+  */
+
+/** @defgroup APB2_peripheral
+  * @{
+  */
+#define RCC_APB2PERIPH_ADC1         ((uint32_t)0x00000200)
+#define RCC_APB2PERIPH_TMR1         ((uint32_t)0x00000800)
+#define RCC_APB2PERIPH_SPI1         ((uint32_t)0x00001000)
+#define RCC_APB2PERIPH_USART1       ((uint32_t)0x00004000)
+
+#if !defined (AT32F421xx)
+#define RCC_APB2PERIPH_ADC2         ((uint32_t)0x00000400)
+#define RCC_APB2PERIPH_TMR9         ((uint32_t)0x00080000)
+#define RCC_APB2PERIPH_TMR10        ((uint32_t)0x00100000)
+#define RCC_APB2PERIPH_TMR11        ((uint32_t)0x00200000)
+#define RCC_APB2PERIPH_AFIO         ((uint32_t)0x00000001)
+#define RCC_APB2PERIPH_GPIOA        ((uint32_t)0x00000004)
+#define RCC_APB2PERIPH_GPIOB        ((uint32_t)0x00000008)
+#define RCC_APB2PERIPH_GPIOC        ((uint32_t)0x00000010)
+#define RCC_APB2PERIPH_GPIOD        ((uint32_t)0x00000020)
+#endif
+
+#if !defined (AT32F403Axx) && !defined (AT32F407xx) && \
+    !defined (AT32F421xx)
+#define RCC_APB2PERIPH_GPIOF        ((uint32_t)0x00000080)
+#endif
+
+#if defined (AT32F403xx)
+#define RCC_APB2PERIPH_GPIOE        ((uint32_t)0x00000040)
+#define RCC_APB2PERIPH_GPIOG        ((uint32_t)0x00000100)
+#define RCC_APB2PERIPH_ADC3         ((uint32_t)0x00008000)
+#define RCC_APB2PERIPH_TMR15        ((uint32_t)0x00010000)
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define RCC_APB2PERIPH_GPIOE        ((uint32_t)0x00000040)
+#define RCC_APB2PERIPH_ADC3         ((uint32_t)0x00008000)
+#define RCC_APB2PERIPH_I2C3         ((uint32_t)0x00800000)
+#define RCC_APB2PERIPH_USART6       ((uint32_t)0x01000000)
+#define RCC_APB2PERIPH_UART7        ((uint32_t)0x02000000)
+#define RCC_APB2PERIPH_UART8        ((uint32_t)0x04000000)
+#elif defined (AT32F421xx)
+#define RCC_APB2PERIPH_SYSCFGCOMP   ((uint32_t)0x00000001)
+#define RCC_APB2PERIPH_TMR15        ((uint32_t)0x00010000)
+#define RCC_APB2PERIPH_TMR16        ((uint32_t)0x00020000)
+#define RCC_APB2PERIPH_TMR17        ((uint32_t)0x00040000)
+#endif
+
+#if !defined (AT32F415xx) && !defined (AT32F421xx)
+#define RCC_APB2PERIPH_TMR8         ((uint32_t)0x00002000)
+#endif
+
+#if !defined (AT32F403xx) && !defined (AT32F421xx)
+#define RCC_APB2PERIPH_ACC          ((uint32_t)0x00400000)
+#endif
+
+#if defined (AT32F415xx) || defined (AT32F421xx)
+#define RCC_APB2PERIPH_EFCB         ((uint32_t)0x00800000)
+#endif
+
+#if defined (AT32F403xx)
+#define IS_RCC_APB2_PERIPH(PERIPH)  ((((PERIPH) & 0xFFC60002) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F413xx)
+#define IS_RCC_APB2_PERIPH(PERIPH)  ((((PERIPH) & 0xFF878142) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F415xx)
+#define IS_RCC_APB2_PERIPH(PERIPH)  ((((PERIPH) & 0xFF078142) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_RCC_APB2_PERIPH(PERIPH)  ((((PERIPH) & 0xF8070182) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F421xx)
+#define IS_RCC_APB2_PERIPH(PERIPH)  ((((PERIPH) & 0xFFF8A5FE) == 0x00) && ((PERIPH) != 0x00))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup APB1_peripheral
+  * @{
+  */
+
+#define RCC_APB1PERIPH_TMR3         ((uint32_t)0x00000002)
+#define RCC_APB1PERIPH_WWDG         ((uint32_t)0x00000800)
+#define RCC_APB1PERIPH_SPI2         ((uint32_t)0x00004000)
+#define RCC_APB1PERIPH_USART2       ((uint32_t)0x00020000)
+#define RCC_APB1PERIPH_I2C1         ((uint32_t)0x00200000)
+#define RCC_APB1PERIPH_I2C2         ((uint32_t)0x00400000)
+#define RCC_APB1PERIPH_PWR          ((uint32_t)0x10000000)
+
+#if !defined (AT32F421xx)
+#define RCC_APB1PERIPH_TMR2         ((uint32_t)0x00000001)
+#define RCC_APB1PERIPH_TMR4         ((uint32_t)0x00000004)
+#define RCC_APB1PERIPH_TMR5         ((uint32_t)0x00000008)
+#define RCC_APB1PERIPH_USART3       ((uint32_t)0x00040000)
+#define RCC_APB1PERIPH_UART4        ((uint32_t)0x00080000)
+#define RCC_APB1PERIPH_UART5        ((uint32_t)0x00100000)
+#define RCC_APB1PERIPH_CAN1         ((uint32_t)0x02000000)
+#endif
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+#define RCC_APB1PERIPH_TMR6         ((uint32_t)0x00000010)
+#define RCC_APB1PERIPH_TMR7         ((uint32_t)0x00000020)
+#define RCC_APB1PERIPH_TMR12        ((uint32_t)0x00000040)
+#define RCC_APB1PERIPH_TMR13        ((uint32_t)0x00000080)
+#define RCC_APB1PERIPH_TMR14        ((uint32_t)0x00000100)
+#define RCC_APB1PERIPH_SPI3         ((uint32_t)0x00008000)
+#define RCC_APB1PERIPH_SPI4         ((uint32_t)0x00010000)
+#define RCC_APB1PERIPH_DAC          ((uint32_t)0x20000000)
+#elif defined (AT32F421xx)
+#define RCC_APB1PERIPH_TMR6         ((uint32_t)0x00000010)
+#define RCC_APB1PERIPH_TMR14        ((uint32_t)0x00000100)
+#endif
+
+#if defined (AT32F403xx)
+#define RCC_APB1PERIPH_I2C3         ((uint32_t)0x04000000)
+#endif
+
+#if defined (AT32F413xx)
+#define RCC_APB1PERIPH_CAN2         ((uint32_t)0x80000000)
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define RCC_APB1PERIPH_CAN2         ((uint32_t)0x04000000)
+#endif
+
+#if !defined (AT32F415xx) && !defined (AT32F421xx)
+#define RCC_APB1PERIPH_USB          ((uint32_t)0x00800000)
+#define RCC_APB1PERIPH_BKP          ((uint32_t)0x08000000)
+#endif
+
+#if defined (AT32F415xx) 
+#define RCC_APB1PERIPH_COMP         ((uint32_t)0x00000200)
+#endif
+
+#if defined (AT32F403xx)
+#define IS_RCC_APB1_PERIPH(PERIPH)  ((((PERIPH) & 0xC1003600) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F413xx)
+#define IS_RCC_APB1_PERIPH(PERIPH)  ((((PERIPH) & 0x6501B7F0) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F415xx)
+#define IS_RCC_APB1_PERIPH(PERIPH)  ((((PERIPH) & 0xED81B5F0) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_RCC_APB1_PERIPH(PERIPH)  ((((PERIPH) & 0xC1003600) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F421xx)
+#define IS_RCC_APB1_PERIPH(PERIPH)  ((((PERIPH) & 0xEF9DB6ED) == 0x00) && ((PERIPH) != 0x00))
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup Clock_source_to_output_on_CLKOUT_pin
+  * @{
+  */
+#define RCC_CLKOUT_NOCLK            ((uint32_t)0x00000000)
+#define RCC_CLKOUT_SYSCLK           ((uint32_t)0x04000000)
+#define RCC_CLKOUT_HSI              ((uint32_t)0x05000000)
+#define RCC_CLKOUT_HSE              ((uint32_t)0x06000000)
+#define RCC_CLKOUT_PLL_Div2         ((uint32_t)0x07000000)
+#define RCC_CLKOUT_PLL_Div4         ((uint32_t)0x14000000)
+#define RCC_CLKOUT_USB              ((uint32_t)0x15000000)
+#define RCC_CLKOUT_ADC              ((uint32_t)0x16000000)
+#if !defined (AT32F403xx)
+#define RCC_CLKOUT_LSI              ((uint32_t)0x02000000)
+#define RCC_CLKOUT_LSE              ((uint32_t)0x03000000)
+#endif
+#if !defined (AT32F403xx)
+#define IS_RCC_CLKOUT(CLK)          (((CLK) == RCC_CLKOUT_NOCLK)    || ((CLK) == RCC_CLKOUT_HSI)      || \
+                                     ((CLK) == RCC_CLKOUT_SYSCLK)   || ((CLK) == RCC_CLKOUT_HSE)      || \
+                                     ((CLK) == RCC_CLKOUT_PLL_Div2) || ((CLK) == RCC_CLKOUT_PLL_Div4) || \
+                                     ((CLK) == RCC_CLKOUT_USB)      || ((CLK) == RCC_CLKOUT_ADC)      || \
+                                     ((CLK) == RCC_CLKOUT_LSI)      || ((CLK) == RCC_CLKOUT_LSE))
+#else
+#define IS_RCC_CLKOUT(CLK)          (((CLK) == RCC_CLKOUT_NOCLK)    || ((CLK) == RCC_CLKOUT_HSI)      || \
+                                     ((CLK) == RCC_CLKOUT_SYSCLK)   || ((CLK) == RCC_CLKOUT_HSE)      || \
+                                     ((CLK) == RCC_CLKOUT_PLL_Div2) || ((CLK) == RCC_CLKOUT_PLL_Div4) || \
+                                     ((CLK) == RCC_CLKOUT_USB)      || ((CLK) == RCC_CLKOUT_ADC))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HSE_Divider
+  * @{
+  */
+#define RCC_HSE_DIV_POS             12
+#define RCC_HSE_DIV_MASK            RCC_MISC2_HSE_DIV_CTRL
+#define RCC_HSE_DIV_2               RCC_MISC2_HSE_DIV_CTRL_2
+#define RCC_HSE_DIV_3               RCC_MISC2_HSE_DIV_CTRL_3
+#define RCC_HSE_DIV_4               RCC_MISC2_HSE_DIV_CTRL_4
+#define RCC_HSE_DIV_5               RCC_MISC2_HSE_DIV_CTRL_5
+
+#define IS_RCC_HSEDIV(CLK)          (((CLK) == RCC_HSE_DIV_2) || ((CLK) == RCC_HSE_DIV_3) || \
+                                     ((CLK) == RCC_HSE_DIV_4) || ((CLK) == RCC_HSE_DIV_5))
+/**
+  * @}
+  */
+
+/** @defgroup RCC miscellaneous register
+  * @{
+  */
+#if !defined (AT32F403xx)
+#define RCC_HSI_DIV_EN              RCC_MISC_HSI_DIV_EN
+#define RCC_AUTO_STEP_EN            RCC_MISC2_AUTO_STEP_EN
+#define RCC_HSI_FOR_USB             RCC_MISC2_HSI_FOR_USB
+#define RCC_HSI_SYS_CTRL            RCC_MISC2_HSI_SYS_CTRL
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup Clock_source_to_output_MCOPRE
+  * @{
+  */
+#define  RCC_MCOPRE_MASK            RCC_MISC_MCOPRE_MASK
+#define  RCC_MCOPRE_1               RCC_MISC_MCOPRE_1
+#define  RCC_MCOPRE_2               RCC_MISC_MCOPRE_2
+#define  RCC_MCOPRE_4               RCC_MISC_MCOPRE_4
+#define  RCC_MCOPRE_8               RCC_MISC_MCOPRE_8
+#define  RCC_MCOPRE_16              RCC_MISC_MCOPRE_16
+#define  RCC_MCOPRE_64              RCC_MISC_MCOPRE_64
+#define  RCC_MCOPRE_128             RCC_MISC_MCOPRE_128
+#define  RCC_MCOPRE_256             RCC_MISC_MCOPRE_256
+#define  RCC_MCOPRE_512             RCC_MISC_MCOPRE_512
+
+#if !defined (AT32F403xx)
+#define IS_RCC_MCO(MCOPRE)          (((MCOPRE) == RCC_MCOPRE_1)    || ((MCOPRE) == RCC_MCOPRE_2)      || \
+                                     ((MCOPRE) == RCC_MCOPRE_4)    || ((MCOPRE) == RCC_MCOPRE_8)      || \
+                                     ((MCOPRE) == RCC_MCOPRE_16)   || ((MCOPRE) == RCC_MCOPRE_64)     || \
+                                     ((MCOPRE) == RCC_MCOPRE_128)  || ((MCOPRE) == RCC_MCOPRE_256)    || \
+                                     ((MCOPRE) == RCC_MCOPRE_512))
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag
+  * @{
+  */
+
+#define RCC_FLAG_HSISTBL            ((uint8_t)0x21)
+#define RCC_FLAG_HSESTBL            ((uint8_t)0x31)
+#define RCC_FLAG_PLLSTBL            ((uint8_t)0x39)
+#define RCC_FLAG_LSESTBL            ((uint8_t)0x41)
+#define RCC_FLAG_LSISTBL            ((uint8_t)0x61)
+#define RCC_FLAG_PINRST             ((uint8_t)0x7A)
+#define RCC_FLAG_PORST              ((uint8_t)0x7B)
+#define RCC_FLAG_SWRST              ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST            ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST            ((uint8_t)0x7E)
+#define RCC_FLAG_LPRST              ((uint8_t)0x7F)
+
+#define IS_RCC_FLAG(FLAG)           (((FLAG) == RCC_FLAG_HSISTBL) || ((FLAG) == RCC_FLAG_HSESTBL) || \
+                                     ((FLAG) == RCC_FLAG_PLLSTBL) || ((FLAG) == RCC_FLAG_LSESTBL) || \
+                                     ((FLAG) == RCC_FLAG_LSISTBL) || ((FLAG) == RCC_FLAG_PINRST)  || \
+                                     ((FLAG) == RCC_FLAG_PORST)   || ((FLAG) == RCC_FLAG_SWRST)   || \
+                                     ((FLAG) == RCC_FLAG_IWDGRST) || ((FLAG) == RCC_FLAG_WWDGRST) || \
+                                     ((FLAG) == RCC_FLAG_LPRST))
+#if defined (AT32F403xx)
+#define IS_RCC_TWEAK_VALUE(VALUE)    ((VALUE) <= 0x1F)
+#else
+#define IS_RCC_TWEAK_VALUE(VALUE)    ((VALUE) <= 0x3F)
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#if defined (AT32F415xx) || defined (AT32F421xx)
+/** @defgroup RCC_PLL_Register
+  * @{
+  */
+#define PLL_FR_POS                   0
+#define PLL_FR_MASK                  ((uint32_t)0x00000007)
+#define PLL_FR_1                     ((uint32_t)0x00000000)
+#define PLL_FR_2                     ((uint32_t)0x00000001)
+#define PLL_FR_4                     ((uint32_t)0x00000002)
+#define PLL_FR_8                     ((uint32_t)0x00000003)
+#define PLL_FR_16                    ((uint32_t)0x00000004)
+#define PLL_FR_32                    ((uint32_t)0x00000005)
+
+#define PLL_MS_POS                   4
+#define PLL_MS_MASK                  ((uint32_t)0x000000F0)
+
+#define PLL_NS_POS                   8
+#define PLL_NS_MASK                  ((uint32_t)0x0001FF00)
+
+#define PLL_FREF_POS                 24
+#define PLL_FREF_MASK                ((uint32_t)0x07000000)
+#define PLL_FREF_4M                  ((uint32_t)0x00000000)
+#define PLL_FREF_6M                  ((uint32_t)0x01000000)
+#define PLL_FREF_8M                  ((uint32_t)0x02000000)
+#define PLL_FREF_12M                 ((uint32_t)0x03000000)
+#define PLL_FREF_16M                 ((uint32_t)0x04000000)
+#define PLL_FREF_25M                 ((uint32_t)0x05000000)
+
+#define PLL_CFGGEN_POS               31
+#define PLL_CFGEN_ENABLE             ((uint32_t)0x80000000)
+#define PLL_CFGEN_MASK               ((uint32_t)0x80000000)
+
+#define IS_RCC_FR(PLL_FR)            (((PLL_FR) == PLL_FR_1)    || ((PLL_FR) == PLL_FR_2)      || \
+                                      ((PLL_FR) == PLL_FR_4)    || ((PLL_FR) == PLL_FR_8)      || \
+                                      ((PLL_FR) == PLL_FR_16)   || ((PLL_FR) == PLL_FR_32))
+
+#define IS_RCC_MS_VALUE(VALUE)       (((VALUE) >= 0x1) && ((VALUE) <= 0xF))
+#define IS_RCC_NS_VALUE(VALUE)       (((VALUE) >= 0x1F) && ((VALUE) <= 0x1F4))
+#define IS_RCC_RESULT_VALUE(VALUE)   (((VALUE) >= 0x1F4) && ((VALUE) <= 0x3E8))
+
+#define RCC_FR_VALUE(VALUE, RET)     do                         \
+                                     {                          \
+                                       switch (VALUE)           \
+                                       {                        \
+                                         case PLL_FR_1:         \
+                                         RET = 1;               \
+                                         break;                 \
+                                         case PLL_FR_2:         \
+                                         RET = 2;               \
+                                         break;                 \
+                                         case PLL_FR_4:         \
+                                         RET = 4;               \
+                                         break;                 \
+                                         case PLL_FR_8:         \
+                                         RET = 8;               \
+                                         break;                 \
+                                         case PLL_FR_16:        \
+                                         RET = 16;              \
+                                         break;                 \
+                                         case PLL_FR_32:        \
+                                         RET = 32;              \
+                                         break;                 \
+                                         default:               \
+                                         RET = 1;               \
+                                         break;                 \
+                                       }                        \
+                                     }while(0)
+/**
+  * @}
+  */
+#endif
+
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Functions
+  * @{
+  */
+uint8_t RCC_GetSYSCLKSelction(void);
+void RCC_AHBCLKConfig(uint32_t RCC_SYSCLK_Div);
+void RCC_APB1CLKConfig(uint32_t RCC_HCLK_Div);
+void RCC_APB2CLKConfig(uint32_t RCC_HCLK_Div);
+void RCC_INTConfig(uint8_t RCC_INT, FunctionalState NewState);
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2_Div);
+void RCC_Reset(void);
+void RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStable(void);
+void RCC_SetHSITweakValue(uint8_t HSITweakValue);
+void RCC_SetHSICalibValue(uint8_t HSICalibValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLRefClk, uint32_t RCC_PLLMult, uint32_t RCC_PLLRange);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSelect);
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+#if defined (AT32F415xx) || defined (AT32F421xx)
+void RCC_ERTCCLKConfig(uint32_t RCC_ERTCCLKSelect);
+void RCC_ERTCCLKCmd(FunctionalState NewState);
+#else
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSelect);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+#endif
+void RCC_GetClocksFreq(RCC_ClockType* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+#if defined (AT32F403Axx) || defined (AT32F407xx) || \
+    defined (AT32F421xx)
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+#endif
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_HSEClockFailureDetectorCmd(FunctionalState NewState);
+#if defined (AT32F403xx)
+void RCC_CLKOUTConfig(uint32_t RCC_CLKOUT);
+#else
+void RCC_CLKOUTConfig(uint32_t RCC_CLKOUT, uint32_t RCC_CLKOUTPRE);
+#endif
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_Flag);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetINTStatus(uint8_t RCC_INT);
+void RCC_ClearINTPendingBit(uint8_t RCC_INT);
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSelect);
+void RCC_StepModeCmd(FunctionalState NewState);
+void RCC_USBINTRemap(FunctionalState NewState);
+void RCC_HSI2SYS48M(FunctionalState NewState);
+void RCC_HSI2USB48M(FunctionalState NewState);
+void RCC_MCO2TMR10(FunctionalState NewState);
+#if defined (AT32F415xx) || defined (AT32F421xx)
+void RCC_PLLFrefTableConfig(uint32_t hse_value);
+void RCC_PLLconfig2(uint32_t PLL_NS, uint32_t PLL_MS, \
+                    uint32_t PLL_FR);
+#endif
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+void RCC_HSEDivConfig(uint32_t HSEDiv);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_RCC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_rtc.h

@@ -0,0 +1,124 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_rtc.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx RTC header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_RTC_H
+#define __AT32F4XX_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */
+
+/** @defgroup RTC_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup RTC_interrupts_define
+  * @{
+  */
+
+#define RTC_INT_OV                          ((uint16_t)0x0004)  /*!< Overflow interrupt */
+#define RTC_INT_ALA                         ((uint16_t)0x0002)  /*!< Alarm interrupt */
+#define RTC_INT_PACE                        ((uint16_t)0x0001)  /*!< Second interrupt */
+#define IS_RTC_INT(INT)                     ((((INT) & (uint16_t)0xFFF8) == 0x00) && ((INT) != 0x00))
+#define IS_RTC_GET_INT(INT)                 (((INT) == RTC_INT_OV) || ((INT) == RTC_INT_ALA) || \
+                                             ((INT) == RTC_INT_PACE))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_interrupts_flags
+  * @{
+  */
+
+#define RTC_FLAG_RTF                        ((uint16_t)0x0020)  /*!< RTC Operation OFF flag */
+#define RTC_FLAG_RSYNF                      ((uint16_t)0x0008)  /*!< Registers Synchronized flag */
+#define RTC_FLAG_OV                         ((uint16_t)0x0004)  /*!< Overflow flag */
+#define RTC_FLAG_ALA                        ((uint16_t)0x0002)  /*!< Alarm flag */
+#define RTC_FLAG_PACE                       ((uint16_t)0x0001)  /*!< Second flag */
+#define IS_RTC_CLEAR_FLAG(FLAG)             ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
+#define IS_RTC_GET_FLAG(FLAG)               (((FLAG) == RTC_FLAG_RTF) || ((FLAG) == RTC_FLAG_RSYNF) || \
+                                             ((FLAG) == RTC_FLAG_OV)  || ((FLAG) == RTC_FLAG_ALA)   || \
+                                             ((FLAG) == RTC_FLAG_PACE))
+#define IS_RTC_DIV(DIV)                      ((DIV) <= 0xFFFFF)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Functions
+  * @{
+  */
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus RTC_GetINTStatus(uint16_t RTC_INT);
+uint32_t  RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+void RTC_ClearINTPendingBit(uint16_t RTC_INT);
+void RTC_SetCounter(uint32_t CounterValue);
+void RTC_SetDIV(uint32_t PrescalerValue);
+void RTC_SetAlarmValue(uint32_t AlarmValue);
+void RTC_INTConfig(uint16_t RTC_INT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+uint32_t  RTC_GetCounter(void);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_RTC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_sdio.h

@@ -0,0 +1,526 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_sdio.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx SDIO header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_SDIO_H
+#define __AT32F4XX_SDIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SDIO
+  * @{
+  */
+
+/** @defgroup SDIO_Exported_Types
+  * @{
+  */
+
+typedef struct
+{
+    uint32_t SDIO_ClkEdge;                  /*!< Specifies the clock transition on which the bit capture is made.
+                                                 This parameter can be a value of @ref SDIO_Clock_Edge */
+                                            
+    uint32_t SDIO_ClkBypass;                /*!< Specifies whether the SDIO Clock divider bypass is
+                                                 enabled or disabled.
+                                                 This parameter can be a value of @ref SDIO_Clock_Bypass */
+                                            
+    uint32_t SDIO_ClkPowerSave;             /*!< Specifies whether SDIO Clock output is enabled or
+                                                 disabled when the bus is idle.
+                                                 This parameter can be a value of @ref SDIO_Clock_Power_Save */
+                                            
+    uint32_t SDIO_BusWidth;                 /*!< Specifies the SDIO bus width.
+                                                 This parameter can be a value of @ref SDIO_Bus_Wide */
+                                            
+    uint32_t SDIO_FlowCtrl;                 /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+                                                 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+                                            
+    uint16_t SDIO_ClkPsc;                    /*!< Specifies the clock frequency of the SDIO controller.
+                                                 This parameter can be a value between 0x00 and 0x3FF. */
+
+} SDIO_InitType;
+
+typedef struct
+{
+    uint32_t SDIO_Argu;                     /*!< Specifies the SDIO command argument which is sent
+                                                 to a card as part of a command message. If a command
+                                                 contains an argument, it must be loaded into this register
+                                                 before writing the command to the command register */
+                                            
+    uint32_t SDIO_CmdIdx;                   /*!< Specifies the SDIO command index. It must be lower than 0x40. */
+                                            
+    uint32_t SDIO_Resp;                     /*!< Specifies the SDIO response type.
+                                                 This parameter can be a value of @ref SDIO_Response_Type */
+                                            
+    uint32_t SDIO_Wait;                     /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+                                                 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+                                            
+    uint32_t SDIO_CPSM;                     /*!< Specifies whether SDIO Command path state machine (CPSM)
+                                                 is enabled or disabled.
+                                                 This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitType;
+
+typedef struct
+{
+    uint32_t SDIO_DataTimeOut;              /*!< Specifies the data timeout period in card bus clock periods. */
+                                            
+    uint32_t SDIO_DataLen;                  /*!< Specifies the number of data bytes to be transferred. */
+                                            
+    uint32_t SDIO_DataBlkSize;              /*!< Specifies the data block size for block transfer.
+                                               This parameter can be a value of @ref SDIO_Data_Block_Size */
+                                            
+    uint32_t SDIO_TransferDir;              /*!< Specifies the data transfer direction, whether the transfer
+                                               is a read or write.
+                                               This parameter can be a value of @ref SDIO_Transfer_Direction */
+                                            
+    uint32_t SDIO_TransferMode;             /*!< Specifies whether data transfer is in stream or block mode.
+                                               This parameter can be a value of @ref SDIO_Transfer_Type */
+                                            
+    uint32_t SDIO_DPSM;                     /*!< Specifies whether SDIO Data path state machine (DPSM)
+                                               is enabled or disabled.
+                                               This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constants
+  * @{
+  */
+
+#if defined (AT32F413xx) || defined (AT32F415xx)
+#define IS_SDIO_ALL_PERIPH(PERIPH)          ((PERIPH) == SDIO)
+#elif defined (AT32F403xx) || defined (AT32F403Axx) || \
+      defined (AT32F407xx)
+#define IS_SDIO_ALL_PERIPH(PERIPH)          (((PERIPH) == SDIO1) || \
+                                             ((PERIPH) == SDIO2))
+#endif
+/** @defgroup SDIO_Clock_Edge
+  * @{
+  */
+
+#define SDIO_ClkEdge_Rising                 ((uint32_t)0x00000000)
+#define SDIO_ClkEdge_Falling                ((uint32_t)0x00002000)
+#define IS_SDIO_CLK_EDGE(EDGE)              (((EDGE) == SDIO_ClkEdge_Rising) || \
+                                             ((EDGE) == SDIO_ClkEdge_Falling))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Clock_Bypass
+  * @{
+  */
+
+#define SDIO_ClkBypass_Disable              ((uint32_t)0x00000000)
+#define SDIO_ClkBypass_Enable               ((uint32_t)0x00000400)
+#define IS_SDIO_CLK_BYPASS(BYPASS)          (((BYPASS) == SDIO_ClkBypass_Disable) || \
+                                             ((BYPASS) == SDIO_ClkBypass_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Clock_Power_Save
+  * @{
+  */
+
+#define SDIO_ClkPowerSave_Disable           ((uint32_t)0x00000000)
+#define SDIO_ClkPowerSave_Enable            ((uint32_t)0x00000200)
+#define IS_SDIO_CLK_POWER_SAVE(SAVE)        (((SAVE) == SDIO_ClkPowerSave_Disable) || \
+                                             ((SAVE) == SDIO_ClkPowerSave_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Bus_Wide
+  * @{
+  */
+
+#define SDIO_BusWidth_1b                    ((uint32_t)0x00000000)
+#define SDIO_BusWidth_4b                    ((uint32_t)0x00000800)
+#define SDIO_BusWidth_8b                    ((uint32_t)0x00001000)
+#define IS_SDIO_BUS_WIDTH(WIDTH)            (((WIDTH) == SDIO_BusWidth_1b) || ((WIDTH) == SDIO_BusWidth_4b) || \
+                                             ((WIDTH) == SDIO_BusWidth_8b))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Hardware_Flow_Control
+  * @{
+  */
+
+#define SDIO_FlowCtrl_Disable               ((uint32_t)0x00000000)
+#define SDIO_FlowCtrl_Enable                ((uint32_t)0x00004000)
+#define IS_SDIO_FLOW_CTRL(CTRL)             (((CTRL) == SDIO_FlowCtrl_Disable) || \
+                                             ((CTRL) == SDIO_FlowCtrl_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Power_State
+  * @{
+  */
+
+#define SDIO_PowerSave_OFF                  ((uint32_t)0x00000000)
+#define SDIO_PowerSave_ON                   ((uint32_t)0x00000003)
+#define IS_SDIO_POWER_SAVE(SAVE)            (((SAVE) == SDIO_PowerSave_OFF) || ((SAVE) == SDIO_PowerSave_ON))
+/**
+  * @}
+  */
+
+
+/** @defgroup SDIO_Interrupt_sources
+  * @{
+  */
+
+#define SDIO_INT_CMDFAIL                    ((uint32_t)0x00000001)
+#define SDIO_INT_DTFAIL                     ((uint32_t)0x00000002)
+#define SDIO_INT_CMDTIMEOUT                 ((uint32_t)0x00000004)
+#define SDIO_INT_DTTIMEOUT                  ((uint32_t)0x00000008)
+#define SDIO_INT_TXERRU                     ((uint32_t)0x00000010)
+#define SDIO_INT_RXERRO                     ((uint32_t)0x00000020)
+#define SDIO_INT_CMDRSPCMPL                 ((uint32_t)0x00000040)
+#define SDIO_INT_CMDCMPL                    ((uint32_t)0x00000080)
+#define SDIO_INT_DTCMPL                     ((uint32_t)0x00000100)
+#define SDIO_INT_SBITERR                    ((uint32_t)0x00000200)
+#define SDIO_INT_DTBLKCMPL                  ((uint32_t)0x00000400)
+#define SDIO_INT_DOCMD                      ((uint32_t)0x00000800)
+#define SDIO_INT_DOTX                       ((uint32_t)0x00001000)
+#define SDIO_INT_DORX                       ((uint32_t)0x00002000)
+#define SDIO_INT_TXBUF_H                    ((uint32_t)0x00004000)
+#define SDIO_INT_RXBUF_H                    ((uint32_t)0x00008000)
+#define SDIO_INT_TXBUF_F                    ((uint32_t)0x00010000)
+#define SDIO_INT_RXBUF_F                    ((uint32_t)0x00020000)
+#define SDIO_INT_TXBUF_E                    ((uint32_t)0x00040000)
+#define SDIO_INT_RXBUF_E                    ((uint32_t)0x00080000)
+#define SDIO_INT_TXBUF                      ((uint32_t)0x00100000)
+#define SDIO_INT_RXBUF                      ((uint32_t)0x00200000)
+#define SDIO_INT_SDIOIF                     ((uint32_t)0x00400000)
+#define SDIO_INT_ATACMPL                    ((uint32_t)0x00800000)
+#define IS_SDIO_INT(INT)                    ((((INT) & (uint32_t)0xFF000000) == 0x00) && ((INT) != (uint32_t)0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Command_Index
+  * @{
+  */
+
+#define IS_SDIO_CMD_IDX(IDX)                ((IDX) < 0x40)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Response_Type
+  * @{
+  */
+
+#define SDIO_Rsp_No                         ((uint32_t)0x00000000)
+#define SDIO_Rsp_Short                      ((uint32_t)0x00000040)
+#define SDIO_Rsp_Long                       ((uint32_t)0x000000C0)
+#define IS_SDIO_RSP_TYPE(TYPE)              (((TYPE) == SDIO_Rsp_No) || \
+                                             ((TYPE) == SDIO_Rsp_Short) || \
+                                             ((TYPE) == SDIO_Rsp_Long))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Wait_Interrupt_State
+  * @{
+  */
+
+#define SDIO_Wait_No                        ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_INT                       ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
+#define IS_SDIO_WAIT(WAIT)                  (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_INT) || \
+                                             ((WAIT) == SDIO_Wait_Pend))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_CPSM_State
+  * @{
+  */
+
+#define SDIO_CPSM_Disable                   ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable                    ((uint32_t)0x00000400)
+#define IS_SDIO_CPSM(CPSM)                  (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Response_Registers
+  * @{
+  */
+
+#define SDIO_RSP1                           ((uint32_t)0x00000000)
+#define SDIO_RSP2                           ((uint32_t)0x00000004)
+#define SDIO_RSP3                           ((uint32_t)0x00000008)
+#define SDIO_RSP4                           ((uint32_t)0x0000000C)
+#define IS_SDIO_RSP(RSP)                    (((RSP) == SDIO_RSP1) || ((RSP) == SDIO_RSP2) || \
+                                             ((RSP) == SDIO_RSP3) || ((RSP) == SDIO_RSP4))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Length
+  * @{
+  */
+
+#define IS_SDIO_DATA_LEN(LEN)               ((LEN) <= 0x01FFFFFF)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Block_Size
+  * @{
+  */
+
+#define SDIO_DataBlkSize_1b                 ((uint32_t)0x00000000)
+#define SDIO_DataBlkSize_2b                 ((uint32_t)0x00000010)
+#define SDIO_DataBlkSize_4b                 ((uint32_t)0x00000020)
+#define SDIO_DataBlkSize_8b                 ((uint32_t)0x00000030)
+#define SDIO_DataBlkSize_16b                ((uint32_t)0x00000040)
+#define SDIO_DataBlkSize_32b                ((uint32_t)0x00000050)
+#define SDIO_DataBlkSize_64b                ((uint32_t)0x00000060)
+#define SDIO_DataBlkSize_128b               ((uint32_t)0x00000070)
+#define SDIO_DataBlkSize_256b               ((uint32_t)0x00000080)
+#define SDIO_DataBlkSize_512b               ((uint32_t)0x00000090)
+#define SDIO_DataBlkSize_1024b              ((uint32_t)0x000000A0)
+#define SDIO_DataBlkSize_2048b              ((uint32_t)0x000000B0)
+#define SDIO_DataBlkSize_4096b              ((uint32_t)0x000000C0)
+#define SDIO_DataBlkSize_8192b              ((uint32_t)0x000000D0)
+#define SDIO_DataBlkSize_16384b             ((uint32_t)0x000000E0)
+#define IS_SDIO_BLK_SIZE(SIZE)              (((SIZE) == SDIO_DataBlkSize_1b)    || \
+                                             ((SIZE) == SDIO_DataBlkSize_2b)    || \
+                                             ((SIZE) == SDIO_DataBlkSize_4b)    || \
+                                             ((SIZE) == SDIO_DataBlkSize_8b)    || \
+                                             ((SIZE) == SDIO_DataBlkSize_16b)   || \
+                                             ((SIZE) == SDIO_DataBlkSize_32b)   || \
+                                             ((SIZE) == SDIO_DataBlkSize_64b)   || \
+                                             ((SIZE) == SDIO_DataBlkSize_128b)  || \
+                                             ((SIZE) == SDIO_DataBlkSize_256b)  || \
+                                             ((SIZE) == SDIO_DataBlkSize_512b)  || \
+                                             ((SIZE) == SDIO_DataBlkSize_1024b) || \
+                                             ((SIZE) == SDIO_DataBlkSize_2048b) || \
+                                             ((SIZE) == SDIO_DataBlkSize_4096b) || \
+                                             ((SIZE) == SDIO_DataBlkSize_8192b) || \
+                                             ((SIZE) == SDIO_DataBlkSize_16384b))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Direction
+  * @{
+  */
+
+#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
+#define IS_SDIO_TRANSFER_DIR(DIR)           (((DIR) == SDIO_TransferDir_ToCard) || \
+                                             ((DIR) == SDIO_TransferDir_ToSDIO))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Type
+  * @{
+  */
+
+#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
+#define IS_SDIO_TRANSFER_MODE(MODE)         (((MODE) == SDIO_TransferMode_Stream) || \
+                                             ((MODE) == SDIO_TransferMode_Block))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_DPSM_State
+  * @{
+  */
+
+#define SDIO_DPSM_Disable                   ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable                    ((uint32_t)0x00000001)
+#define IS_SDIO_DPSM(DPSM)                  (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Flags
+  * @{
+  */
+
+#define SDIO_FLG_CMDFAIL                    ((uint32_t)0x00000001)
+#define SDIO_FLG_DTFAIL                     ((uint32_t)0x00000002)
+#define SDIO_FLG_CMDTIMEOUT                 ((uint32_t)0x00000004)
+#define SDIO_FLG_DTTIMEOUT                  ((uint32_t)0x00000008)
+#define SDIO_FLG_TXERRU                     ((uint32_t)0x00000010)
+#define SDIO_FLG_RXERRO                     ((uint32_t)0x00000020)
+#define SDIO_FLG_CMDRSPCMPL                 ((uint32_t)0x00000040)
+#define SDIO_FLG_CMDCMPL                    ((uint32_t)0x00000080)
+#define SDIO_FLG_DTCMPL                     ((uint32_t)0x00000100)
+#define SDIO_FLG_SBITERR                    ((uint32_t)0x00000200)
+#define SDIO_FLG_DTBLKCMPL                  ((uint32_t)0x00000400)
+#define SDIO_FLG_DOCMD                      ((uint32_t)0x00000800)
+#define SDIO_FLG_DOTX                       ((uint32_t)0x00001000)
+#define SDIO_FLG_DORX                       ((uint32_t)0x00002000)
+#define SDIO_FLG_TXBUF_H                    ((uint32_t)0x00004000)
+#define SDIO_FLG_RXBUF_H                    ((uint32_t)0x00008000)
+#define SDIO_FLG_TXBUF_F                    ((uint32_t)0x00010000)
+#define SDIO_FLG_RXBUF_F                    ((uint32_t)0x00020000)
+#define SDIO_FLG_TXBUF_E                    ((uint32_t)0x00040000)
+#define SDIO_FLG_RXBUF_E                    ((uint32_t)0x00080000)
+#define SDIO_FLG_TXBUF                      ((uint32_t)0x00100000)
+#define SDIO_FLG_RXBUF                      ((uint32_t)0x00200000)
+#define SDIO_FLG_SDIOIF                     ((uint32_t)0x00400000)
+#define SDIO_FLG_ATACMPL                    ((uint32_t)0x00800000)
+#define IS_SDIO_FLG(FLG)                    (((FLG)  == SDIO_FLG_CMDFAIL)    || \
+                                             ((FLG)  == SDIO_FLG_DTFAIL)     || \
+                                             ((FLG)  == SDIO_FLG_CMDTIMEOUT) || \
+                                             ((FLG)  == SDIO_FLG_DTTIMEOUT)  || \
+                                             ((FLG)  == SDIO_FLG_TXERRU)     || \
+                                             ((FLG)  == SDIO_FLG_RXERRO)     || \
+                                             ((FLG)  == SDIO_FLG_CMDRSPCMPL) || \
+                                             ((FLG)  == SDIO_FLG_CMDCMPL)    || \
+                                             ((FLG)  == SDIO_FLG_DTCMPL)     || \
+                                             ((FLG)  == SDIO_FLG_SBITERR)    || \
+                                             ((FLG)  == SDIO_FLG_DTBLKCMPL)  || \
+                                             ((FLG)  == SDIO_FLG_DOCMD)      || \
+                                             ((FLG)  == SDIO_FLG_DOTX)       || \
+                                             ((FLG)  == SDIO_FLG_DORX)       || \
+                                             ((FLG)  == SDIO_FLG_TXBUF_H)    || \
+                                             ((FLG)  == SDIO_FLG_RXBUF_H)    || \
+                                             ((FLG)  == SDIO_FLG_TXBUF_F)    || \
+                                             ((FLG)  == SDIO_FLG_RXBUF_F)    || \
+                                             ((FLG)  == SDIO_FLG_TXBUF_E)    || \
+                                             ((FLG)  == SDIO_FLG_RXBUF_E)    || \
+                                             ((FLG)  == SDIO_FLG_TXBUF)      || \
+                                             ((FLG)  == SDIO_FLG_RXBUF)      || \
+                                             ((FLG)  == SDIO_FLG_SDIOIF)     || \
+                                             ((FLG)  == SDIO_FLG_ATACMPL))
+
+#define IS_SDIO_CLEAR_FLG(FLG)              ((((FLG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_INT(INT)                (((INT)  == SDIO_INT_CMDFAIL)    || \
+                                             ((INT)  == SDIO_INT_DTFAIL)     || \
+                                             ((INT)  == SDIO_INT_CMDTIMEOUT) || \
+                                             ((INT)  == SDIO_INT_DTTIMEOUT)  || \
+                                             ((INT)  == SDIO_INT_TXERRU)     || \
+                                             ((INT)  == SDIO_INT_RXERRO)     || \
+                                             ((INT)  == SDIO_INT_CMDRSPCMPL) || \
+                                             ((INT)  == SDIO_INT_CMDCMPL)    || \
+                                             ((INT)  == SDIO_INT_DTCMPL)     || \
+                                             ((INT)  == SDIO_INT_SBITERR)    || \
+                                             ((INT)  == SDIO_INT_DTBLKCMPL)  || \
+                                             ((INT)  == SDIO_INT_DOCMD)      || \
+                                             ((INT)  == SDIO_INT_DOTX)       || \
+                                             ((INT)  == SDIO_INT_DORX)       || \
+                                             ((INT)  == SDIO_INT_TXBUF_H)    || \
+                                             ((INT)  == SDIO_INT_RXBUF_H)    || \
+                                             ((INT)  == SDIO_INT_TXBUF_F)    || \
+                                             ((INT)  == SDIO_INT_RXBUF_F)    || \
+                                             ((INT)  == SDIO_INT_TXBUF_E)    || \
+                                             ((INT)  == SDIO_INT_RXBUF_E)    || \
+                                             ((INT)  == SDIO_INT_TXBUF)      || \
+                                             ((INT)  == SDIO_INT_RXBUF)      || \
+                                             ((INT)  == SDIO_INT_SDIOIF)     || \
+                                             ((INT)  == SDIO_INT_ATACMPL))
+
+#define IS_SDIO_CLEAR_INT(INT)              ((((INT) & (uint32_t)0xFF3FF800) == 0x00) && ((INT) != (uint32_t)0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Read_Wait_Mode
+  * @{
+  */
+
+#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000001)
+#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000000)
+#define IS_SDIO_READWAIT_MODE(MODE)         (((MODE) == SDIO_ReadWaitMode_CLK) || \
+                                             ((MODE) == SDIO_ReadWaitMode_DATA2))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions
+  * @{
+  */
+void SDIO_CommandCompletionCmd(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_ATAINTCmd(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_SendATACmd(SDIO_Type * SDIOx, FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(SDIO_Type * SDIOx, uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(SDIO_Type * SDIOx, uint32_t SDIO_FLAG);
+ITStatus SDIO_GetINTStatus(SDIO_Type * SDIOx, uint32_t SDIO_INT);
+void SDIO_ClearINTPendingBit(SDIO_Type * SDIOx, uint32_t SDIO_INT);
+void SDIO_Reset(SDIO_Type * SDIOx);
+void SDIO_SendCommand(SDIO_Type * SDIOx, SDIO_CmdInitType *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitType* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(SDIO_Type * SDIOx);
+uint32_t SDIO_GetResponse(SDIO_Type * SDIOx, uint32_t SDIO_RESP);
+void SDIO_DataConfig(SDIO_Type * SDIOx, SDIO_DataInitType* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitType* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(SDIO_Type * SDIOx);
+uint32_t SDIO_ReadData(SDIO_Type * SDIOx);
+void SDIO_WriteData(SDIO_Type * SDIOx, uint32_t Data);
+uint32_t SDIO_GetBUFCount(SDIO_Type * SDIOx);
+void SDIO_Init(SDIO_Type * SDIOx, SDIO_InitType* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitType* SDIO_InitStruct);
+void SDIO_ClockCmd(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_SetPowerSaveState(SDIO_Type * SDIOx, uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerSaveState(SDIO_Type * SDIOx);
+void SDIO_INTConfig(SDIO_Type * SDIOx, uint32_t SDIO_INT, FunctionalState NewState);
+void SDIO_DMACmd(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_StartSDIOReadWait(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_StopSDIOReadWait(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(SDIO_Type * SDIOx, uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(SDIO_Type * SDIOx, FunctionalState NewState);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_SDIO_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_spi.h

@@ -0,0 +1,514 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_spi.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx SPI header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_SPI_H
+#define __AT32F4XX_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */
+
+/** @defgroup SPI_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  SPI Init structure definition
+  */
+
+typedef struct
+{
+    uint16_t SPI_TransMode;                 /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                               This parameter can be a value of @ref SPI_data_direction */
+                                            
+    uint16_t SPI_Mode;                      /*!< Specifies the SPI operating mode.
+                                               This parameter can be a value of @ref SPI_mode */
+                                            
+    uint16_t SPI_FrameSize;                 /*!< Specifies the SPI data size.
+                                               This parameter can be a value of @ref SPI_data_size */
+                                            
+    uint16_t SPI_CPOL;                      /*!< Specifies the serial clock steady state.
+                                               This parameter can be a value of @ref SPI_Clock_Polarity */
+                                            
+    uint16_t SPI_CPHA;                      /*!< Specifies the clock active edge for the bit capture.
+                                               This parameter can be a value of @ref SPI_Clock_Phase */
+                                            
+    uint16_t SPI_NSSSEL;                    /*!< Specifies whether the NSSSEL signal is managed by
+                                               hardware (NSSSEL pin) or by software using the SSI bit.
+                                               This parameter can be a value of @ref SPI_Slave_Select_management */
+                                            
+    uint16_t SPI_MCLKP;                     /*!< Specifies the Baud Rate prescaler value which will be
+                                                used to configure the transmit and receive SCK clock.
+                                                This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+                                                @note The communication clock is derived from the master
+                                                      clock. The slave clock does not need to be set. */
+                                            
+    uint16_t SPI_FirstBit;                  /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                                This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+                                    
+    uint16_t SPI_CPOLY;                     /*!<  Specifies the polynomial used for the CRC calculation. */
+} SPI_InitType;                     
+                                    
+/**                                 
+  * @brief  I2S Init structure defi nition
+  */                                
+                                    
+typedef struct                      
+{                                   
+                                    
+    uint16_t I2S_Mode;                      /*!<  Specifies the I2S operating mode.
+                                               This parameter can be a value of @ref I2S_Mode */
+                                    
+    uint16_t I2s_AudioProtocol;             /*!< Specifies the standard used for the I2S communication.
+                                                This parameter can be a value of @ref I2s_AudioProtocol */
+                                    
+    uint16_t I2S_FrameFormat;               /*! < Specifies the data format for the I2S communication.
+                                              This parameter can be a value of @ref I2S_Data_Format */
+
+    uint16_t I2S_MCLKOE;                    /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                                   This parameter can be a value of @ref I2S_MCLK_Output */
+
+    uint32_t I2S_AudioFreq;                 /*!< Specifies the frequency selected for the I2S communication.
+                                               This parameter can be a value of @ref I2S_Audio_Frequency */
+                                            
+    uint16_t I2S_CPOL;                      /*!< Specifies the idle state of the I2S clock.
+                                               This parameter can be a value of @ref I2S_Clock_Polarity */
+} I2S_InitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Constants
+  * @{
+  */
+
+#if defined (AT32F413xx) || defined (AT32F415xx)
+#define IS_SPI_ALL_PERIPH(PERIPH)           (((PERIPH) == SPI1) || \
+                                             ((PERIPH) == SPI2))
+#elif defined (AT32F403xx)
+#define IS_SPI_ALL_PERIPH(PERIPH)           (((PERIPH) == SPI1) || \
+                                             ((PERIPH) == SPI2) || \
+                                             ((PERIPH) == SPI3) || \
+                                             ((PERIPH) == SPI4))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_SPI_ALL_PERIPH(PERIPH)           (((PERIPH) == SPI1)    || \
+                                             ((PERIPH) == SPI2)    || \
+                                             ((PERIPH) == SPI3)    || \
+                                             ((PERIPH) == SPI4)    || \
+                                             ((PERIPH) == I2S2EXT) || \
+                                             ((PERIPH) == I2S3EXT))
+#elif defined (AT32F421xx)
+#define IS_SPI_ALL_PERIPH(PERIPH)           (((PERIPH) == SPI1)    || \
+                                             ((PERIPH) == SPI2))
+#endif
+
+#if defined (AT32F413xx) || defined (AT32F415xx) || defined (AT32F421xx)
+#define IS_SPI_I2S_PERIPH(PERIPH)           (((PERIPH) == SPI1) || \
+                                             ((PERIPH) == SPI2))
+#elif defined (AT32F403xx)
+#define IS_SPI_I2S_PERIPH(PERIPH)           (((PERIPH) == SPI1) || \
+                                             ((PERIPH) == SPI2) || \
+                                             ((PERIPH) == SPI3) || \
+                                             ((PERIPH) == SPI4))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_SPI_I2S_PERIPH(PERIPH)           (((PERIPH) == SPI1)    || \
+                                             ((PERIPH) == SPI2)    || \
+                                             ((PERIPH) == SPI3)    || \
+                                             ((PERIPH) == SPI4)    || \
+                                             ((PERIPH) == I2S2EXT) || \
+                                             ((PERIPH) == I2S3EXT))
+#endif
+
+/** @defgroup SPI_data_direction
+  * @{
+  */
+
+#define SPI_TRANSMODE_FULLDUPLEX            ((uint16_t)0x0000)
+#define SPI_TRANSMODE_RXONLY                ((uint16_t)0x0400)
+#define SPI_TRANSMODE_RX_HALFDUPLEX         ((uint16_t)0x8000)
+#define SPI_TRANSMODE_TX_HALFDUPLEX         ((uint16_t)0xC000)
+#define IS_SPI_TRANS_MODE(MODE)             (((MODE) == SPI_TRANSMODE_FULLDUPLEX) || \
+                                             ((MODE) == SPI_TRANSMODE_RXONLY) || \
+                                             ((MODE) == SPI_TRANSMODE_RX_HALFDUPLEX) || \
+                                             ((MODE) == SPI_TRANSMODE_TX_HALFDUPLEX))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_mode
+  * @{
+  */
+
+#define SPI_MODE_MASTER                     ((uint16_t)0x0104)
+#define SPI_MODE_SLAVE                      ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE)                   (((MODE) == SPI_MODE_MASTER) || \
+                                             ((MODE) == SPI_MODE_SLAVE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_data_size
+  * @{
+  */
+
+#define SPI_FRAMESIZE_16BIT                 ((uint16_t)0x0800)
+#define SPI_FRAMESIZE_8BIT                  ((uint16_t)0x0000)
+#define IS_SPI_FRAMESIZE(FRAMESIZE)         (((FRAMESIZE) == SPI_FRAMESIZE_16BIT) || \
+                                             ((FRAMESIZE) == SPI_FRAMESIZE_8BIT))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Polarity
+  * @{
+  */
+
+#define SPI_CPOL_LOW                        ((uint16_t)0x0000)
+#define SPI_CPOL_HIGH                       ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL)                   (((CPOL) == SPI_CPOL_LOW) || \
+                                             ((CPOL) == SPI_CPOL_HIGH))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase
+  * @{
+  */
+
+#define SPI_CPHA_1EDGE                      ((uint16_t)0x0000)
+#define SPI_CPHA_2EDGE                      ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA)                   (((CPHA) == SPI_CPHA_1EDGE) || \
+                                             ((CPHA) == SPI_CPHA_2EDGE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management
+  * @{
+  */
+
+#define SPI_NSSSEL_SOFT                     ((uint16_t)0x0200)
+#define SPI_NSSSEL_HARD                     ((uint16_t)0x0000)
+#define IS_SPI_NSSSEL(NSSSEL)               (((NSSSEL) == SPI_NSSSEL_SOFT) || \
+                                             ((NSSSEL) == SPI_NSSSEL_HARD))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_BaudRate_Prescaler
+  * @{
+  */
+
+
+#define SPI_MCLKP_OVER_256                  ((uint16_t)0x8000)
+                                            
+#define SPI_MCLKP_2                         ((uint16_t)0x0000)
+#define SPI_MCLKP_4                         ((uint16_t)0x0008)
+#define SPI_MCLKP_8                         ((uint16_t)0x0010)
+#define SPI_MCLKP_16                        ((uint16_t)0x0018)
+#define SPI_MCLKP_32                        ((uint16_t)0x0020)
+#define SPI_MCLKP_64                        ((uint16_t)0x0028)
+#define SPI_MCLKP_128                       ((uint16_t)0x0030)
+#define SPI_MCLKP_256                       ((uint16_t)0x0038)
+#define SPI_MCLKP_512                       ((uint16_t)0x8000)
+#define SPI_MCLKP_1024                      ((uint16_t)0x8008)
+#define IS_SPI_MCLKP(MCLKP)                 (((MCLKP) == SPI_MCLKP_2) || \
+                                             ((MCLKP) == SPI_MCLKP_4) || \
+                                             ((MCLKP) == SPI_MCLKP_8) || \
+                                             ((MCLKP) == SPI_MCLKP_16) || \
+                                             ((MCLKP) == SPI_MCLKP_32) || \
+                                             ((MCLKP) == SPI_MCLKP_64) || \
+                                             ((MCLKP) == SPI_MCLKP_128) || \
+                                             ((MCLKP) == SPI_MCLKP_256) || \
+                                             ((MCLKP) == SPI_MCLKP_512) || \
+                                             ((MCLKP) == SPI_MCLKP_1024))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_MSB_LSB_transmission
+  * @{
+  */
+
+#define SPI_FIRSTBIT_MSB                    ((uint16_t)0x0000)
+#define SPI_FIRSTBIT_LSB                    ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT)               (((BIT) == SPI_FIRSTBIT_MSB) || \
+                                             ((BIT) == SPI_FIRSTBIT_LSB))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Mode
+  * @{
+  */
+
+#define I2S_MODE_SLAVETX                    ((uint16_t)0x0000)
+#define I2S_MODE_SLAVERX                    ((uint16_t)0x0100)
+#define I2S_MODE_MASTERTX                   ((uint16_t)0x0200)
+#define I2S_MODE_MASTERRX                   ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE)                   (((MODE) == I2S_MODE_SLAVETX) || \
+                                             ((MODE) == I2S_MODE_SLAVERX) || \
+                                             ((MODE) == I2S_MODE_MASTERTX) || \
+                                             ((MODE) == I2S_MODE_MASTERRX) )
+/**
+  * @}
+  */
+
+/** @defgroup I2S_AUDIOPROTOCOL
+  * @{
+  */
+
+#define I2S_AUDIOPROTOCOL_PHILLIPS                  ((uint16_t)0x0000)
+#define I2S_AUDIOPROTOCOL_MSB                       ((uint16_t)0x0010)
+#define I2S_AUDIOPROTOCOL_LSB                       ((uint16_t)0x0020)
+#define I2S_AUDIOPROTOCOL_PCMSHORT                  ((uint16_t)0x0030)
+#define I2S_AUDIOPROTOCOL_PCMLONG                   ((uint16_t)0x00B0)
+#define IS_I2S_AUDIOPROTOCOL(AUDIOPROTOCOL)         (((AUDIOPROTOCOL) == I2S_AUDIOPROTOCOL_PHILLIPS) || \
+                                                     ((AUDIOPROTOCOL) == I2S_AUDIOPROTOCOL_MSB) || \
+                                                     ((AUDIOPROTOCOL) == I2S_AUDIOPROTOCOL_LSB) || \
+                                                     ((AUDIOPROTOCOL) == I2S_AUDIOPROTOCOL_PCMSHORT) || \
+                                                     ((AUDIOPROTOCOL) == I2S_AUDIOPROTOCOL_PCMLONG))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Data_Format
+  * @{
+  */
+
+#define I2S_FRAMEFORMAT_DL16BIT_CHL16BIT    ((uint16_t)0x0000)
+#define I2S_FRAMEFORMAT_DL16BIT_CHL32BIT    ((uint16_t)0x0001)
+#define I2S_FRAMEFORMAT_DL24BIT_CHL32BIT    ((uint16_t)0x0003)
+#define I2S_FRAMEFORMAT_DL32BIT_CHL32BIT    ((uint16_t)0x0005)
+#define IS_I2S_FRAMEFORMAT(FRAMEFORMAT)     (((FRAMEFORMAT) == I2S_FRAMEFORMAT_DL16BIT_CHL16BIT) || \
+                                             ((FRAMEFORMAT) == I2S_FRAMEFORMAT_DL16BIT_CHL32BIT) || \
+                                             ((FRAMEFORMAT) == I2S_FRAMEFORMAT_DL24BIT_CHL32BIT) || \
+                                             ((FRAMEFORMAT) == I2S_FRAMEFORMAT_DL32BIT_CHL32BIT))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_MCLK_Output
+  * @{
+  */
+
+#define I2S_MCLKOE_ENABLE                   ((uint16_t)0x0200)
+#define I2S_MCLKOE_DISABLE                  ((uint16_t)0x0000)
+#define IS_I2S_MCLKOE(MCLKOE)               (((MCLKOE) == I2S_MCLKOE_ENABLE) || \
+                                             ((MCLKOE) == I2S_MCLKOE_DISABLE))
+/**
+  * @}
+  */
+  
+#define I2S_DIV_VALUE_MAX                   ((uint16_t)0x03FF)
+#define I2S_DIV_EXT_VALUE_MASK              ((uint16_t)0x0300)
+#define I2S_DIV_EXT_VALUE_LSHIFT_OFFSET     ((uint16_t)2)
+
+/** @defgroup I2S_Audio_Frequency
+  * @{
+  */
+
+#define I2S_AUDIOFREQ_192K                  ((uint32_t)192000)
+#define I2S_AUDIOFREQ_96K                   ((uint32_t)96000)
+#define I2S_AUDIOFREQ_48K                   ((uint32_t)48000)
+#define I2S_AUDIOFREQ_44K                   ((uint32_t)44100)
+#define I2S_AUDIOFREQ_32K                   ((uint32_t)32000)
+#define I2S_AUDIOFREQ_22K                   ((uint32_t)22050)
+#define I2S_AUDIOFREQ_16K                   ((uint32_t)16000)
+#define I2S_AUDIOFREQ_11K                   ((uint32_t)11025)
+#define I2S_AUDIOFREQ_8K                    ((uint32_t)8000)
+#define I2S_AUDIOFREQ_DEFAULT               ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ)             ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
+                                             ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+                                             ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Clock_Polarity
+  * @{
+  */
+
+#define I2S_CPOL_LOW                        ((uint16_t)0x0000)
+#define I2S_CPOL_HIGH                       ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL)                   (((CPOL) == I2S_CPOL_LOW) || \
+                                             ((CPOL) == I2S_CPOL_HIGH))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests
+  * @{
+  */
+
+#define SPI_I2S_DMA_TX                      ((uint16_t)0x0002)
+#define SPI_I2S_DMA_RX                      ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMA(DMA)                 ((((DMA) & (uint16_t)0xFFFC) == 0x00) && ((DMA) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_NSS_internal_software_management
+  * @{
+  */
+
+#define SPI_ISS_SET                         ((uint16_t)0x0100)
+#define SPI_ISS_RESET                       ((uint16_t)0xFEFF)
+#define IS_SPI_ISS(ISS)                     (((ISS) == SPI_ISS_SET) || \
+                                             ((ISS) == SPI_ISS_RESET))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Transmit_Receive
+  * @{
+  */
+
+#define SPI_CRC_TX                          ((uint8_t)0x00)
+#define SPI_CRC_RX                          ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC)                     (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_direction_transmit_receive
+  * @{
+  */
+
+#define SPI_HALFDUPLEX_RX                   ((uint16_t)0xBFFF)
+#define SPI_HALFDUPLEX_TX                   ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION)         (((DIRECTION) == SPI_HALFDUPLEX_RX) || \
+                                             ((DIRECTION) == SPI_HALFDUPLEX_TX))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_interrupts_definition
+  * @{
+  */
+
+#define SPI_I2S_INT_TE                      ((uint8_t)0x71)
+#define SPI_I2S_INT_RNE                     ((uint8_t)0x60)
+#define SPI_I2S_INT_ERR                     ((uint8_t)0x50)
+#define IS_SPI_I2S_CONFIG_INT(INT)          (((INT) == SPI_I2S_INT_TE) || \
+                                             ((INT) == SPI_I2S_INT_RNE) || \
+                                             ((INT) == SPI_I2S_INT_ERR))
+#define SPI_I2S_INT_OVR                     ((uint8_t)0x56)
+#define SPI_INT_MODF                        ((uint8_t)0x55)
+#define SPI_INT_CERR                        ((uint8_t)0x54)
+#define I2S_INT_UDR                         ((uint8_t)0x53)
+#define IS_SPI_I2S_CLEAR_INT(INT)           (((INT) == SPI_INT_CERR))
+#define IS_SPI_I2S_GET_INT(INT)             (((INT) == SPI_I2S_INT_RNE) || ((INT) == SPI_I2S_INT_TE) || \
+                                             ((INT) == I2S_INT_UDR)     || ((INT) == SPI_INT_CERR) || \
+                                             ((INT) == SPI_INT_MODF)    || ((INT) == SPI_I2S_INT_OVR))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_flags_definition
+  * @{
+  */
+
+#define SPI_I2S_FLAG_RNE                    ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TE                     ((uint16_t)0x0002)
+#define I2S_FLAG_CS                         ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                        ((uint16_t)0x0008)
+#define SPI_FLAG_CERR                       ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                       ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                    ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BUSY                   ((uint16_t)0x0080)
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG)         (((FLAG) == SPI_FLAG_CERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG)           (((FLAG) == SPI_I2S_FLAG_BUSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+                                             ((FLAG) == SPI_FLAG_MODF)     || ((FLAG) == SPI_FLAG_CERR) || \
+                                             ((FLAG) == I2S_FLAG_UDR)      || ((FLAG) == I2S_FLAG_CS) || \
+                                             ((FLAG) == SPI_I2S_FLAG_TE)   || ((FLAG) == SPI_I2S_FLAG_RNE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_polynomial
+  * @{
+  */
+
+#define IS_SPI_CPOLY(CPOLY)                 ((CPOLY) >= 0x1)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Functions
+  * @{
+  */
+uint16_t SPI_GetCRC(SPI_Type* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_Type* SPIx);
+void SPI_HalfDuplexTransModeConfig(SPI_Type* SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_Type* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_Type* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_Type* SPIx, uint8_t SPI_I2S_INT);
+void SPI_I2S_ClearINTPendingBit(SPI_Type* SPIx, uint8_t SPI_I2S_INT);
+void SPI_I2S_INTConfig(SPI_Type* SPIx, uint8_t SPI_I2S_INT, FunctionalState NewState);
+void SPI_I2S_DMAEnable(SPI_Type* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_I2S_TxData(SPI_Type* SPIx, uint16_t Data);
+uint16_t SPI_I2S_RxData(SPI_Type* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_Type* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_NSSHardwareOutputEnable(SPI_Type* SPIx, FunctionalState NewState);
+void SPI_FrameSizeConfig(SPI_Type* SPIx, uint16_t SPI_DataSize);
+void SPI_TxCRC(SPI_Type* SPIx);
+void SPI_CRCEN(SPI_Type* SPIx, FunctionalState NewState);
+void SPI_I2S_Reset(SPI_Type* SPIx);
+void SPI_Init(SPI_Type* SPIx, SPI_InitType* SPI_InitStruct);
+void I2S_Init(SPI_Type* SPIx, I2S_InitType* I2S_InitStruct);
+void SPI_DefaultInitParaConfig(SPI_InitType* SPI_InitStruct);
+void I2S_DefaultInit(I2S_InitType* I2S_InitStruct);
+void SPI_Enable(SPI_Type* SPIx, FunctionalState NewState);
+void I2S_Enable(SPI_Type* SPIx, FunctionalState NewState);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4XX_SPI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_syscfg.h

@@ -0,0 +1,192 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_syscfg.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx SYSCFG header file
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_SYSCFG_H
+#define __AT32F4XX_SYSCFG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SYSCFG
+  * @{
+  */
+
+#if defined (AT32F421xx)
+
+/** @defgroup SYSCFG_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup SYSCFG_EXTI_Port_Sources 
+  * @{
+  */ 
+#define EXTI_PortSourceGPIOA       ((uint8_t)0x00)
+#define EXTI_PortSourceGPIOB       ((uint8_t)0x01)
+#define EXTI_PortSourceGPIOC       ((uint8_t)0x02)
+#define EXTI_PortSourceGPIOD       ((uint8_t)0x03)
+#define EXTI_PortSourceGPIOF       ((uint8_t)0x05)
+
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOF)) 
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_EXTI_Pin_sources 
+  * @{
+  */ 
+#define EXTI_PinSource0            ((uint8_t)0x00)
+#define EXTI_PinSource1            ((uint8_t)0x01)
+#define EXTI_PinSource2            ((uint8_t)0x02)
+#define EXTI_PinSource3            ((uint8_t)0x03)
+#define EXTI_PinSource4            ((uint8_t)0x04)
+#define EXTI_PinSource5            ((uint8_t)0x05)
+#define EXTI_PinSource6            ((uint8_t)0x06)
+#define EXTI_PinSource7            ((uint8_t)0x07)
+#define EXTI_PinSource8            ((uint8_t)0x08)
+#define EXTI_PinSource9            ((uint8_t)0x09)
+#define EXTI_PinSource10           ((uint8_t)0x0A)
+#define EXTI_PinSource11           ((uint8_t)0x0B)
+#define EXTI_PinSource12           ((uint8_t)0x0C)
+#define EXTI_PinSource13           ((uint8_t)0x0D)
+#define EXTI_PinSource14           ((uint8_t)0x0E)
+#define EXTI_PinSource15           ((uint8_t)0x0F)
+
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
+                                       ((PINSOURCE) == EXTI_PinSource1) || \
+                                       ((PINSOURCE) == EXTI_PinSource2) || \
+                                       ((PINSOURCE) == EXTI_PinSource3) || \
+                                       ((PINSOURCE) == EXTI_PinSource4) || \
+                                       ((PINSOURCE) == EXTI_PinSource5) || \
+                                       ((PINSOURCE) == EXTI_PinSource6) || \
+                                       ((PINSOURCE) == EXTI_PinSource7) || \
+                                       ((PINSOURCE) == EXTI_PinSource8) || \
+                                       ((PINSOURCE) == EXTI_PinSource9) || \
+                                       ((PINSOURCE) == EXTI_PinSource10) || \
+                                       ((PINSOURCE) == EXTI_PinSource11) || \
+                                       ((PINSOURCE) == EXTI_PinSource12) || \
+                                       ((PINSOURCE) == EXTI_PinSource13) || \
+                                       ((PINSOURCE) == EXTI_PinSource14) || \
+                                       ((PINSOURCE) == EXTI_PinSource15))
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_PA11_PA12_Remap_Config 
+  * @{
+  */ 
+#define SYSCFG_GPIORemap_PA11_PA12  ((uint32_t)0x00000010)    /* PA11 and PA12 remapping bit for small packages (28 and 20 pins). */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Memory_Remap_Config 
+  * @{
+  */ 
+#define SYSCFG_MemoryRemap_Flash                ((uint8_t)0x00)
+#define SYSCFG_MemoryRemap_SystemMemory         ((uint8_t)0x01)
+#define SYSCFG_MemoryRemap_SRAM                 ((uint8_t)0x03)
+
+
+#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+                                       ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
+                                       ((REMAP) == SYSCFG_MemoryRemap_SRAM))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_DMA_Remap_Config 
+  * @{
+  */ 
+#define SYSCFG_DMARemap_TIM17       SYSCFG_CFGR1_TIM17_DMA_RMP    /* Remap TIM17 DMA requests from channel1 to channel2 */
+#define SYSCFG_DMARemap_TIM16       SYSCFG_CFGR1_TIM16_DMA_RMP    /* Remap TIM16 DMA requests from channel3 to channel4 */
+#define SYSCFG_DMARemap_USART1Rx    SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */
+#define SYSCFG_DMARemap_USART1Tx    SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */
+#define SYSCFG_DMARemap_ADC1        SYSCFG_CFGR1_ADC_DMA_RMP      /* Remap ADC1 DMA requests from channel1 to channel2 */
+  
+#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
+                                    ((REMAP) == SYSCFG_DMARemap_TIM16) || \
+                                    ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \
+                                    ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \
+                                    ((REMAP) == SYSCFG_DMARemap_ADC1))
+
+/**
+  * @}
+  */
+  
+/** @defgroup SYSCFG_IRTMR_Mode_Config 
+  * @{
+  */ 
+#define SYSCFG_IRTMR_Mode_TIM16       SYSCFG_CFGR1_TIM16_IRTMR_MODE    /* IRTMR MODE1: TIM16 */
+#define SYSCFG_IRTMR_Mode_USART1      SYSCFG_CFGR1_USART1_IRTMR_MODE   /* IRTMR MODE1: USART1 */
+#define SYSCFG_IRTMR_Mode_USART2      SYSCFG_CFGR1_USART2_IRTMR_MODE   /* IRTMR MODE1: USART2 */
+
+  
+#define IS_SYSCFG_IRTMR_MODE(MODE) (((MODE) == SYSCFG_IRTMR_Mode_TIM16) || \
+                                    ((MODE) == SYSCFG_IRTMR_Mode_USART1) || \
+                                    ((MODE) == SYSCFG_IRTMR_Mode_USART2))
+
+/**
+  * @}
+  */
+  
+/** @defgroup SYSCFG_IRTMR_Pol_Config 
+  * @{
+  */ 
+#define SYSCFG_IRTMR_Pol_High       SYSCFG_CFGR1_Pol_IRTMR_HIGH    /* IRTMR Pol: high */
+#define SYSCFG_IRTMR_Pol_Low        SYSCFG_CFGR1_Pol_IRTMR_LOW     /* IRTMR Pol: low */
+
+  
+#define IS_SYSCFG_IRTMR_POL(POL)   (((POL) == SYSCFG_CFGR1_Pol_IRTMR_HIGH) || \
+                                    ((POL) == SYSCFG_CFGR1_Pol_IRTMR_LOW))
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+void SYSCFG_DeInit(void);
+void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
+void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
+void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
+void SYSCFG_IRTMRConfig(uint32_t IRTMR_Mode,uint32_t IR_Pol);
+void SYSCFG_GPIORemapConfig(FunctionalState NewState);
+
+#endif /*__AT32F4XX_SYSCFG_H */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* AT32F421xx */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */

StdPeriph_Driver/inc/at32f4xx_usart.h

@@ -0,0 +1,424 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_usart.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx USART header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_USART_H
+#define __AT32F4XX_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */
+
+/** @defgroup USART_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  USART Init Structure definition
+  */
+
+typedef struct
+{
+    uint32_t USART_BaudRate;                /*!< This member configures the USART communication baud rate.
+                                                 The baud rate is computed using the following formula:
+                                                  - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                                  - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+    uint16_t USART_WordLength;               /*!< Specifies the number of data bits transmitted or received in a frame.
+                                                  This parameter can be a value of @ref USART_Word_Length */
+
+    uint16_t USART_StopBits;                /*!< Specifies the number of stop bits transmitted.
+                                                 This parameter can be a value of @ref USART_Stop_Bits */
+                                             
+    uint16_t USART_Parity;                  /*!< Specifies the parity mode.
+                                                 This parameter can be a value of @ref USART_Parity
+                                                 @note When parity is enabled, the computed parity is inserted
+                                                       at the MSB position of the transmitted data (9th bit when
+                                                       the word length is set to 9 data bits; 8th bit when the
+                                                       word length is set to 8 data bits). */
+                                            
+    uint16_t USART_Mode;                    /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                                 This parameter can be a value of @ref USART_Mode */
+                                            
+    uint16_t USART_HardwareFlowControl;     /*!< Specifies wether the hardware flow control mode is enabled
+                                                 or disabled.
+                                                 This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitType;
+
+/**
+  * @brief  USART Clock Init Structure definition
+  */
+
+typedef struct
+{
+
+    uint16_t USART_Clock;                   /*!< Specifies whether the USART clock is enabled or disabled.
+                                                This parameter can be a value of @ref USART_Clock */
+                                            
+    uint16_t USART_CPOL;                    /*!< Specifies the steady state value of the serial clock.
+                                                This parameter can be a value of @ref USART_Clock_Polarity */
+                                            
+    uint16_t USART_CPHA;                    /*!< Specifies the clock transition on which the bit capture is made.
+                                                This parameter can be a value of @ref USART_Clock_Phase */
+                                            
+    uint16_t USART_LastBit;                 /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                                data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                                This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Exported_Constants
+  * @{
+  */
+#if defined (AT32F403xx) || defined (AT32F413xx) || defined (AT32F415xx)
+  #define IS_USART_ALL_PERIPH(PERIPH)         (((PERIPH) == USART1) || \
+                                               ((PERIPH) == USART2) || \
+                                               ((PERIPH) == USART3) || \
+                                               ((PERIPH) == UART4)  || \
+                                               ((PERIPH) == UART5))
+#elif defined (AT32F403Axx)|| defined (AT32F407xx)
+  #define IS_USART_ALL_PERIPH(PERIPH)         (((PERIPH) == USART1) || \
+                                               ((PERIPH) == USART2) || \
+                                               ((PERIPH) == USART3) || \
+                                               ((PERIPH) == UART4)  || \
+                                               ((PERIPH) == UART5)  || \
+                                               ((PERIPH) == USART6) || \
+                                               ((PERIPH) == UART7)  || \
+                                               ((PERIPH) == UART8))
+#elif defined (AT32F421xx)
+  #define IS_USART_ALL_PERIPH(PERIPH)         (((PERIPH) == USART1) || \
+                                               ((PERIPH) == USART2))
+#endif
+
+#if !defined (AT32F421xx)
+#define IS_USART_123_PERIPH(PERIPH)         (((PERIPH) == USART1) || \
+                                             ((PERIPH) == USART2) || \
+                                             ((PERIPH) == USART3))
+#else
+#define IS_USART_123_PERIPH(PERIPH)         (((PERIPH) == USART1) || \
+                                             ((PERIPH) == USART2))
+#endif
+
+#if !defined (AT32F421xx)
+#define IS_USART_1234_PERIPH(PERIPH)        (((PERIPH) == USART1) || \
+                                             ((PERIPH) == USART2) || \
+                                             ((PERIPH) == USART3) || \
+                                             ((PERIPH) == UART4))
+#else
+#define IS_USART_1234_PERIPH(PERIPH)        (((PERIPH) == USART1) || \
+                                             ((PERIPH) == USART2))
+#endif
+/** @defgroup USART_Word_Length
+  * @{
+  */
+
+#define USART_WordLength_8b                 ((uint16_t)0x0000)
+#define USART_WordLength_9b                 ((uint16_t)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH)        (((LENGTH) == USART_WordLength_8b) || \
+                                             ((LENGTH) == USART_WordLength_9b))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Stop_Bits
+  * @{
+  */
+                                            
+#define USART_StopBits_1                    ((uint16_t)0x0000)
+#define USART_StopBits_0_5                  ((uint16_t)0x1000)
+#define USART_StopBits_2                    ((uint16_t)0x2000)
+#define USART_StopBits_1_5                  ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS)         (((STOPBITS) == USART_StopBits_1) || \
+                                             ((STOPBITS) == USART_StopBits_0_5) || \
+                                             ((STOPBITS) == USART_StopBits_2) || \
+                                             ((STOPBITS) == USART_StopBits_1_5))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Parity
+  * @{
+  */
+
+#define USART_Parity_No                     ((uint16_t)0x0000)
+#define USART_Parity_Even                   ((uint16_t)0x0400)
+#define USART_Parity_Odd                    ((uint16_t)0x0600)
+#define IS_USART_PARITY(PARITY)             (((PARITY) == USART_Parity_No) || \
+                                             ((PARITY) == USART_Parity_Even) || \
+                                             ((PARITY) == USART_Parity_Odd))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Mode
+  * @{
+  */
+
+#define USART_Mode_Rx                       ((uint16_t)0x0004)
+#define USART_Mode_Tx                       ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE)                 ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Hardware_Flow_Control
+  * @{
+  */
+#define USART_HardwareFlowControl_None      ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS       ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS       ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS   ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                                            (((CONTROL) == USART_HardwareFlowControl_None) || \
+                                             ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+                                             ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+                                             ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock
+  * @{
+  */
+#define USART_Clock_Disable                 ((uint16_t)0x0000)
+#define USART_Clock_Enable                  ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK)               (((CLOCK) == USART_Clock_Disable) || \
+                                             ((CLOCK) == USART_Clock_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Polarity
+  * @{
+  */
+
+#define USART_CPOL_Low                      ((uint16_t)0x0000)
+#define USART_CPOL_High                     ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL)                 (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Phase
+  * @{
+  */
+
+#define USART_CPHA_1Edge                    ((uint16_t)0x0000)
+#define USART_CPHA_2Edge                    ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA)                 (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit
+  * @{
+  */
+
+#define USART_LastBit_Disable               ((uint16_t)0x0000)
+#define USART_LastBit_Enable                ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT)           (((LASTBIT) == USART_LastBit_Disable) || \
+                                             ((LASTBIT) == USART_LastBit_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Interrupt_definition
+  * @{
+  */
+
+#define USART_INT_PERR                      ((uint16_t)0x0028)
+#define USART_INT_TDE                       ((uint16_t)0x0727)
+#define USART_INT_TRAC                      ((uint16_t)0x0626)
+#define USART_INT_RDNE                      ((uint16_t)0x0525)
+#define USART_INT_IDLEF                     ((uint16_t)0x0424)
+#define USART_INT_LBDF                      ((uint16_t)0x0846)
+#define USART_INT_CTSF                      ((uint16_t)0x096A)
+#define USART_INT_ERR                       ((uint16_t)0x0060)
+#define USART_INT_ORERR                     ((uint16_t)0x0360)
+#define USART_INT_NERR                      ((uint16_t)0x0260)
+#define USART_INT_FERR                      ((uint16_t)0x0160)
+#define IS_USART_CONFIG_INT(INT)            (((INT) == USART_INT_PERR)  || ((INT) == USART_INT_TDE) || \
+                                             ((INT) == USART_INT_TRAC)  || ((INT) == USART_INT_RDNE) || \
+                                             ((INT) == USART_INT_IDLEF) || ((INT) == USART_INT_LBDF) || \
+                                             ((INT) == USART_INT_CTSF)  || ((INT) == USART_INT_ERR))
+#define IS_USART_GET_INT(INT)               (((INT) == USART_INT_PERR)  || ((INT) == USART_INT_TDE) || \
+                                             ((INT) == USART_INT_TRAC)  || ((INT) == USART_INT_RDNE) || \
+                                             ((INT) == USART_INT_IDLEF) || ((INT) == USART_INT_LBDF) || \
+                                             ((INT) == USART_INT_CTSF)  || ((INT) == USART_INT_ORERR) || \
+                                             ((INT) == USART_INT_NERR)  || ((INT) == USART_INT_FERR))
+#define IS_USART_CLEAR_INT(INT)             (((INT) == USART_INT_TRAC)  || ((INT) == USART_INT_RDNE) || \
+                                             ((INT) == USART_INT_LBDF)  || ((INT) == USART_INT_CTSF))
+/**
+  * @}
+  */
+
+/** @defgroup USART_DMA_Requests
+  * @{
+  */
+
+#define USART_DMAReq_Tx                     ((uint16_t)0x0080)
+#define USART_DMAReq_Rx                     ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ)             ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_WakeUp_methods
+  * @{
+  */
+
+#define USART_WakeUp_IdleLine               ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark            ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP)             (((WAKEUP) == USART_WakeUp_IdleLine) || \
+                                             ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+  * @}
+  */
+
+/** @defgroup USART_LIN_Break_Detection_Length
+  * @{
+  */
+
+#define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+                                            (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+                                             ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+  * @}
+  */
+
+/** @defgroup USART_IrDA_Low_Power
+  * @{
+  */
+
+#define USART_IrDAMode_LowPower             ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal               ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE)            (((MODE) == USART_IrDAMode_LowPower) || \
+                                             ((MODE) == USART_IrDAMode_Normal))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Flags
+  * @{
+  */
+
+#define USART_FLAG_CTSF                     ((uint16_t)0x0200)
+#define USART_FLAG_LBDF                     ((uint16_t)0x0100)
+#define USART_FLAG_TDE                      ((uint16_t)0x0080)
+#define USART_FLAG_TRAC                     ((uint16_t)0x0040)
+#define USART_FLAG_RDNE                     ((uint16_t)0x0020)
+#define USART_FLAG_IDLEF                    ((uint16_t)0x0010)
+#define USART_FLAG_ORERR                    ((uint16_t)0x0008)
+#define USART_FLAG_NERR                     ((uint16_t)0x0004)
+#define USART_FLAG_FERR                     ((uint16_t)0x0002)
+#define USART_FLAG_PERR                     ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG)                 (((FLAG) == USART_FLAG_PERR) || ((FLAG) == USART_FLAG_TDE) || \
+                                             ((FLAG) == USART_FLAG_TRAC) || ((FLAG) == USART_FLAG_RDNE) || \
+                                             ((FLAG) == USART_FLAG_IDLEF)|| ((FLAG) == USART_FLAG_LBDF) || \
+                                             ((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_ORERR) || \
+                                             ((FLAG) == USART_FLAG_NERR) || ((FLAG) == USART_FLAG_FERR))
+
+#define IS_USART_CLEAR_FLAG(FLAG)           ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG)    ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
+                                                     ((*(uint32_t*)&(PERIPH)) != UART5_BASE) &&\
+                                                     ((*(uint32_t*)&(PERIPH)) != UART7_BASE) &&\
+                                                     ((*(uint32_t*)&(PERIPH)) != UART8_BASE)) \
+                                                     || ((USART_FLAG) != USART_FLAG_CTSF))
+#define IS_USART_ADDRESS(ADDRESS)           ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA)                 ((DATA) <= 0x1FF)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Exported_Functions
+  * @{
+  */
+void USART_SendBreak(USART_Type* USARTx);
+void USART_SetGuardTime(USART_Type* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_Type* USARTx, uint8_t USART_Prescaler);
+void USART_SmartCardCmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_Type* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_Type* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_Type* USARTx, uint16_t USART_FLAG);
+void USART_Reset(USART_Type* USARTx);
+void USART_Init(USART_Type* USARTx, USART_InitType* USART_InitStruct);
+void USART_StructInit(USART_InitType* USART_InitStruct);
+void USART_ClockInit(USART_Type* USARTx, USART_ClockInitType* USART_ClockInitStruct);
+void USART_ReceiverWakeUpCmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_Type* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_SendData(USART_Type* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_Type* USARTx);
+void USART_ClearFlag(USART_Type* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_Type* USARTx, uint16_t USART_INT);
+void USART_ClearITPendingBit(USART_Type* USARTx, uint16_t USART_INT);
+#if defined (AT32F421xx)
+void USART_SWAP(USART_Type* USARTx, FunctionalState NewState);
+#endif
+void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct);
+void USART_Cmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_INTConfig(USART_Type* USARTx, uint16_t USART_INT, FunctionalState NewState);
+void USART_DMACmd(USART_Type* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_Type* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_Type* USARTx, uint16_t USART_WakeUp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_USART_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_wwdg.h

@@ -0,0 +1,103 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_wwdg.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx WWDG header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_WWDG_H
+#define __AT32F4XX_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */
+
+/** @defgroup WWDG_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup WWDG_Prescaler
+  * @{
+  */
+
+#define WWDG_Psc_1                          ((uint32_t)0x00000000)
+#define WWDG_Psc_2                          ((uint32_t)0x00000080)
+#define WWDG_Psc_4                          ((uint32_t)0x00000100)
+#define WWDG_Psc_8                          ((uint32_t)0x00000180)
+#define IS_WWDG_PSC(PSC)                    (((PSC) == WWDG_Psc_1) || \
+                                             ((PSC) == WWDG_Psc_2) || \
+                                             ((PSC) == WWDG_Psc_4) || \
+                                             ((PSC) == WWDG_Psc_8))
+#define IS_WWDG_WCNTR(WCNTR)                ((WCNTR) <= 0x7F)
+#define IS_WWDG_CNTR(CNTR)                  (((CNTR) >= 0x40) && ((CNTR) <= 0x7F))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Exported_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Exported_Functions
+  * @{
+  */
+void WWDG_SetCounter(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+void WWDG_Reset(void);
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowCounter(uint8_t WindowValue);
+void WWDG_EnableINT(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4XX_WWDG_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/at32f4xx_xmc.h

@@ -0,0 +1,738 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_xmc.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx XMC header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_XMC_H
+#define __AT32F4XX_XMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup XMC
+  * @{
+  */
+
+/** @defgroup XMC_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  Timing parameters For NOR/SRAM Banks
+  */
+
+typedef struct
+{
+    uint32_t XMC_AdrOpTime;                 /*!< Defines the number of HCLK cycles to configure
+                                                       the duration of the address setup time.
+                                                       This parameter can be a value between 0 and 0xF.
+                                                       @note: It is not used with synchronous NOR Flash memories. */
+
+    uint32_t XMC_AdrHoldTime;               /*!< Defines the number of HCLK cycles to configure
+                                                    the duration of the address hold time.
+                                                    This parameter can be a value between 0 and 0xF.
+                                                    @note: It is not used with synchronous NOR Flash memories.*/
+
+    uint32_t XMC_DataOpTime;                /*!< Defines the number of HCLK cycles to configure
+                                                   the duration of the data setup time.
+                                                   This parameter can be a value between 0 and 0xFF.
+                                                   @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+    uint32_t XMC_IntervalBetweenOP;         /*!< Defines the number of HCLK cycles to configure
+                                                    the duration of the bus turnaround.
+                                                    This parameter can be a value between 0 and 0xF.
+                                                    @note: It is only used for multiplexed NOR Flash memories. */
+
+    uint32_t XMC_CLKPsc;                    /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+                                                     This parameter can be a value between 1 and 0xF.
+                                                     @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+    uint32_t XMC_DataStableTime;            /*!< Defines the number of memory clock cycles to issue
+                                             to the memory before getting the first data.
+                                             The value of this parameter depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between 0 and 0xF in NOR Flash memories
+                                                with synchronous burst mode enable */
+
+    uint32_t XMC_Mode;                      /*!< Specifies the asynchronous access mode.
+                                                      This parameter can be a value of @ref XMC_Access_Mode */
+} XMC_NORSRAMTimingInitType;
+
+/**
+  * @brief  XMC NOR/SRAM Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t XMC_Bank;                      /*!< Specifies the NOR/SRAM memory bank that will be used.
+                                                 This parameter can be a value of @ref XMC_NORSRAM_Bank */
+
+    uint32_t XMC_DataAdrMux;                /*!< Specifies whether the address and data values are
+                                                 multiplexed on the databus or not.
+                                                 This parameter can be a value of @ref XMC_Data_Address_Bus_Multiplexing */
+
+    uint32_t XMC_Dev;                       /*!< Specifies the type of external memory attached to
+                                                 the corresponding memory bank.
+                                                 This parameter can be a value of @ref XMC_Memory_Type */
+
+    uint32_t XMC_BusType;                   /*!< Specifies the external memory device width.
+                                                        This parameter can be a value of @ref XMC_Data_Width */
+
+    uint32_t XMC_EnableBurstMode;           /*!< Enables or disables the burst access mode for Flash memory,
+                                                 valid only with synchronous burst Flash memories.
+                                                 This parameter can be a value of @ref XMC_Burst_Access_Mode */
+
+    uint32_t XMC_EnableAsynWait;            /*!< Enables or disables wait signal during asynchronous transfers,
+                                                 valid only with asynchronous Flash memories.
+                                                 This parameter can be a value of @ref XMC_EnableAsynWait */
+
+    uint32_t XMC_WaitSignalLv;              /*!< Specifies the wait signal polarity, valid only when accessing
+                                                 the Flash memory in burst mode.
+                                                 This parameter can be a value of @ref XMC_Wait_Signal_Polarity */
+
+    uint32_t XMC_EnableBurstModeSplit;      /*!< Enables or disables the Wrapped burst access mode for Flash
+                                                 memory, valid only when accessing Flash memories in burst mode.
+                                                 This parameter can be a value of @ref XMC_Wrap_Mode */
+
+    uint32_t XMC_WaitSignalConfig;          /*!< Specifies if the wait signal is asserted by the memory one
+                                                 clock cycle before the wait state or during the wait state,
+                                                 valid only when accessing memories in burst mode.
+                                                 This parameter can be a value of @ref XMC_Wait_Timing */
+
+    uint32_t XMC_EnableWrite;               /*!< Enables or disables the write operation in the selected bank by the XMC.
+                                                 This parameter can be a value of @ref XMC_Write_Operation */
+
+    uint32_t XMC_EnableWaitSignal;          /*!< Enables or disables the wait-state insertion via wait
+                                                 signal, valid for Flash memory access in burst mode.
+                                                 This parameter can be a value of @ref XMC_Wait_Signal */
+
+    uint32_t XMC_EnableWriteTiming;         /*!< Enables or disables the extended mode.
+                                                 This parameter can be a value of @ref XMC_Extended_Mode */
+
+    uint32_t XMC_WriteBurstSyn;             /*!< Enables or disables the write burst operation.
+                                                 This parameter can be a value of @ref XMC_Write_Burst */
+
+    XMC_NORSRAMTimingInitType* XMC_RWTimingStruct;  /*!< Timing Parameters for write and read access if the  ExtendedMode is not used*/
+
+    XMC_NORSRAMTimingInitType* XMC_WTimingStruct;   /*!< Timing Parameters for write access if the  ExtendedMode is used*/
+} XMC_NORSRAMInitType;
+
+/**
+  * @brief  Timing parameters For XMC NAND and PCCARD Banks
+  */
+
+typedef struct
+{
+    uint32_t XMC_SetupTime;                 /*!< Defines the number of HCLK cycles to setup address before
+                                                 the command assertion for NAND-Flash read or write access
+                                                 to common/Attribute or I/O memory space (depending on
+                                                 the memory space timing to be configured).
+                                                 This parameter can be a value between 0 and 0xFF.*/
+
+    uint32_t XMC_OpTime;                    /*!< Defines the minimum number of HCLK cycles to assert the
+                                                 command for NAND-Flash read or write access to
+                                                 common/Attribute or I/O memory space (depending on the
+                                                 memory space timing to be configured).
+                                                 This parameter can be a number between 0x00 and 0xFF */
+
+    uint32_t XMC_HoldTime;                  /*!< Defines the number of HCLK clock cycles to hold address
+                                                 (and data for write access) after the command deassertion
+                                                 for NAND-Flash read or write access to common/Attribute
+                                                 or I/O memory space (depending on the memory space timing
+                                                 to be configured).
+                                                 This parameter can be a number between 0x00 and 0xFF */
+
+    uint32_t XMC_WriteSetupTime;            /*!< Defines the number of HCLK clock cycles during which the
+                                                 databus is kept in HiZ after the start of a NAND-Flash
+                                                 write access to common/Attribute or I/O memory space (depending
+                                                 on the memory space timing to be configured).
+                                                 This parameter can be a number between 0x00 and 0xFF */
+} XMC_NAND_PCCARDTimingInitType;
+
+/**
+  * @brief  XMC NAND Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t XMC_Bank;                      /*!< Specifies the NAND memory bank that will be used.
+                                                 This parameter can be a value of @ref XMC_NAND_Bank */
+
+    uint32_t XMC_EnableWait;                /*!< Enables or disables the Wait feature for the NAND Memory Bank.
+                                                 This parameter can be any value of @ref XMC_Wait_feature */
+
+    uint32_t XMC_BusType;                   /*!< Specifies the external memory device width.
+                                                 This parameter can be any value of @ref XMC_Data_Width */
+
+    uint32_t XMC_EnableECC;                 /*!< Enables or disables the ECC computation.
+                                                 This parameter can be any value of @ref XMC_EnableECC */
+
+    uint32_t XMC_ECCPageSize;               /*!< Defines the page size for the extended ECC.
+                                                 This parameter can be any value of @ref XMC_ECC_Page_Size */
+
+    uint32_t XMC_DelayTimeCR;               /*!< Defines the number of HCLK cycles to configure the
+                                                 delay between CLE low and RE low.
+                                                 This parameter can be a value between 0 and 0xFF. */
+
+    uint32_t XMC_DelayTimeAR;               /*!< Defines the number of HCLK cycles to configure the
+                                                 delay between ALE low and RE low.
+                                                 This parameter can be a number between 0x0 and 0xFF */
+
+    XMC_NAND_PCCARDTimingInitType*  XMC_CommonSpaceTimingStruct;    /*!< XMC Common Space Timing */
+
+    XMC_NAND_PCCARDTimingInitType*  XMC_AttributeSpaceTimingStruct; /*!< XMC Attribute Space Timing */
+} XMC_NANDInitType;
+
+/**
+  * @brief  XMC PCCARD Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t XMC_EnableWait;                /*!< Enables or disables the Wait feature for the Memory Bank.
+                                                 This parameter can be any value of @ref XMC_Wait_feature */
+
+    uint32_t XMC_DelayTimeCR;               /*!< Defines the number of HCLK cycles to configure the
+                                                 delay between CLE low and RE low.
+                                                 This parameter can be a value between 0 and 0xFF. */
+
+    uint32_t XMC_DelayTimeAR;               /*!< Defines the number of HCLK cycles to configure the
+                                                 delay between ALE low and RE low.
+                                                 This parameter can be a number between 0x0 and 0xFF */
+
+
+    XMC_NAND_PCCARDTimingInitType*  XMC_CommonSpaceTimingStruct; /*!< XMC Common Space Timing */
+
+    XMC_NAND_PCCARDTimingInitType*  XMC_AttributeSpaceTimingStruct;  /*!< XMC Attribute Space Timing */
+
+    XMC_NAND_PCCARDTimingInitType*  XMC_IOSpaceTimingStruct; /*!< XMC IO Space Timing */
+} XMC_PCCARDInitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup XMC_NORSRAM_Bank
+  * @{
+  */
+#define XMC_Bank1_NORSRAM1                  ((uint32_t)0x00000000)
+#define XMC_Bank1_NORSRAM2                  ((uint32_t)0x00000002)
+#define XMC_Bank1_NORSRAM3                  ((uint32_t)0x00000004)
+#define XMC_Bank1_NORSRAM4                  ((uint32_t)0x00000006)
+/**
+  * @}
+  */
+
+/** @defgroup XMC_SubBank
+  * @{
+  */
+#define XMC_SubBank1_NORSRAM1                  ((uint32_t)0x00000000)
+#define XMC_SubBank1_NORSRAM2                  ((uint32_t)0x00000001)
+#define XMC_SubBank1_NORSRAM3                  ((uint32_t)0x00000002)
+#define XMC_SubBank1_NORSRAM4                  ((uint32_t)0x00000003)
+/**
+  * @}
+  */
+
+
+/** @defgroup XMC_NAND_Bank
+  * @{
+  */
+#define XMC_Bank2_NAND                      ((uint32_t)0x00000010)
+#define XMC_Bank3_NAND                      ((uint32_t)0x00000100)
+/**
+  * @}
+  */
+
+/** @defgroup XMC_PCCARD_Bank
+  * @{
+  */
+#define XMC_Bank4_PCCARD                    ((uint32_t)0x00001000)
+/**
+  * @}
+  */
+
+#define IS_XMC_Sub_NORSRAM_REGION(REGION)       (((REGION) == XMC_SubBank1_NORSRAM1) || \
+                                             ((REGION) == XMC_SubBank1_NORSRAM2) || \
+                                             ((REGION) == XMC_SubBank1_NORSRAM3) || \
+                                             ((REGION) == XMC_SubBank1_NORSRAM4))
+
+#define IS_XMC_NORSRAM_REGION(REGION)       (((REGION) == XMC_Bank1_NORSRAM1) || \
+                                             ((REGION) == XMC_Bank1_NORSRAM2) || \
+                                             ((REGION) == XMC_Bank1_NORSRAM3) || \
+                                             ((REGION) == XMC_Bank1_NORSRAM4))
+
+#define IS_XMC_NAND_BANK(BANK)              (((BANK) == XMC_Bank2_NAND) || \
+                                             ((BANK) == XMC_Bank3_NAND))
+
+#define IS_XMC_GETFLAG_BANK(BANK)           (((BANK) == XMC_Bank2_NAND) || \
+                                             ((BANK) == XMC_Bank3_NAND) || \
+                                             ((BANK) == XMC_Bank4_PCCARD))
+
+#define IS_XMC_INT_BANK(BANK)               (((BANK) == XMC_Bank2_NAND) || \
+                                             ((BANK) == XMC_Bank3_NAND) || \
+                                             ((BANK) == XMC_Bank4_PCCARD))
+
+/** @defgroup NOR_SRAM_Controller
+  * @{
+  */
+
+/** @defgroup XMC_Data_Address_Bus_Multiplexing
+  * @{
+  */
+
+#define XMC_DataAdrMux_Disable              ((uint32_t)0x00000000)
+#define XMC_DataAdrMux_Enable               ((uint32_t)0x00000002)
+#define IS_XMC_MUX(MUX)                     (((MUX) == XMC_DataAdrMux_Disable) || \
+                                             ((MUX) == XMC_DataAdrMux_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Memory_Type
+  * @{
+  */
+
+#define XMC_Dev_SRAM                        ((uint32_t)0x00000000)
+#define XMC_Dev_PSRAM                       ((uint32_t)0x00000004)
+#define XMC_Dev_NOR                         ((uint32_t)0x00000008)
+#define IS_XMC_DEVICE(DEVICE)               (((DEVICE) == XMC_Dev_SRAM) || \
+                                             ((DEVICE) == XMC_Dev_PSRAM)|| \
+                                             ((DEVICE) == XMC_Dev_NOR))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Data_Width
+  * @{
+  */
+
+#define XMC_BusType_8b                      ((uint32_t)0x00000000)
+#define XMC_BusType_16b                     ((uint32_t)0x00000010)
+#define IS_XMC_BUS_TYPE(TYPE)               (((TYPE) == XMC_BusType_8b) || \
+                                             ((TYPE) == XMC_BusType_16b))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Burst_Access_Mode
+  * @{
+  */
+
+#define XMC_BurstMode_Disable               ((uint32_t)0x00000000)
+#define XMC_BurstMode_Enable                ((uint32_t)0x00000100)
+#define IS_XMC_BURSTMODE(STATE)             (((STATE) == XMC_BurstMode_Disable) || \
+                                             ((STATE) == XMC_BurstMode_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup XMC_AsynchronousWait
+  * @{
+  */
+#define XMC_AsynWait_Disable                ((uint32_t)0x00000000)
+#define XMC_AsynWait_Enable                 ((uint32_t)0x00008000)
+#define IS_XMC_ASYNWAIT(STATE)              (((STATE) == XMC_AsynWait_Disable) || \
+                                             ((STATE) == XMC_AsynWait_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Wait_Signal_Polarity
+  * @{
+  */
+
+#define XMC_WaitSignalLv_Low                ((uint32_t)0x00000000)
+#define XMC_WaitSignalLv_High               ((uint32_t)0x00000200)
+#define IS_XMC_WAIT_SIGNAL_LEVEL(LEVEL)     (((LEVEL) == XMC_WaitSignalLv_Low) || \
+                                             ((LEVEL) == XMC_WaitSignalLv_High))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Wrap_Mode
+  * @{
+  */
+
+#define XMC_BurstModeSplit_Disable          ((uint32_t)0x00000000)
+#define XMC_BurstModeSplit_Enable           ((uint32_t)0x00000400)
+#define IS_XMC_BURSTMODE_SPLIT(MODE)        (((MODE) == XMC_BurstModeSplit_Disable) || \
+                                             ((MODE) == XMC_BurstModeSplit_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Wait_Timing
+  * @{
+  */
+
+#define XMC_WaitSignalConfig_BeforeWaitState        ((uint32_t)0x00000000)
+#define XMC_WaitSignalConfig_DuringWaitState        ((uint32_t)0x00000800)
+#define IS_XMC_WAIT_SIGNAL_CONFIG(CONFIG)           (((CONFIG) == XMC_WaitSignalConfig_BeforeWaitState) || \
+                                                     ((CONFIG) == XMC_WaitSignalConfig_DuringWaitState))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Write_Operation
+  * @{
+  */
+
+#define XMC_WriteOperation_Disable          ((uint32_t)0x00000000)
+#define XMC_WriteOperation_Enable           ((uint32_t)0x00001000)
+#define IS_XMC_WRITE_OPERATION(OPERATION)   (((OPERATION) == XMC_WriteOperation_Disable) || \
+                                             ((OPERATION) == XMC_WriteOperation_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Wait_Signal
+  * @{
+  */
+
+#define XMC_WaitSignal_Disable              ((uint32_t)0x00000000)
+#define XMC_WaitSignal_Enable               ((uint32_t)0x00002000)
+#define IS_XMC_WAIT_SIGNAL(SIGNAL)          (((SIGNAL) == XMC_WaitSignal_Disable) || \
+                                             ((SIGNAL) == XMC_WaitSignal_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Extended_Mode
+  * @{
+  */
+
+#define XMC_WriteTiming_Disable             ((uint32_t)0x00000000)
+#define XMC_WriteTiming_Enable              ((uint32_t)0x00004000)
+
+#define IS_XMC_WRITE_TIMING(STATE)          (((STATE) == XMC_WriteTiming_Disable) || \
+                                             ((STATE) == XMC_WriteTiming_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Write_Burst
+  * @{
+  */
+
+#define XMC_WriteBurstSyn_Disable           ((uint32_t)0x00000000)
+#define XMC_WriteBurstSyn_Enable            ((uint32_t)0x00080000)
+#define IS_XMC_WRITE_BURST_SYN(SYN)         (((SYN) == XMC_WriteBurstSyn_Disable) || \
+                                             ((SYN) == XMC_WriteBurstSyn_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Address_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_ADDRESS_OP_TIME(TIME)        ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Address_Hold_Time
+  * @{
+  */
+
+#define IS_XMC_ADDRESS_HOLD_TIME(TIME)      ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Data_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_DATA_OP_TIME(TIME)           (((TIME) > 0) && ((TIME) <= 0xFF))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Bus_Turn_around_Duration
+  * @{
+  */
+
+#define IS_XMC_INTERVAL_BETWEEN_OP_TIME(TIME)       ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_CLK_Division
+  * @{
+  */
+
+#define IS_XMC_CLK_DIV(DIV)                 ((DIV) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Data_Latency
+  * @{
+  */
+
+#define IS_XMC_DATA_STABLE_TIME(TIME)       ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Access_Mode
+  * @{
+  */
+
+#define XMC_Mode_A                          ((uint32_t)0x00000000)
+#define XMC_Mode_B                          ((uint32_t)0x10000000)
+#define XMC_Mode_C                          ((uint32_t)0x20000000)
+#define XMC_Mode_D                          ((uint32_t)0x30000000)
+#define IS_XMC_MODE(MODE)                   (((MODE) == XMC_Mode_A) || \
+                                             ((MODE) == XMC_Mode_B) || \
+                                             ((MODE) == XMC_Mode_C) || \
+                                             ((MODE) == XMC_Mode_D))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup NAND_PCCARD_Controller
+  * @{
+  */
+
+/** @defgroup XMC_Wait_feature
+  * @{
+  */
+
+#define XMC_WaitOperation_Disable           ((uint32_t)0x00000000)
+#define XMC_WaitOperation_Enable            ((uint32_t)0x00000002)
+#define IS_XMC_WAIT_OPERATION(OPERATION)    (((OPERATION) == XMC_WaitOperation_Disable) || \
+                                             ((OPERATION) == XMC_WaitOperation_Enable))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup XMC_EnableECC
+  * @{
+  */
+
+#define XMC_ECCOperation_Disable            ((uint32_t)0x00000000)
+#define XMC_ECCOperation_Enable             ((uint32_t)0x00000040)
+#define IS_XMC_ECC_OPERATION(OPERATION)     (((OPERATION) == XMC_ECCOperation_Disable) || \
+                                             ((OPERATION) == XMC_ECCOperation_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_ECC_Page_Size
+  * @{
+  */
+
+#define XMC_ECCPageSize_256Bytes            ((uint32_t)0x00000000)
+#define XMC_ECCPageSize_512Bytes            ((uint32_t)0x00020000)
+#define XMC_ECCPageSize_1024Bytes           ((uint32_t)0x00040000)
+#define XMC_ECCPageSize_2048Bytes           ((uint32_t)0x00060000)
+#define XMC_ECCPageSize_4096Bytes           ((uint32_t)0x00080000)
+#define XMC_ECCPageSize_8192Bytes           ((uint32_t)0x000A0000)
+#define IS_XMC_ECCPAGE_SIZE(SIZE)           (((SIZE) == XMC_ECCPageSize_256Bytes) || \
+                                             ((SIZE) == XMC_ECCPageSize_512Bytes) || \
+                                             ((SIZE) == XMC_ECCPageSize_1024Bytes) || \
+                                             ((SIZE) == XMC_ECCPageSize_2048Bytes) || \
+                                             ((SIZE) == XMC_ECCPageSize_4096Bytes) || \
+                                             ((SIZE) == XMC_ECCPageSize_8192Bytes))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_TCLR_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_DELAY_CR_TIME(TIME)          ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_TAR_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_DELAY_AR_TIME(TIME)          ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_SETUP_TIME(TIME)             ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Wait_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_OP_TIME(TIME)                ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Hold_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_HOLD_TIME(TIME)              ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_HiZ_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_WRITE_SETUP_TIME(TIME)       ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Interrupt_sources
+  * @{
+  */
+
+#define XMC_INT_RisingEdge                  ((uint32_t)0x00000008)
+#define XMC_INT_Level                       ((uint32_t)0x00000010)
+#define XMC_INT_FallingEdge                 ((uint32_t)0x00000020)
+#define IS_XMC_INT(INT)                     ((((INT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((INT) != 0x00000000))
+#define IS_XMC_GET_INT(INT)                 (((INT) == XMC_INT_RisingEdge) || \
+                                             ((INT) == XMC_INT_Level) || \
+                                             ((INT) == XMC_INT_FallingEdge))
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Flags
+  * @{
+  */
+
+#define XMC_FLAG_RisingEdge                 ((uint32_t)0x00000001)
+#define XMC_FLAG_Level                      ((uint32_t)0x00000002)
+#define XMC_FLAG_FallingEdge                ((uint32_t)0x00000004)
+#define XMC_FLAG_FEMPT                      ((uint32_t)0x00000040)
+#define IS_XMC_GET_FLAG(FLAG)               (((FLAG) == XMC_FLAG_RisingEdge) || \
+                                             ((FLAG) == XMC_FLAG_Level) || \
+                                             ((FLAG) == XMC_FLAG_FallingEdge) || \
+                                             ((FLAG) == XMC_FLAG_FEMPT))
+
+#define IS_XMC_CLEAR_FLAG(FLAG)             ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Exported_Functions
+  * @{
+  */
+void XMC_NANDCmd(uint32_t XMC_Bank, FunctionalState NewState);
+void XMC_PCCARDCmd(FunctionalState NewState);
+void XMC_NANDECCCmd(uint32_t XMC_Bank, FunctionalState NewState);
+uint32_t XMC_GetECC(uint32_t XMC_Bank);
+void XMC_INTConfig(uint32_t XMC_Bank, uint32_t XMC_INT, FunctionalState NewState);
+FlagStatus XMC_GetFlagStatus(uint32_t XMC_Bank, uint32_t XMC_FLAG);
+void XMC_NORSRAMStructInit(XMC_NORSRAMInitType* XMC_NORSRAMInitStruct);
+void XMC_NANDStructInit(XMC_NANDInitType* XMC_NANDInitStruct);
+void XMC_PCCARDStructInit(XMC_PCCARDInitType* XMC_PCCARDInitStruct);
+void XMC_NORSRAMCmd(uint32_t XMC_Bank, FunctionalState NewState);
+void XMC_ClearFlag(uint32_t XMC_Bank, uint32_t XMC_FLAG);
+ITStatus XMC_GetINTStatus(uint32_t XMC_Bank, uint32_t XMC_INT);
+void XMC_ClearINTPendingBit(uint32_t XMC_Bank, uint32_t XMC_INT);  
+void XMC_ExtTimingConfig(uint32_t XMC_SubBank, uint8_t W2W_Timing, uint8_t R2R_Timing);
+void XMC_NORSRAMReset(uint32_t XMC_Bank);
+void XMC_NANDReset(uint32_t XMC_Bank);
+void XMC_PCCARDReset(void);
+void XMC_NORSRAMInit(XMC_NORSRAMInitType* XMC_NORSRAMInitStruct);
+void XMC_NANDInit(XMC_NANDInitType* XMC_NANDInitStruct);
+void XMC_PCCARDInit(XMC_PCCARDInitType* XMC_PCCARDInitStruct);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4XX_XMC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/inc/misc.h

@@ -0,0 +1,208 @@
+/**
+  **************************************************************************
+  * File   : misc.h
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx MISC header file
+  **************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/** @defgroup MISC_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  NVIC Init Structure definition
+  */
+
+typedef struct
+{
+    uint8_t NVIC_IRQChannel;                        /*!< Specifies the IRQ channel to be enabled or disabled.
+                                                       This parameter can be a value of @ref IRQn_Type
+                                                       (For the complete AT32 Devices IRQ Channels list, please
+                                                        refer to at32f4xx.h file) */
+
+    uint8_t NVIC_IRQChannelPreemptionPriority;      /*!< Specifies the pre-emption priority for the IRQ channel
+                                                       specified in NVIC_IRQChannel. This parameter can be a value
+                                                       between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+    uint8_t NVIC_IRQChannelSubPriority;             /*!< Specifies the subpriority level for the IRQ channel specified
+                                                       in NVIC_IRQChannel. This parameter can be a value
+                                                       between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+    FunctionalState NVIC_IRQChannelCmd;             /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                       will be enabled or disabled.
+                                                       This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup NVIC_Priority_Table
+  * @{
+  */
+
+/**
+@code
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  ============================================================================================================================
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
+  ============================================================================================================================
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
+                         |                                   |                             |   4 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
+                         |                                   |                             |   3 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
+                         |                                   |                             |   2 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
+                         |                                   |                             |   1 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
+                         |                                   |                             |   0 bits for subpriority
+  ============================================================================================================================
+@endcode
+*/
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Vector_Table_Base
+  * @{
+  */
+
+#define NVIC_VectTab_RAM                    ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH                  ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB)            (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                             ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup System_Low_Power
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND                   ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP                   ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT                 ((uint8_t)0x02)
+#define IS_NVIC_LP(LP)                      (((LP) == NVIC_LP_SEVONPEND) || \
+                                             ((LP) == NVIC_LP_SLEEPDEEP) || \
+                                             ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup Preemption_Priority_Group
+  * @{
+  */
+
+#define NVIC_PriorityGroup_0                ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+                                                                   4 bits for subpriority */
+#define NVIC_PriorityGroup_1                ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+                                                                   3 bits for subpriority */
+#define NVIC_PriorityGroup_2                ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+                                                                   2 bits for subpriority */
+#define NVIC_PriorityGroup_3                ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+                                                                   1 bits for subpriority */
+#define NVIC_PriorityGroup_4                ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+                                                                   0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP)       (((GROUP) == NVIC_PriorityGroup_0) || \
+                                             ((GROUP) == NVIC_PriorityGroup_1) || \
+                                             ((GROUP) == NVIC_PriorityGroup_2) || \
+                                             ((GROUP) == NVIC_PriorityGroup_3) || \
+                                             ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)       ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)              ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)                      ((OFFSET) < 0x000FFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup SysTick_clock_source
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8         ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK              ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE)       (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                             ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Functions
+  * @{
+  */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_acc.c

@@ -0,0 +1,238 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_acc.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx ACC source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_acc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup ACC
+  * @brief ACC driver modules
+  * @{
+  */
+#if defined (AT32F413xx) || defined (AT32F415xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+
+/** @defgroup ACC_Private_Functions
+  * @{
+  */
+  
+/**
+  * @brief  Stores Calibration Step data in ACC's CTRL1 register.
+  * @param  StepValue:  value to be stored in the ACC's CTRL1 register 					
+  * @retval None
+  */
+void ACC_SetStep(uint8_t StepValue)
+{
+  ACC->CTRL1 |= StepValue<<8;
+}
+
+/**
+  * @brief  Enables the specified ACC Calibration.
+  * @param  ACC_CAL: specifies the ACC CAL sources.
+  *   This parameter can be one of the following values:
+  *     @arg ACC_CAL_HSICAL:  Calibration HSICAL
+  *     @arg ACC_CAL_HSITRIM:  Calibration HSITRIM
+  * @retval None
+  */
+void ACC_CAL_Choose(uint16_t ACC_CAL)
+{
+  ACC->CTRL1 &= ~0x2;
+  
+  ACC->CTRL1 |= ACC_CAL;
+  
+}
+
+/**
+  * @brief  Enables or disables the specified ACC interrupts.
+  * @param  ACC_IT: specifies the ACC interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg ACC_IT_CALRDYIEN:  CALRDY interrupt enable
+  *     @arg ACC_IT_EIEN:  RSLOST error interrupt enable
+  * @param  NewState: new state of the specified ACC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ACC_ITConfig(uint16_t ACC_IT, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    ACC->CTRL1  |= ACC_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    ACC->CTRL1 &= (uint16_t)~ACC_IT;
+  }
+}
+
+/**
+  * @brief  Enters the ACC Calibration mode.
+  * @param  ACC_IT: specifies the ACC interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg ACC_CAL_ON:  CALRDY interrupt enable
+  *     @arg ACC_TRIM_ON:  RSLOST error interrupt enable
+  * @param  NewState: new state of the specified ACC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ACC_EnterCALMode(uint16_t ACC_ON, FunctionalState NewState)
+{
+  ACC->CTRL1 |= ACC_ON;
+}
+/**
+  * @brief  Exits from the ACC Calibration mode.
+  * @param  None
+  * @retval None
+  */
+void ACC_ExitCALMode(void)
+{
+  ACC->CTRL1 &= ~ACC_CAL_Enable;
+}
+
+/**
+  * @brief  Checks whether the specified ACC flag is set or not.
+  * @param  ACC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ACC_FLAG_RSLOST:  Reference Signal Lost
+  *     @arg ACC_FLAG_CALRDY:  Internal high-speed clock calibration ready
+  * @retval The new state of ACC_FLAG (SET or RESET).
+  */
+FlagStatus ACC_GetFlagStatus(uint16_t ACC_FLAG)
+{
+  FlagStatus bitstatus = RESET;  
+  
+  if ((ACC->STS & ACC_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Wtire the value to  ACC C1 register.
+  * @param  ACC_C1_Value
+  * @retval none.
+  */
+void ACC_WriteC1(uint16_t ACC_C1_Value)
+{
+  ACC->C1 = ACC_C1_Value;
+}
+
+/**
+  * @brief  Wtire the value to  ACC C2 register.
+  * @param  ACC_C2_Value
+  * @retval none.
+  */
+void ACC_WriteC2(uint16_t ACC_C2_Value)
+{
+  ACC->C2 = ACC_C2_Value;
+}
+/**
+  * @brief  Wtire the value to  ACC C3 register.
+  * @param  ACC_C3_Value
+  * @retval none.
+  */
+void ACC_WriteC3(uint16_t ACC_C3_Value)
+{
+  ACC->C3 = ACC_C3_Value;
+}
+
+/**
+  * @brief  Returns the current ACC HSITRIM value.
+  * @param  None
+  * @retval 8-bit HSITRIM value.
+  */
+uint8_t ACC_GetHSITRIM(void)
+{
+  return ((uint8_t)((ACC->CTRL2)>>8));
+}
+
+
+/**
+  * @brief  Returns the current ACC HSICAL value.
+  * @param  None
+  * @retval 8-bit HSITRIM value.
+  */
+uint8_t ACC_GetHSICAL(void)
+{
+  return ((uint8_t)(ACC->CTRL2));
+}
+
+/**
+  * @brief  Returns the current ACC C1 value.
+  * @param  None
+  * @retval 16-bit C1 value.
+  */
+uint16_t ACC_ReadC1(void)
+{
+  return ((uint16_t)(ACC->C1));
+}
+
+/**
+  * @brief  Returns the current ACC C2 value.
+  * @param  None
+  * @retval 16-bit C2 value.
+  */
+uint16_t ACC_ReadC2(void)
+{
+  return ((uint16_t)(ACC->C2));
+}
+/**
+  * @brief  Returns the current ACC C3 value.
+  * @param  None
+  * @retval 16-bit C3 value.
+  */
+uint16_t ACC_ReadC3(void)
+{
+  return ((uint16_t)(ACC->C3));
+}
+
+/**
+  * @brief  Checks whether the specified ACC flag is set or not.
+  * @param  ACC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ACC_FLAG_RSLOST:  Reference Signal Lost
+  *     @arg ACC_FLAG_CALRDY:  Internal high-speed clock calibration ready
+  * @retval None.
+  */
+void ACC_ClearFlag(uint16_t ACC_FLAG)            
+{
+  if(ACC_FLAG == ACC_FLAG_CALRDY)
+  {
+    ACC->STS &= ~1;
+  }
+  
+  if(ACC_FLAG == ACC_FLAG_RSLOST)
+  {
+    ACC->STS &= ~2;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* AT32F413xx || AT32F415xx || AT32F403Axx || AT32F407xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

StdPeriph_Driver/src/at32f4xx_bkp.c

@@ -0,0 +1,306 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_bkp.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx BKP source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_bkp.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup BKP
+  * @brief BKP driver modules
+  * @{
+  */
+
+#if defined (AT32F403xx) || defined (AT32F413xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+
+/** @defgroup BKP_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Private_Defines
+  * @{
+  */
+
+/* ------------ BKP registers bit address in the alias region --------------- */
+#define BKP_OFFSET                  (BKP_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ----*/
+
+/* Alias word address of TPAL bit */
+#define CTRL_OFFSET                 (BKP_OFFSET + 0x30)
+#define TPALV_BitPos                0x01
+#define CTRL_TPALV_BBMAP            (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (TPALV_BitPos * 4))
+
+/* Alias word address of TPE bit */
+#define TPEN_BitPos                 0x00
+#define CTRL_TPEN_BBMAP             (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (TPEN_BitPos * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of TPIE bit */
+#define CTRLSTS_OFFSET              (BKP_OFFSET + 0x34)
+#define TPIEN_BitPos                0x02
+#define CTRLSTS_TPIEN_BBMAP         (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TPIEN_BitPos * 4))
+
+/* Alias word address of TIF bit */
+#define TPIF_BitPos                 0x09
+#define CTRLSTS_TPIF_BBMAP          (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TPIF_BitPos * 4))
+
+/* Alias word address of TEF bit */
+#define TPEF_BitPos                 0x08
+#define CTRLSTS_TPEF_BBMAP          (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TPEF_BitPos * 4))
+
+/* ---------------------- BKP registers bit mask ------------------------ */
+
+/* RTCCR register bit mask */
+#define RTCCAL_CAL_MASK             ((uint16_t)0xFF80)
+#define RTCCAL_MASK                 ((uint16_t)0xF07F)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup BKP_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Checks whether the Tamper Pin Event flag is set or not.
+  * @param  None
+  * @retval The new state of the Tamper Pin Event flag (SET or RESET).
+  */
+FlagStatus BKP_GetFlagStatus(void)
+{
+  return (FlagStatus)(*(__IO uint32_t *) CTRLSTS_TPEF_BBMAP);
+}
+
+/**
+  * @brief  Clears Tamper Pin Event pending flag.
+  * @param  None
+  * @retval None
+  */
+void BKP_ClearFlag(void)
+{
+  /* Set CTE bit to clear Tamper Pin Event flag */
+  BKP->CTRLSTS |= BKP_CTRLSTS_CTPEF;
+}
+
+/**
+  * @brief  Checks whether the Tamper Pin Interrupt has occurred or not.
+  * @param  None
+  * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
+  */
+ITStatus BKP_GetIntStatus(void)
+{
+  return (ITStatus)(*(__IO uint32_t *) CTRLSTS_TPIF_BBMAP);
+}
+
+/**
+  * @brief  Clears Tamper Pin Interrupt pending bit.
+  * @param  None
+  * @retval None
+  */
+void BKP_ClearIntPendingBit(void)
+{
+  /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
+  BKP->CTRLSTS |= BKP_CTRLSTS_CTPIF;
+}
+
+/**
+  * @brief  Sets RTC Clock Calibration value.
+  * @param  CalibrationValue: specifies the RTC Clock Calibration value.
+  *   This parameter must be a number between 0 and 0x7F.
+  * @retval None
+  */
+void BKP_SetRTCCalValue(uint8_t CalibrationValue)
+{
+  uint16_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_BKP_CAL_VAL(CalibrationValue));
+  tmpreg = BKP->RTCCAL;
+  /* Clear CAL[6:0] bits */
+  tmpreg &= RTCCAL_CAL_MASK;
+  /* Set CAL[6:0] bits according to CalibrationValue value */
+  tmpreg |= CalibrationValue;
+  /* Store the new value */
+  BKP->RTCCAL = tmpreg;
+}
+
+/**
+  * @brief  Writes user data to the specified Data Backup Register.
+  * @param  BKP_DR: specifies the Data Backup Register.
+  *   This parameter can be BKP_DRx where x:[1, 42]
+  * @param  Data: data to write
+  * @retval None
+  */
+void BKP_WriteBackupReg(uint16_t BKP_DR, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_BKP_DT(BKP_DR));
+
+  tmp = (uint32_t)BKP_BASE;
+  tmp += BKP_DR;
+
+  *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+  * @brief  Reads data from the specified Data Backup Register.
+  * @param  BKP_DR: specifies the Data Backup Register.
+  *   This parameter can be BKP_DRx where x:[1, 42]
+  * @retval The content of the specified Data Backup Register
+  */
+uint16_t BKP_ReadBackupReg(uint16_t BKP_DR)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_BKP_DT(BKP_DR));
+
+  tmp = (uint32_t)BKP_BASE;
+  tmp += BKP_DR;
+
+  return (*(__IO uint16_t *) tmp);
+}
+
+/**
+  * @brief  Deinitializes the BKP peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void BKP_Reset(void)
+{
+  RCC_BackupResetCmd(ENABLE);
+  RCC_BackupResetCmd(DISABLE);
+}
+
+/**
+  * @brief  Configures the Tamper Pin active level.
+  * @param  BKP_TamperPinLevel: specifies the Tamper Pin active level.
+  *   This parameter can be one of the following values:
+  *     @arg BKP_TamperPinLv_H: Tamper pin active on high level
+  *     @arg BKP_TamperPinLv_L: Tamper pin active on low level
+  * @retval None
+  */
+void BKP_TamperPinLvConfig(uint16_t BKP_TamperPinLevel)
+{
+  /* Check the parameters */
+  assert_param(IS_BKP_TAMPER_PIN_LV(BKP_TamperPinLevel));
+  *(__IO uint32_t *) CTRL_TPALV_BBMAP = BKP_TamperPinLevel;
+}
+
+/**
+  * @brief  Enables or disables the Tamper Pin activation.
+  * @param  NewState: new state of the Tamper Pin activation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRL_TPEN_BBMAP = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the Tamper Pin Interrupt.
+  * @param  NewState: new state of the Tamper Pin Interrupt.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void BKP_IntConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRLSTS_TPIEN_BBMAP = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Select the RTC output source to output on the Tamper pin.
+  * @param  BKP_RTCOutputSource: specifies the RTC output source.
+  *   This parameter can be one of the following values:
+  *     @arg BKP_RTCOutput_None: no RTC output on the Tamper pin.
+  *     @arg BKP_RTCOutput_CalClk: output the RTC clock with frequency
+  *                                          divided by 64 on the Tamper pin.
+  *     @arg BKP_RTCOutput_Alarm: output the RTC Alarm pulse signal on
+  *                                     the Tamper pin.
+  *     @arg BKP_RTCOutput_Second: output the RTC Second pulse signal on
+  *                                      the Tamper pin.
+  *     Note: The following two parameter apply only to AT32F403Axx or AT32F407xx
+  *     @arg BKP_RTCOutput_Alarm_Toggle: output the RTC Alarm toggle signal on
+  *                                     the Tamper pin.
+  *     @arg BKP_RTCOutput_Second_Toggle: output the RTC Second toggle signal on
+  *                                      the Tamper pin.
+  * @retval None
+  */
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
+{
+  uint16_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_BKP_RTC_OUTPUT_SEL(BKP_RTCOutputSource));
+  tmpreg = BKP->RTCCAL;
+  /* Clear CCO, ASOE and ASOS bits */
+  tmpreg &= RTCCAL_MASK;
+
+  /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
+  tmpreg |= BKP_RTCOutputSource;
+  /* Store the new value */
+  BKP->RTCCAL = tmpreg;
+}
+
+/**
+  * @}
+  */
+
+#endif /* AT32F403xx || AT32F413xx || AT32F403Axx || AT32F407xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_comp.c

@@ -0,0 +1,444 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_comp.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx COMP source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_comp.h"
+
+/** @addtogroup AT32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup COMP 
+  * @brief COMP driver modules
+  * @{
+  */ 
+
+#if defined (AT32F415xx) || defined (AT32F421xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* CTRLSTS1 register Mask */
+#ifdef AT32F421xx
+#define COMP_CTRLSTS1_CLEAR_MASK              ((uint32_t)0x00039C7C)
+#define COMP_INPINPUT_CLEAR_MASK              ((uint32_t)0x00000180)
+#else
+#define COMP_CTRLSTS1_CLEAR_MASK              ((uint32_t)0x00003F74)
+#define COMP_INPINPUT_CLEAR_MASK              ((uint32_t)0x00000003)
+#endif
+#define COMP_HIGH_PULSE_CLEAR_MASK            ((uint16_t)0x003F) 
+#define COMP_LOW_PULSE_CLEAR_MASK             ((uint16_t)0x003F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup COMP_Private_Functions
+  * @{
+  */
+   
+/**
+  * @brief  Deinitializes COMP peripheral registers to their default reset values.
+  * @note   Deinitialization can't be performed if the COMP configuration is locked.
+  *         To unlock the configuration, perform a system reset.
+  * @param  None
+  * @retval None
+  */
+void COMP_Reset(void)
+{
+  COMP->CTRLSTS1 = ((uint32_t)0x00000080);    /*!< Set COMP_CTRLSTS register to reset value */
+}
+
+/**
+  * @brief  Initializes the COMP peripheral according to the specified parameters
+  *         in COMP_InitStruct
+  * @note   If the selected comparator is locked, initialization can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @note   By default, PA1 is selected as COMP1 non inverting input.
+  *         To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be one of the following values:
+  *            @arg COMP1_Selection: COMP1 selected
+  *            @arg COMP2_Selection: COMP2 selected
+  * @param  COMP_InitStruct: pointer to an COMP_InitType structure that contains 
+  *         the configuration information for the specified COMP peripheral.
+  * @retval None
+  */
+void COMP_Init(uint32_t COMP_Selection, COMP_InitType* COMP_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_INMInput));
+  assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
+  assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutPolarity));
+  assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
+  assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
+
+  /*!< Get the COMP_CTRLSTS register value */
+  tmpreg = COMP->CTRLSTS1;
+
+  /*!< Clear the COMP1SW1, COMPx_IN_SEL, COMPx_OUT_TIM_SEL, COMPx_POL, COMPx_HYST and COMPx_PWR_MODE bits */ 
+  tmpreg &= (uint32_t) ~(COMP_CTRLSTS1_CLEAR_MASK<<COMP_Selection);
+
+  /*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
+  /*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
+  /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
+  /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
+  /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
+  /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */   
+  tmpreg |= (uint32_t)((COMP_InitStruct->COMP_INMInput | COMP_InitStruct->COMP_Output |
+                       COMP_InitStruct->COMP_OutPolarity | COMP_InitStruct->COMP_Hysteresis |
+                       COMP_InitStruct->COMP_Mode)<<COMP_Selection);
+
+  /*!< Write to COMP_CTRLSTS1 register */
+  COMP->CTRLSTS1 = tmpreg;  
+}
+
+/**
+  * @brief  Select the non-inverting input for COMP1/COMP2.
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be one of the following values:
+  *            @arg COMP1_Selection: COMP1 selected
+  *            @arg COMP2_Selection: COMP2 selected
+  * @param  COMP_INPInput: the selected COMP non-inverting input.
+  *         This parameter can be one of the following values:
+  *            @arg COMP_INPInput_00: PA5/PA7 connected to comparator1/2 non-inverting input
+  *            @arg COMP_INPInput_01: PA1/PA3 connected to comparator1/2 non-inverting input
+  *            @arg COMP_INPInput_10: PA0/PA2 connected to comparator1/2 non-inverting input
+  * @retval None
+  */
+void COMP_SelectINPInput(uint32_t COMP_Selection, uint32_t COMP_INPInput)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_COMP_NONINVERTING_INPUT(COMP_INPInput));
+
+#ifdef AT32F421xx
+  /*!< Get the COMP_CTRLSTS register value */
+  tmpreg = COMP->CTRLSTS1;
+#else
+  /*!< Get the COMP_CTRLSTS register value */
+  tmpreg = COMP->CTRLSTS2;
+#endif
+  
+  /*!< Clear the COMPxINPSEL bits */ 
+  tmpreg &= (uint32_t) ~(COMP_INPINPUT_CLEAR_MASK<<COMP_Selection);
+
+  /*!< Set COMPxINPSEL bits according to COMP_InitStruct->COMP_NonInvertingInput value */
+  tmpreg |= (uint32_t)(COMP_INPInput<<COMP_Selection);
+
+#ifdef AT32F421xx
+  /*!< Write to COMP_CTRLSTS2 register */
+  COMP->CTRLSTS1 = tmpreg;  
+#else
+  /*!< Write to COMP_CTRLSTS2 register */
+  COMP->CTRLSTS2 = tmpreg;  
+#endif
+}
+
+/**
+  * @brief  Fills each COMP_InitStruct member with its default value.
+  * @param  COMP_InitStruct: pointer to an COMP_InitType structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void COMP_StructInit(COMP_InitType* COMP_InitStruct)
+{
+  COMP_InitStruct->COMP_INMInput = COMP_INMInput_1_4VREFINT;
+  COMP_InitStruct->COMP_Output = COMP_Output_None;
+  COMP_InitStruct->COMP_OutPolarity = COMP_OutPolarity_NonInverted;
+  COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
+  COMP_InitStruct->COMP_Mode = COMP_Mode_Fast;
+}
+
+/**
+  * @brief  Enable or disable the COMP peripheral.
+  * @note   If the selected comparator is locked, enable/disable can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  COMP_Selection: the selected comparator.
+  *          This parameter can be one of the following values:
+  *            @arg COMP1_Selection: COMP1 selected
+  *            @arg COMP2_Selection: COMP2 selected
+  * @param  NewState: new state of the COMP peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When enabled, the comparator compares the non inverting input with 
+  *         the inverting input and the comparison result is available on comparator output.
+  * @note   When disabled, the comparator doesn't perform comparison and the 
+  *         output level is low.
+  * @retval None
+  */
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected COMP peripheral */
+    COMP->CTRLSTS1 |= (uint32_t) (1<<COMP_Selection);
+  }
+  else
+  {
+    /* Disable the selected COMP peripheral  */
+    COMP->CTRLSTS1 &= (uint32_t)(~((uint32_t)1<<COMP_Selection));
+  }
+}
+
+/**
+  * @brief  Close or Open the SW1 switch.
+  * @note   This switch is solely intended to redirect signals onto high
+  *         impedance input, such as COMP1 non-inverting input (highly resistive switch)
+  * @param  NewState: New state of the analog switch.
+  *          This parameter can be: ENABLE or DISABLE. 
+  * @note   When enabled, the SW1 is closed; PA1 is connected to PA4
+  * @note   When disabled, the SW1 switch is open; PA1 is disconnected from PA4
+  * @retval None
+  */
+void COMP_SwitchCmd(FunctionalState NewState)
+{
+  /* Check the parameter */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Close SW1 switch */
+    COMP->CTRLSTS1 |= (uint32_t) (COMP_CTRLSTS_COMP1SW1);
+  }
+  else
+  {
+    /* Open SW1 switch */
+    COMP->CTRLSTS1 &= (uint32_t)(~COMP_CTRLSTS_COMP1SW1);
+  }
+}
+
+/**
+  * @brief  Return the output level (high or low) of the selected comparator. 
+  * @note   The output level depends on the selected polarity.
+  * @note   If the polarity is not inverted:
+  *          - Comparator output is low when the non-inverting input is at a lower
+  *            voltage than the inverting input
+  *          - Comparator output is high when the non-inverting input is at a higher
+  *            voltage than the inverting input
+  * @note   If the polarity is inverted:
+  *          - Comparator output is high when the non-inverting input is at a lower
+  *            voltage than the inverting input
+  *          - Comparator output is low when the non-inverting input is at a higher
+  *            voltage than the inverting input
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be one of the following values:
+  *            @arg COMP1_Selection: COMP1 selected
+  *            @arg COMP2_Selection: COMP2 selected  
+  * @retval Returns the selected comparator output level: low or high.
+  *       
+  */
+uint32_t COMP_GetOutputState(uint32_t COMP_Selection)
+{
+  uint32_t compout = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  /* Check if selected comparator output is high */
+  if ((COMP->CTRLSTS1 & (COMP_CTRLSTS_COMP1OUT<<COMP_Selection)) != 0)
+  {
+    compout = SET;
+  }
+  else
+  {
+    compout = RESET;
+  }
+
+  /* Return the comparator output level */
+  return (uint32_t)(compout);
+}
+
+#ifdef AT32F415
+/**
+  * @brief  Enables or disables the window mode.
+  * @note   In window mode, COMP1 and COMP2 non inverting inputs are connected
+  *         together and only COMP1 non inverting input (PA1) can be used.
+  * @param  NewState: new state of the window mode.
+  *          This parameter can be :
+  *           @arg ENABLE: COMP1 and COMP2 non inverting inputs are connected together.
+  *           @arg DISABLE: OMP1 and COMP2 non inverting inputs are disconnected.
+  * @retval None
+  */
+void COMP_WindowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the window mode */
+    COMP->CTRLSTS1 |= (uint32_t)COMP_CTRLSTS_WNDWEN;
+  }
+  else
+  {
+    /* Disable the window mode */
+    COMP->CTRLSTS1 &= (uint32_t)(~COMP_CTRLSTS_WNDWEN);
+  }
+}
+#endif
+
+/**
+  * @brief  Lock the selected comparator (COMP1/COMP2) configuration.
+  * @note   Locking the configuration means that all control bits are read-only.
+  *         To unlock the comparator configuration, perform a system reset.
+  * @param  COMP_Selection: selects the comparator to be locked 
+  *          This parameter can be a value of the following values:
+  *            @arg COMP1_Selection: COMP1 configuration is locked.
+  *            @arg COMP2_Selection: COMP2 configuration is locked.  
+  * @retval None
+  */
+void COMP_LockConfig(uint32_t COMP_Selection)
+{
+  /* Check the parameter */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  /* Set the lock bit corresponding to selected comparator */
+  COMP->CTRLSTS1 |= (uint32_t) (COMP_CTRLSTS_COMP1LOCK<<COMP_Selection);
+}
+
+#ifdef AT32F421xx
+/**
+  * @brief  Configure COMP Glitch Filter.
+  * @note   G_FILTER_EN, HIGH_PULSE and LOW_PULSE registers will
+  *         act on both COMP1 and COMP2.
+  * @param  COMP_HighPulseCnt: COMP High Pulse Count.
+  *         This parameter must be a value between 0x00 and 0x3F  
+  * @param  COMP_LowPulseCnt: COMP Low Pulse Count.
+  *         This parameter must be a value between 0x00 and 0x3F  
+  * @param  NewState: new state of the Glitch Filter.
+  *          This parameter can be :
+  *           @arg ENABLE: COMP1 and COMP2 turn on glitch filter.
+  *           @arg DISABLE: COMP1 and COMP2 turn off glitch filter.
+  * @retval None
+  */
+void COMP_FilterConfig(uint16_t COMP_HighPulseCnt, uint16_t COMP_LowPulseCnt, FunctionalState NewState)
+{
+  uint16_t tmphp = 0;
+  uint16_t tmplp = 0;
+  /* Check the parameters */
+  assert_param(IS_COMP_HighPulseCnt(COMP_HighPulseCnt));
+  assert_param(IS_COMP_LowPulseCnt(COMP_LowPulseCnt));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the glitch filter */
+    COMP->G_FILTER_EN |= (uint16_t)COMP_G_FILTER_EN_GFE;
+    
+    tmphp = COMP->HIGH_PULSE;
+    tmplp = COMP->LOW_PULSE;
+    
+    /* Reset the H_PULSE_CNT and L_PULSE_CNT Bits */
+    tmphp &= ~COMP_HIGH_PULSE_CLEAR_MASK;
+    tmplp &= ~COMP_LOW_PULSE_CLEAR_MASK;
+    
+    /* Set the H_PULSE_CNT and L_PULSE_CNT Bits */
+    tmphp |= COMP_HighPulseCnt;
+    tmplp |= COMP_LowPulseCnt;
+    
+    /* Write to COMP HIGH_PULSE and LOW_PULSE */
+    COMP->HIGH_PULSE = tmphp;
+    COMP->LOW_PULSE = tmplp;
+  }
+  else
+  {
+    /* Disable the glitch filter */
+    COMP->G_FILTER_EN &= (uint16_t)(~COMP_G_FILTER_EN_GFE);
+    
+    /* Reset the H_PULSE_CNT and L_PULSE_CNT Bits */
+    COMP->HIGH_PULSE &= ~COMP_HIGH_PULSE_CLEAR_MASK;
+    COMP->LOW_PULSE &= ~COMP_LOW_PULSE_CLEAR_MASK;
+  }
+}
+
+/**
+  * @brief  Configure COMP blanking source.
+  * @param  Blank_Selection: COMP blanking source.
+  *         This parameter can be one of the following values:
+  *            @arg COMP_Blanking_None: No blanking source
+  *            @arg COMP_Blanking_TMR1OC4: TMR1OC4 as the blanking source  
+  *            @arg COMP_Blanking_TMR3OC3: TMR3OC3 as the blanking source 
+  *            @arg COMP_Blanking_TMR15OC2: TMR15OC2 as the blanking source   
+  *            @arg COMP_Blanking_TMR15OC1: TMR15OC1 as the blanking source 
+  * @retval None
+  */
+void COMP_BlankingConfig(uint32_t Blank_Selection)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_COMP_BLANKING(Blank_Selection));
+
+  /*!< Get the COMP_CTRLSTS register value */
+  tmpreg = COMP->CTRLSTS1;
+
+  /*!< Clear the COMPBLANKING bits */ 
+  tmpreg &= (uint32_t) ~COMP_CTRLSTS_COMP1BLANKING;
+
+  /*!< Set COMPBLANKING bits according to Blank_Selection value */
+  tmpreg |= (uint32_t)(Blank_Selection);
+
+  /*!< Write to COMP_CTRLSTS1 register */
+  COMP->CTRLSTS1 = tmpreg; 
+}
+
+/**
+  * @brief  Configure COMP internal equipartition voltage bridge.
+  * @param  SCAL_BRG: COMP SCAL&BRG configure.
+  *         This parameter can be one of the following values:
+  *            @arg COMP_SCAL_BRG_00: VREFINT = 3/4 VREFINT = 1/2 VREFINT = 1/4 VREFINT = 0V
+  *            @arg COMP_SCAL_BRG_10: VREFINT = 3/4 VREFINT = 1/2 VREFINT = 1/4 VREFINT = 1.2V  
+  *            @arg COMP_SCAL_BRG_11: VREFINT = 1.2V, 3/4 VREFINT = 0.9V, 1/2 VREFINT = 0.6V, 1/4 VREFINT = 0.3V 
+  * @retval None
+  */
+void COMP_SCAL_BRGConfig(uint32_t SCAL_BRG)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_COMP_SCAL_BRG(SCAL_BRG));
+
+  /*!< Get the COMP_CTRLSTS register value */
+  tmpreg = COMP->CTRLSTS1;
+
+  /*!< Clear the COMPBLANKING bits */ 
+  tmpreg &= (uint32_t) ~(COMP_CTRLSTS_COMP1SCALEN | COMP_CTRLSTS_COMP1BRGEN);
+
+  /*!< Set COMPBLANKING bits according to Blank_Selection value */
+  tmpreg |= (uint32_t)(SCAL_BRG);
+
+  /*!< Write to COMP_CTRLSTS1 register */
+  COMP->CTRLSTS1 = tmpreg; 
+}
+#endif
+
+/**
+  * @}
+  */
+
+#endif /* AT32F415xx || AT32F421xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

StdPeriph_Driver/src/at32f4xx_crc.c

@@ -0,0 +1,150 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_crc.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx CRC source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_crc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRC
+  * @brief CRC driver modules
+  * @{
+  */
+
+/** @defgroup CRC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Stores a 8-bit data in the Independent Data(ID) register.
+  * @param  IDValue: 8-bit value to be stored in the ID register
+  * @retval None
+  */
+void CRC_SetIDTReg(uint8_t IDValue)
+{
+  CRC->IDT = IDValue;
+}
+
+/**
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+  * @param  None
+  * @retval 8-bit value of the ID register
+  */
+uint8_t CRC_GetIDTReg(void)
+{
+  return (CRC->IDT);
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
+  * @param  BufferLength: length of the buffer to be computed
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalculateBlkCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+
+  for(index = 0; index < BufferLength; index++)
+  {
+    CRC->DT = pBuffer[index];
+  }
+
+  return (CRC->DT);
+}
+
+/**
+  * @brief  Returns the current CRC value.
+  * @param  None
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_GetCRC(void)
+{
+  return (CRC->DT);
+}
+
+/**
+  * @brief  Resets the CRC Data register (DR).
+  * @param  None
+  * @retval None
+  */
+void CRC_ResetDT(void)
+{
+  /* Reset CRC generator */
+  CRC->CTRL = CRC_CTRL_RST;
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
+  * @param  Data: data word(32-bit) to compute its CRC
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalculateCRC(uint32_t Data)
+{
+  CRC->DT = Data;
+
+  return (CRC->DT);
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_dac.c

@@ -0,0 +1,419 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_dac.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx DAC source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_dac.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DAC
+  * @brief DAC driver modules
+  * @{
+  */
+#if defined (AT32F403xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+
+/** @defgroup DAC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Defines
+  * @{
+  */
+
+/* CTRL register Mask */
+#define CTRL_CLEAR_MSK                  ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET                 ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RST                 ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET                  ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET                  ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET                  ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define ODT_OFFSET                      ((uint32_t)0x0000002C)
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Functions
+  * @{
+  */
+
+
+/**
+  * @brief  Set the specified data holding register value for dual channel
+  *   DAC.
+  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_Right: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_Left: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_Right: 12bit right data alignment selected
+  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data
+  *   holding register.
+  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data
+  *   holding register.
+  * @retval None
+  */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+  uint32_t data = 0, tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+
+  /* Calculate and set dual DAC data holding register value */
+  if (DAC_Align == DAC_Align_8b_Right)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1;
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12RD_OFFSET + DAC_Align;
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+
+  tmp = (uint32_t) DAC_BASE ;
+  tmp += ODT_OFFSET + ((uint32_t)DAC_Channel >> 2);
+
+  /* Returns the DAC channel data output register value */
+  return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void DAC_Reset(void)
+{
+  /* Enable DAC reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_DAC, ENABLE);
+  /* Release DAC from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_DAC, DISABLE);
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel software trigger.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel software trigger.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_SoftwareTriggerCtrl(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for the selected DAC channel */
+    DAC->SWTRG |= (uint32_t)DAC_SWTRG_SWTRG1 << (DAC_Channel >> 4);
+  }
+  else
+  {
+    /* Disable software trigger for the selected DAC channel */
+    DAC->SWTRG &= ~((uint32_t)DAC_SWTRG_SWTRG1 << (DAC_Channel >> 4));
+  }
+}
+
+/**
+  * @brief  Enables or disables simultaneously the two DAC channels software
+  *   triggers.
+  * @param  NewState: new state of the DAC channels software triggers.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DualSoftwareTriggerCtrl(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for both DAC channels */
+    DAC->SWTRG |= DUAL_SWTRIG_SET ;
+  }
+  else
+  {
+    /* Disable software trigger for both DAC channels */
+    DAC->SWTRG &= DUAL_SWTRIG_RST;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_Wave: Specifies the wave type to enable or disable.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Wave_Noise: noise wave generation
+  *     @arg DAC_Wave_Triangle: triangle wave generation
+  * @param  NewState: new state of the selected DAC channel wave generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_WaveGenerationCtrl(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_WAVE(DAC_Wave));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected wave generation for the selected DAC channel */
+    DAC->CTRL |= DAC_Wave << DAC_Channel;
+  }
+  else
+  {
+    /* Disable the selected wave generation for the selected DAC channel */
+    DAC->CTRL &= ~(DAC_Wave << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel1.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_Right: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_Left: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_Right: 12bit right data alignment selected
+  * @param  Data : Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12R1_OFFSET + DAC_Align;
+
+  /* Set the DAC channel1 selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel2.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_Right: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_Left: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_Right: 12bit right data alignment selected
+  * @param  Data : Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12R2_OFFSET + DAC_Align;
+
+  /* Set the DAC channel2 selected data holding register */
+  *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+  * @brief  Initializes the DAC peripheral according to the specified
+  *         parameters in the DAC_InitStruct.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_InitStruct: pointer to a DAC_InitType structure that
+  *        contains the configuration information for the specified DAC channel.
+  * @retval None
+  */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitType* DAC_InitStruct)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+  /*---------------------------- DAC CTRL Configuration --------------------------*/
+  /* Get the DAC CTRL value */
+  tmpreg1 = DAC->CTRL;
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(CTRL_CLEAR_MSK << DAC_Channel);
+  /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+     mask/amplitude for wave generation */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  /* Set WAVEx bits according to DAC_WaveGeneration value */
+  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
+  /* Set BOFFx bit according to DAC_OutputBuffer value */
+  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
+  /* Calculate CTRL register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << DAC_Channel;
+  /* Write to DAC CTRL */
+  DAC->CTRL = tmpreg1;
+}
+
+/**
+  * @brief  Fills each DAC_InitStruct member with its default value.
+  * @param  DAC_InitStruct : pointer to a DAC_InitType structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DAC_StructInit(DAC_InitType* DAC_InitStruct)
+{
+  /*--------------- Reset DAC init structure parameters values -----------------*/
+  /* Initialize the DAC_Trigger member */
+  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+  /* Initialize the DAC_WaveGeneration member */
+  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmsk_Bit0;
+  /* Initialize the DAC_OutputBuffer member */
+  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the DAC channel.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_Ctrl(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel */
+    DAC->CTRL |= (DAC_CTRL_EN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel */
+    DAC->CTRL &= ~(DAC_CTRL_EN1 << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel DMA request.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel DMA request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DMACtrl(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel DMA request */
+    DAC->CTRL |= (DAC_CTRL_DMAEN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel DMA request */
+    DAC->CTRL &= ~(DAC_CTRL_DMAEN1 << DAC_Channel);
+  }
+}
+/**
+  * @}
+  */
+
+#endif /* AT32F403xx || AT32F403Axx || AT32F407xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_dbgmcu.c

@@ -0,0 +1,149 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_dbgmcu.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx MCUDBG source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_dbgmcu.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup MCUDBG
+  * @brief MCUDBG driver modules
+  * @{
+  */
+
+/** @defgroup MCUDBG_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MCUDBG_Private_Defines
+  * @{
+  */
+
+#define IDCODE_DEVID_MASK           ((uint32_t)0x00000FFF)
+/**
+  * @}
+  */
+
+/** @defgroup MCUDBG_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MCUDBG_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MCUDBG_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MCUDBG_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @param  None
+  * @retval Device revision identifier
+  */
+uint32_t MCUDBG_GetRevID(void)
+{
+  return(MCUDBG->IDCR >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @param  None
+  * @retval Device identifier
+  */
+uint32_t MCUDBG_GetDevID(void)
+{
+  return(MCUDBG->IDCR & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Configures the specified peripheral and low power mode behavior
+  *   when the MCU under Debug mode.
+  * @param  MCUDBG_Periph: specifies the peripheral and low power mode.
+  *   This parameter can be any combination of the following values:
+  *     @arg MCUDBG_SLEEP: Keep debugger connection during SLEEP mode
+  *     @arg MCUDBG_STOP: Keep debugger connection during STOP mode
+  *     @arg MCUDBG_STANDBY: Keep debugger connection during STANDBY mode
+  *     @arg MCUDBG_IWDG_STOP: Debug IWDG stopped when Core is halted
+  *     @arg MCUDBG_WWDG_STOP: Debug WWDG stopped when Core is halted
+  *     @arg MCUDBG_TMR1_STOP: TMR1 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR2_STOP: TMR2 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR3_STOP: TMR3 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR4_STOP: TMR4 counter stopped when Core is halted
+  *     @arg MCUDBG_CAN1_STOP: Debug CAN1 stopped when Core is halted
+  *     @arg MCUDBG_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
+  *     @arg MCUDBG_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
+  *     @arg MCUDBG_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
+  *     @arg MCUDBG_TMR5_STOP: TMR5 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR6_STOP: TMR6 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR7_STOP: TMR7 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR8_STOP: TMR8 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR15_STOP: TMR15 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR9_STOP: TMR9 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR10_STOP: TMR10 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR11_STOP: TMR11 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR12_STOP: TMR12 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR13_STOP: TMR13 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR14_STOP: TMR14 counter stopped when Core is halted
+  * @param  NewState: new state of the specified peripheral in Debug mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void MCUDBG_PeriphDebugModeConfig(uint32_t MCUDBG_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_MCUDBG_PERIPH(MCUDBG_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    MCUDBG->CTRL |= MCUDBG_Periph;
+  }
+  else
+  {
+    MCUDBG->CTRL &= ~MCUDBG_Periph;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_dma.c

@@ -0,0 +1,769 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_dma.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx DMA source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_dma.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DMA
+  * @brief DMA driver modules
+  * @{
+  */
+
+/** @defgroup DMA_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_Defines
+  * @{
+  */
+
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_CHANNEL1_INT_MASK      ((uint32_t)(DMA_ISTS_GIF1 | DMA_ISTS_TCIF1 | DMA_ISTS_HTIF1 | DMA_ISTS_ERRIF1))
+#define DMA1_CHANNEL2_INT_MASK      ((uint32_t)(DMA_ISTS_GIF2 | DMA_ISTS_TCIF2 | DMA_ISTS_HTIF2 | DMA_ISTS_ERRIF2))
+#define DMA1_CHANNEL3_INT_MASK      ((uint32_t)(DMA_ISTS_GIF3 | DMA_ISTS_TCIF3 | DMA_ISTS_HTIF3 | DMA_ISTS_ERRIF3))
+#define DMA1_CHANNEL4_INT_MASK      ((uint32_t)(DMA_ISTS_GIF4 | DMA_ISTS_TCIF4 | DMA_ISTS_HTIF4 | DMA_ISTS_ERRIF4))
+#define DMA1_CHANNEL5_INT_MASK      ((uint32_t)(DMA_ISTS_GIF5 | DMA_ISTS_TCIF5 | DMA_ISTS_HTIF5 | DMA_ISTS_ERRIF5))
+#define DMA1_CHANNEL6_INT_MASK      ((uint32_t)(DMA_ISTS_GIF6 | DMA_ISTS_TCIF6 | DMA_ISTS_HTIF6 | DMA_ISTS_ERRIF6))
+#define DMA1_CHANNEL7_INT_MASK      ((uint32_t)(DMA_ISTS_GIF7 | DMA_ISTS_TCIF7 | DMA_ISTS_HTIF7 | DMA_ISTS_ERRIF7))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_CHANNEL1_INT_MASK      ((uint32_t)(DMA_ISTS_GIF1 | DMA_ISTS_TCIF1 | DMA_ISTS_HTIF1 | DMA_ISTS_ERRIF1))
+#define DMA2_CHANNEL2_INT_MASK      ((uint32_t)(DMA_ISTS_GIF2 | DMA_ISTS_TCIF2 | DMA_ISTS_HTIF2 | DMA_ISTS_ERRIF2))
+#define DMA2_CHANNEL3_INT_MASK      ((uint32_t)(DMA_ISTS_GIF3 | DMA_ISTS_TCIF3 | DMA_ISTS_HTIF3 | DMA_ISTS_ERRIF3))
+#define DMA2_CHANNEL4_INT_MASK      ((uint32_t)(DMA_ISTS_GIF4 | DMA_ISTS_TCIF4 | DMA_ISTS_HTIF4 | DMA_ISTS_ERRIF4))
+#define DMA2_CHANNEL5_INT_MASK      ((uint32_t)(DMA_ISTS_GIF5 | DMA_ISTS_TCIF5 | DMA_ISTS_HTIF5 | DMA_ISTS_ERRIF5))
+
+/* DMA2 FLAG mask */
+#define FLAG_Mask                   ((uint32_t)0x10000000)
+
+/* DMA registers Masks */
+#define CHCTRL_CLEAR_MASK           ((uint32_t)0xFFFF800F)
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the number of data units in the current DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DataNumber: The number of data units in the current DMAy Channelx
+  *         transfer.
+  * @note   This function can only be used when the DMAy_Channelx is disabled.
+  * @retval None.
+  */
+void DMA_SetCurrDataCounter(DMA_Channel_Type* DMAy_Channelx, uint16_t DataNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+  /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->TCNT = DataNumber;
+}
+
+/**
+  * @brief  Returns the number of remaining data units in the current
+  *         DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @retval The number of remaining data units in the current DMAy Channelx
+  *         transfer.
+  */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_Type* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  /* Return the number of remaining data units for DMAy Channelx */
+  return ((uint16_t)(DMAy_Channelx->TCNT));
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx flag is set or not.
+  * @param  DMAy_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *     @arg DMA1_FLAG_ERR1: DMA1 Channel1 transfer error flag.
+  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *     @arg DMA1_FLAG_ERR2: DMA1 Channel2 transfer error flag.
+  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *     @arg DMA1_FLAG_ERR3: DMA1 Channel3 transfer error flag.
+  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *     @arg DMA1_FLAG_ERR4: DMA1 Channel4 transfer error flag.
+  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *     @arg DMA1_FLAG_ERR5: DMA1 Channel5 transfer error flag.
+  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+  *     @arg DMA1_FLAG_ERR6: DMA1 Channel6 transfer error flag.
+  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+  *     @arg DMA1_FLAG_ERR7: DMA1 Channel7 transfer error flag.
+  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+  *     @arg DMA2_FLAG_ERR1: DMA2 Channel1 transfer error flag.
+  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+  *     @arg DMA2_FLAG_ERR2: DMA2 Channel2 transfer error flag.
+  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+  *     @arg DMA2_FLAG_ERR3: DMA2 Channel3 transfer error flag.
+  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+  *     @arg DMA2_FLAG_ERR4: DMA2 Channel4 transfer error flag.
+  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+  *     @arg DMA2_FLAG_ERR5: DMA2 Channel5 transfer error flag.
+  * @retval The new state of DMAy_FLAG (SET or RESET).
+  */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
+
+  /* Calculate the used DMAy */
+#if !defined (AT32F421xx)
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Get DMA2 ISR register value */
+    tmpreg = DMA2->ISTS ;
+  }
+  else
+#endif
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISTS ;
+  }
+
+  /* Check the status of the specified DMAy flag */
+  if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+  {
+    /* DMAy_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_FLAG is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the DMAy_FLAG status */
+  return  bitstatus;
+}
+
+
+/**
+  * @brief  Initializes the DMAy Channelx according to the specified
+  *         parameters in the DMA_InitStruct.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DMA_InitStruct: pointer to a DMA_InitType structure that
+  *         contains the configuration information for the specified DMA Channel.
+  * @retval None
+  */
+void DMA_Init(DMA_Channel_Type* DMAy_Channelx, DMA_InitType* DMA_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_Direction));
+  assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_WIDTH(DMA_InitStruct->DMA_PeripheralDataWidth));
+  assert_param(IS_DMA_MEMORY_DATA_WIDTH(DMA_InitStruct->DMA_MemoryDataWidth));
+  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+  assert_param(IS_DMA_MTOM_STATE(DMA_InitStruct->DMA_MTOM));
+
+  /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
+  /* Get the DMAy_Channelx CCR value */
+  tmpreg = DMAy_Channelx->CHCTRL;
+  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+  tmpreg &= CHCTRL_CLEAR_MASK;
+  /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+  /* Set DIR bit according to DMA_DIR value */
+  /* Set CIRC bit according to DMA_Mode value */
+  /* Set PINC bit according to DMA_PeripheralInc value */
+  /* Set MINC bit according to DMA_MemoryInc value */
+  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+  /* Set MSIZE bits according to DMA_MemoryDataSize value */
+  /* Set PL bits according to DMA_Priority value */
+  /* Set the MEM2MEM bit according to DMA_M2M value */
+  tmpreg |= DMA_InitStruct->DMA_Direction | DMA_InitStruct->DMA_Mode |
+            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+            DMA_InitStruct->DMA_PeripheralDataWidth | DMA_InitStruct->DMA_MemoryDataWidth |
+            DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_MTOM;
+
+  /* Write to DMAy Channelx CCR */
+  DMAy_Channelx->CHCTRL = tmpreg;
+
+  /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->TCNT = DMA_InitStruct->DMA_BufferSize;
+
+  /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
+  /* Write to DMAy Channelx CPAR */
+  DMAy_Channelx->CPBA = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+  /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
+  /* Write to DMAy Channelx CMAR */
+  DMAy_Channelx->CMBA = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+  * @brief  Initializes the DMAy flexible function according to the specified
+  *         parameters.
+  * @param  Flex_Channelx: where x can be 1 to 7 for DMA1 or DMA2.
+  * @param  Hardware_ID: Every peripheral have specified Hardware_ID.
+  * @retval None
+  */
+void DMA_Flexible_Config(DMA_Type* DMAx,uint8_t Flex_Channelx,uint8_t Hardware_ID)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_CHANNELS(Flex_Channelx));	
+  assert_param(IS_DMA_ALL_HARDWARE_ID(Hardware_ID));		
+	/* Initialize the DMA flexible function */
+  if((DMAx->DMA_SRC_SEL1 & DMA_FLEX_FUNCTION_EN) != SET)
+  {
+	  DMAx->DMA_SRC_SEL1 &= (uint32_t)(~DMA_FLEX_FUNCTION_EN);
+	  DMAx->DMA_SRC_SEL1 |= (uint32_t)(DMA_FLEX_FUNCTION_EN);
+  }
+	/* Set the Hardware_ID for DMA_Channel */
+	if(Flex_Channelx == Flex_Channel1)/* channel1 */
+	{ 
+		DMAx->DMA_SRC_SEL0 &= (uint32_t)(~0xFF);
+		DMAx->DMA_SRC_SEL0 |= (uint32_t)(Hardware_ID);
+	}
+	else if(Flex_Channelx == Flex_Channel2)/* channel2 */
+	{
+		DMAx->DMA_SRC_SEL0 &= (uint32_t)(~(0xFF<<8));
+		DMAx->DMA_SRC_SEL0 |= (uint32_t)((Hardware_ID<<8));
+	}
+	else if(Flex_Channelx == Flex_Channel3)/* channel3 */
+	{
+		DMAx->DMA_SRC_SEL0 &= (uint32_t)(~(0xFF<<16));
+		DMAx->DMA_SRC_SEL0 |= (uint32_t)((Hardware_ID<<16));		
+	}
+	else if(Flex_Channelx == Flex_Channel4)/* channel5 */
+	{
+		DMAx->DMA_SRC_SEL0 &= (uint32_t)(~((~(uint32_t)(0x00))<<24));
+		DMAx->DMA_SRC_SEL0 |= (uint32_t)((Hardware_ID<<24));			
+	}	
+	else if(Flex_Channelx == Flex_Channel5)/* channel5 */
+	{
+		DMAx->DMA_SRC_SEL1 &= (uint32_t)(~0xFF);
+		DMAx->DMA_SRC_SEL1 |= (uint32_t)(Hardware_ID);		
+	}	
+	else if(Flex_Channelx == Flex_Channel6)/* channel6 */
+	{
+		DMAx->DMA_SRC_SEL1 &= (uint32_t)(~(0xFF<<8));
+		DMAx->DMA_SRC_SEL1 |= (uint32_t)((Hardware_ID<<8));		
+	}	
+	else if(Flex_Channelx == Flex_Channel7)/* channel7 */
+	{
+		DMAx->DMA_SRC_SEL1 &= (uint32_t)(~(0xFF<<16));
+		DMAx->DMA_SRC_SEL1 |= (uint32_t)((Hardware_ID<<16));		
+	}
+}
+
+/**
+  * @brief  Fills each DMA_InitStruct member with its default value.
+  * @param  DMA_InitStruct : pointer to a DMA_InitType structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DMA_DefaultInitParaConfig(DMA_InitType* DMA_InitStruct)
+{
+  /*-------------- Reset DMA init structure parameters values ------------------*/
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+  /* Initialize the DMA_MemoryBaseAddr member */
+  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+  /* Initialize the DMA_DIR member */
+  DMA_InitStruct->DMA_Direction = DMA_DIR_PERIPHERALSRC;
+  /* Initialize the DMA_BufferSize member */
+  DMA_InitStruct->DMA_BufferSize = 0;
+  /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStruct->DMA_PeripheralInc = DMA_PERIPHERALINC_DISABLE;
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStruct->DMA_MemoryInc = DMA_MEMORYINC_DISABLE;
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStruct->DMA_PeripheralDataWidth = DMA_PERIPHERALDATAWIDTH_BYTE;
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStruct->DMA_MemoryDataWidth = DMA_MEMORYDATAWIDTH_BYTE;
+  /* Initialize the DMA_Mode member */
+  DMA_InitStruct->DMA_Mode = DMA_MODE_NORMAL;
+  /* Initialize the DMA_Priority member */
+  DMA_InitStruct->DMA_Priority = DMA_PRIORITY_LOW;
+  /* Initialize the DMA_M2M member */
+  DMA_InitStruct->DMA_MTOM = DMA_MEMTOMEM_DISABLE;
+}
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  NewState: new state of the DMAy Channelx.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_ChannelEnable(DMA_Channel_Type* DMAy_Channelx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMAy Channelx */
+    DMAy_Channelx->CHCTRL |= DMA_CHCTRL1_CHEN;
+  }
+  else
+  {
+    /* Disable the selected DMAy Channelx */
+    DMAy_Channelx->CHCTRL &= (uint16_t)(~DMA_CHCTRL1_CHEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx interrupts.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DMA_INT: specifies the DMA interrupts sources to be enabled
+  *   or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg DMA_INT_TC:  Transfer complete interrupt mask
+  *     @arg DMA_INT_HT:  Half transfer interrupt mask
+  *     @arg DMA_INT_ERR:  Transfer error interrupt mask
+  * @param  NewState: new state of the specified DMA interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_INTConfig(DMA_Channel_Type* DMAy_Channelx, uint32_t DMA_INT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_CONFIG_INT(DMA_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA interrupts */
+    DMAy_Channelx->CHCTRL |= DMA_INT;
+  }
+  else
+  {
+    /* Disable the selected DMA interrupts */
+    DMAy_Channelx->CHCTRL &= ~DMA_INT;
+  }
+}
+
+
+
+/**
+  * @brief  Clears the DMAy Channelx's pending flags.
+  * @param  DMAy_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination (for the same DMA) of the following values:
+  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *     @arg DMA1_FLAG_ERR1: DMA1 Channel1 transfer error flag.
+  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *     @arg DMA1_FLAG_ERR2: DMA1 Channel2 transfer error flag.
+  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *     @arg DMA1_FLAG_ERR3: DMA1 Channel3 transfer error flag.
+  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *     @arg DMA1_FLAG_ERR4: DMA1 Channel4 transfer error flag.
+  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *     @arg DMA1_FLAG_ERR5: DMA1 Channel5 transfer error flag.
+  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+  *     @arg DMA1_FLAG_ERR6: DMA1 Channel6 transfer error flag.
+  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+  *     @arg DMA1_FLAG_ERR7: DMA1 Channel7 transfer error flag.
+  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+  *     @arg DMA2_FLAG_ERR1: DMA2 Channel1 transfer error flag.
+  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+  *     @arg DMA2_FLAG_ERR2: DMA2 Channel2 transfer error flag.
+  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+  *     @arg DMA2_FLAG_ERR3: DMA2 Channel3 transfer error flag.
+  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+  *     @arg DMA2_FLAG_ERR4: DMA2 Channel4 transfer error flag.
+  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+  *     @arg DMA2_FLAG_ERR5: DMA2 Channel5 transfer error flag.
+  * @retval None
+  */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
+
+  /* Calculate the used DMAy */
+#if !defined (AT32F421xx)
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Clear the selected DMAy flags */
+    DMA2->ICLR = DMAy_FLAG;
+  }
+  else
+#endif
+  {
+    /* Clear the selected DMAy flags */
+    DMA1->ICLR = DMAy_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
+  * @param  DMAy_INT: specifies the DMAy interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg DMA1_INT_GL1: DMA1 Channel1 global interrupt.
+  *     @arg DMA1_INT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *     @arg DMA1_INT_HT1: DMA1 Channel1 half transfer interrupt.
+  *     @arg DMA1_INT_ERR1: DMA1 Channel1 transfer error interrupt.
+  *     @arg DMA1_INT_GL2: DMA1 Channel2 global interrupt.
+  *     @arg DMA1_INT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *     @arg DMA1_INT_HT2: DMA1 Channel2 half transfer interrupt.
+  *     @arg DMA1_INT_ERR2: DMA1 Channel2 transfer error interrupt.
+  *     @arg DMA1_INT_GL3: DMA1 Channel3 global interrupt.
+  *     @arg DMA1_INT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *     @arg DMA1_INT_HT3: DMA1 Channel3 half transfer interrupt.
+  *     @arg DMA1_INT_ERR3: DMA1 Channel3 transfer error interrupt.
+  *     @arg DMA1_INT_GL4: DMA1 Channel4 global interrupt.
+  *     @arg DMA1_INT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *     @arg DMA1_INT_HT4: DMA1 Channel4 half transfer interrupt.
+  *     @arg DMA1_INT_ERR4: DMA1 Channel4 transfer error interrupt.
+  *     @arg DMA1_INT_GL5: DMA1 Channel5 global interrupt.
+  *     @arg DMA1_INT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *     @arg DMA1_INT_HT5: DMA1 Channel5 half transfer interrupt.
+  *     @arg DMA1_INT_ERR5: DMA1 Channel5 transfer error interrupt.
+  *     @arg DMA1_INT_GL6: DMA1 Channel6 global interrupt.
+  *     @arg DMA1_INT_TC6: DMA1 Channel6 transfer complete interrupt.
+  *     @arg DMA1_INT_HT6: DMA1 Channel6 half transfer interrupt.
+  *     @arg DMA1_INT_ERR6: DMA1 Channel6 transfer error interrupt.
+  *     @arg DMA1_INT_GL7: DMA1 Channel7 global interrupt.
+  *     @arg DMA1_INT_TC7: DMA1 Channel7 transfer complete interrupt.
+  *     @arg DMA1_INT_HT7: DMA1 Channel7 half transfer interrupt.
+  *     @arg DMA1_INT_ERR7: DMA1 Channel7 transfer error interrupt.
+  *     @arg DMA2_INT_GL1: DMA2 Channel1 global interrupt.
+  *     @arg DMA2_INT_TC1: DMA2 Channel1 transfer complete interrupt.
+  *     @arg DMA2_INT_HT1: DMA2 Channel1 half transfer interrupt.
+  *     @arg DMA2_INT_ERR1: DMA2 Channel1 transfer error interrupt.
+  *     @arg DMA2_INT_GL2: DMA2 Channel2 global interrupt.
+  *     @arg DMA2_INT_TC2: DMA2 Channel2 transfer complete interrupt.
+  *     @arg DMA2_INT_HT2: DMA2 Channel2 half transfer interrupt.
+  *     @arg DMA2_INT_ERR2: DMA2 Channel2 transfer error interrupt.
+  *     @arg DMA2_INT_GL3: DMA2 Channel3 global interrupt.
+  *     @arg DMA2_INT_TC3: DMA2 Channel3 transfer complete interrupt.
+  *     @arg DMA2_INT_HT3: DMA2 Channel3 half transfer interrupt.
+  *     @arg DMA2_INT_ERR3: DMA2 Channel3 transfer error interrupt.
+  *     @arg DMA2_INT_GL4: DMA2 Channel4 global interrupt.
+  *     @arg DMA2_INT_TC4: DMA2 Channel4 transfer complete interrupt.
+  *     @arg DMA2_INT_HT4: DMA2 Channel4 half transfer interrupt.
+  *     @arg DMA2_INT_ERR4: DMA2 Channel4 transfer error interrupt.
+  *     @arg DMA2_INT_GL5: DMA2 Channel5 global interrupt.
+  *     @arg DMA2_INT_TC5: DMA2 Channel5 transfer complete interrupt.
+  *     @arg DMA2_INT_HT5: DMA2 Channel5 half transfer interrupt.
+  *     @arg DMA2_INT_ERR5: DMA2 Channel5 transfer error interrupt.
+  * @retval The new state of DMAy_INT (SET or RESET).
+  */
+ITStatus DMA_GetITStatus(uint32_t DMAy_INT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_INT(DMAy_INT));
+
+  /* Calculate the used DMA */
+#if !defined (AT32F421xx)
+  if ((DMAy_INT & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Get DMA2 ISR register value */
+    tmpreg = DMA2->ISTS;
+  }
+  else
+#endif
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISTS;
+  }
+
+  /* Check the status of the specified DMAy interrupt */
+  if ((tmpreg & DMAy_INT) != (uint32_t)RESET)
+  {
+    /* DMAy_INT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_INT is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the DMA_INT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Channelx's interrupt pending bits.
+  * @param  DMAy_INT: specifies the DMAy interrupt pending bit to clear.
+  *   This parameter can be any combination (for the same DMA) of the following values:
+  *     @arg DMA1_INT_GL1: DMA1 Channel1 global interrupt.
+  *     @arg DMA1_INT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *     @arg DMA1_INT_HT1: DMA1 Channel1 half transfer interrupt.
+  *     @arg DMA1_INT_ERR1: DMA1 Channel1 transfer error interrupt.
+  *     @arg DMA1_INT_GL2: DMA1 Channel2 global interrupt.
+  *     @arg DMA1_INT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *     @arg DMA1_INT_HT2: DMA1 Channel2 half transfer interrupt.
+  *     @arg DMA1_INT_ERR2: DMA1 Channel2 transfer error interrupt.
+  *     @arg DMA1_INT_GL3: DMA1 Channel3 global interrupt.
+  *     @arg DMA1_INT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *     @arg DMA1_INT_HT3: DMA1 Channel3 half transfer interrupt.
+  *     @arg DMA1_INT_ERR3: DMA1 Channel3 transfer error interrupt.
+  *     @arg DMA1_INT_GL4: DMA1 Channel4 global interrupt.
+  *     @arg DMA1_INT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *     @arg DMA1_INT_HT4: DMA1 Channel4 half transfer interrupt.
+  *     @arg DMA1_INT_ERR4: DMA1 Channel4 transfer error interrupt.
+  *     @arg DMA1_INT_GL5: DMA1 Channel5 global interrupt.
+  *     @arg DMA1_INT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *     @arg DMA1_INT_HT5: DMA1 Channel5 half transfer interrupt.
+  *     @arg DMA1_INT_ERR5: DMA1 Channel5 transfer error interrupt.
+  *     @arg DMA1_INT_GL6: DMA1 Channel6 global interrupt.
+  *     @arg DMA1_INT_TC6: DMA1 Channel6 transfer complete interrupt.
+  *     @arg DMA1_INT_HT6: DMA1 Channel6 half transfer interrupt.
+  *     @arg DMA1_INT_ERR6: DMA1 Channel6 transfer error interrupt.
+  *     @arg DMA1_INT_GL7: DMA1 Channel7 global interrupt.
+  *     @arg DMA1_INT_TC7: DMA1 Channel7 transfer complete interrupt.
+  *     @arg DMA1_INT_HT7: DMA1 Channel7 half transfer interrupt.
+  *     @arg DMA1_INT_ERR7: DMA1 Channel7 transfer error interrupt.
+  *     @arg DMA2_INT_GL1: DMA2 Channel1 global interrupt.
+  *     @arg DMA2_INT_TC1: DMA2 Channel1 transfer complete interrupt.
+  *     @arg DMA2_INT_HT1: DMA2 Channel1 half transfer interrupt.
+  *     @arg DMA2_INT_ERR1: DMA2 Channel1 transfer error interrupt.
+  *     @arg DMA2_INT_GL2: DMA2 Channel2 global interrupt.
+  *     @arg DMA2_INT_TC2: DMA2 Channel2 transfer complete interrupt.
+  *     @arg DMA2_INT_HT2: DMA2 Channel2 half transfer interrupt.
+  *     @arg DMA2_INT_ERR2: DMA2 Channel2 transfer error interrupt.
+  *     @arg DMA2_INT_GL3: DMA2 Channel3 global interrupt.
+  *     @arg DMA2_INT_TC3: DMA2 Channel3 transfer complete interrupt.
+  *     @arg DMA2_INT_HT3: DMA2 Channel3 half transfer interrupt.
+  *     @arg DMA2_INT_ERR3: DMA2 Channel3 transfer error interrupt.
+  *     @arg DMA2_INT_GL4: DMA2 Channel4 global interrupt.
+  *     @arg DMA2_INT_TC4: DMA2 Channel4 transfer complete interrupt.
+  *     @arg DMA2_INT_HT4: DMA2 Channel4 half transfer interrupt.
+  *     @arg DMA2_INT_ERR4: DMA2 Channel4 transfer error interrupt.
+  *     @arg DMA2_INT_GL5: DMA2 Channel5 global interrupt.
+  *     @arg DMA2_INT_TC5: DMA2 Channel5 transfer complete interrupt.
+  *     @arg DMA2_INT_HT5: DMA2 Channel5 half transfer interrupt.
+  *     @arg DMA2_INT_ERR5: DMA2 Channel5 transfer error interrupt.
+  * @retval None
+  */
+void DMA_ClearITPendingBit(uint32_t DMAy_INT)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_INT(DMAy_INT));
+
+  /* Calculate the used DMAy */
+#if !defined (AT32F421xx)
+  if ((DMAy_INT & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Clear the selected DMAy interrupt pending bits */
+    DMA2->ICLR = DMAy_INT;
+  }
+  else
+#endif
+  {
+    /* Clear the selected DMAy interrupt pending bits */
+    DMA1->ICLR = DMAy_INT;
+  }
+}
+/**
+  * @brief  Deinitializes the DMAy Channelx registers to their default reset
+  *         values.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @retval None
+  */
+void DMA_Reset(DMA_Channel_Type* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+  /* Disable the selected DMAy Channelx */
+  DMAy_Channelx->CHCTRL &= (uint16_t)(~DMA_CHCTRL1_CHEN);
+
+  /* Reset DMAy Channelx control register */
+  DMAy_Channelx->CHCTRL  = 0;
+
+  /* Reset DMAy Channelx remaining bytes register */
+  DMAy_Channelx->TCNT = 0;
+
+  /* Reset DMAy Channelx peripheral address register */
+  DMAy_Channelx->CPBA  = 0;
+
+  /* Reset DMAy Channelx memory address register */
+  DMAy_Channelx->CMBA = 0;
+
+  if (DMAy_Channelx == DMA1_Channel1)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel1 */
+    DMA1->ICLR |= DMA1_CHANNEL1_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel2)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel2 */
+    DMA1->ICLR |= DMA1_CHANNEL2_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel3)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel3 */
+    DMA1->ICLR |= DMA1_CHANNEL3_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel4)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel4 */
+    DMA1->ICLR |= DMA1_CHANNEL4_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel5)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel5 */
+    DMA1->ICLR |= DMA1_CHANNEL5_INT_MASK;
+  }
+#if !defined (AT32F421xx)
+  else if (DMAy_Channelx == DMA1_Channel6)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel6 */
+    DMA1->ICLR |= DMA1_CHANNEL6_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel7)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel7 */
+    DMA1->ICLR |= DMA1_CHANNEL7_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel1)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel1 */
+    DMA2->ICLR |= DMA2_CHANNEL1_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel2)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel2 */
+    DMA2->ICLR |= DMA2_CHANNEL2_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel3)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel3 */
+    DMA2->ICLR |= DMA2_CHANNEL3_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel4)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel4 */
+    DMA2->ICLR |= DMA2_CHANNEL4_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel5)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel5 */
+    DMA2->ICLR |= DMA2_CHANNEL5_INT_MASK;
+  }
+#endif
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_exti.c

@@ -0,0 +1,261 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_exti.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx EXTI source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_exti.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup EXTI
+  * @brief EXTI driver modules
+  * @{
+  */
+
+/** @defgroup EXTI_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_Defines
+  * @{
+  */
+
+#define EXTI_LINENONE           ((uint32_t)0x00000)  /* No interrupt selected */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  EXTI_Line: specifies the EXTI line flag to check.
+  *   This parameter can be:
+  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+  if ((EXTI->PND & EXTI_Line) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
+  * @retval None
+  */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->PND = EXTI_Line;
+}
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  EXTI_Line: specifies the EXTI line to check.
+  *   This parameter can be:
+  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+ITStatus EXTI_GetIntStatus(uint32_t EXTI_Line)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+  enablestatus =  EXTI->INTEN & EXTI_Line;
+
+  if (((EXTI->PND & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  EXTI_Line: specifies the EXTI lines to clear.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
+  * @retval None
+  */
+void EXTI_ClearIntPendingBit(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->PND = EXTI_Line;
+}
+
+/**
+  * @brief  Fills each EXTI_InitStruct member with its reset value.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitType structure which will
+  *         be initialized.
+  * @retval None
+  */
+void EXTI_StructInit(EXTI_InitType* EXTI_InitStruct)
+{
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+  EXTI_InitStruct->EXTI_LineEnable = DISABLE;
+}
+
+/**
+  * @brief  Generates a Software interrupt.
+  * @param  EXTI_Line: specifies the EXTI lines to be enabled or disabled.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
+  * @retval None
+  */
+void EXTI_GenerateSWInt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->SWIE |= EXTI_Line;
+}
+
+/**
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void EXTI_Reset(void)
+{
+  EXTI->INTEN = 0x00000000;
+  EXTI->EVTEN = 0x00000000;
+  EXTI->RTRSEL = 0x00000000;
+  EXTI->FTRSEL = 0x00000000;
+  EXTI->PND = 0x007FFFFF;
+}
+
+/**
+  * @brief  Initializes the EXTI peripheral according to the specified
+  *         parameters in the EXTI_InitStruct.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitType structure
+  *         that contains the configuration information for the EXTI peripheral.
+  * @retval None
+  */
+void EXTI_Init(EXTI_InitType* EXTI_InitStruct)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineEnable));
+
+  tmp = (uint32_t)EXTI_BASE;
+
+  if (EXTI_InitStruct->EXTI_LineEnable != DISABLE)
+  {
+    /* Clear EXTI line configuration */
+    EXTI->INTEN &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->EVTEN &= ~EXTI_InitStruct->EXTI_Line;
+
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+    /* Clear Rising Falling edge configuration */
+    EXTI->RTRSEL &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->FTRSEL &= ~EXTI_InitStruct->EXTI_Line;
+
+    /* Select the trigger for the selected external interrupts */
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+    {
+      /* Rising Falling edge */
+      EXTI->RTRSEL |= EXTI_InitStruct->EXTI_Line;
+      EXTI->FTRSEL |= EXTI_InitStruct->EXTI_Line;
+    }
+    else
+    {
+      tmp = (uint32_t)EXTI_BASE;
+      tmp += EXTI_InitStruct->EXTI_Trigger;
+
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+    }
+  }
+  else
+  {
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    /* Disable the selected external lines */
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_gpio_ex.c

@@ -0,0 +1,522 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_gpio_ex.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx GPIO extended source file
+  **************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_gpio_ex.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup GPIO
+  * @brief GPIO driver modules
+  * @{
+  */
+
+#if defined (AT32F421xx)
+
+/** @defgroup GPIO_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Defines
+  * @{
+  */
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET                 (AFIO_BASE - PERIPH_BASE)
+
+/* --- EVENTCR Register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET                 (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber              ((uint8_t)0x07)
+#define EVCR_EVOE_BB                (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+
+/* ---  MAPR Register ---*/
+/* Alias word address of MII_RMII_SEL bit */
+#define MAP_OFFSET                 (AFIO_OFFSET + 0x04)
+#define MII_RMII_SEL_BitNumber      ((u8)0x17)
+#define MAPR_MII_RMII_SEL_BB        (PERIPH_BB_BASE + (MAP_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
+
+
+#define EVCR_PORTPINCONFIG_MASK     ((uint16_t)0xFF80)
+#define LSB_MASK                    ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK        ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCONF_MASK          ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK        ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK         ((uint32_t)0x00100000)
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @retval None
+  */
+void GPIO_Reset(GPIO_Type* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  if (GPIOx == GPIOA)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPERIPH_GPIOA, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPERIPH_GPIOA, DISABLE);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPERIPH_GPIOB, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPERIPH_GPIOB, DISABLE);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPERIPH_GPIOC, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPERIPH_GPIOC, DISABLE);
+  }
+  else if (GPIOx == GPIOF)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPERIPH_GPIOF, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPERIPH_GPIOF, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified
+  *         parameters in the GPIO_InitStruct.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitType structure that
+  *         contains the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void GPIO_Init(GPIO_Type* GPIOx, GPIO_InitType* GPIO_InitStruct)
+{
+  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_MDE(GPIO_InitStruct->GPIO_Mode));
+  assert_param(IS_GPIO_PINS(GPIO_InitStruct->GPIO_Pins));
+  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_Pull));
+  assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OutType));
+  assert_param(IS_GPIO_MAXSPEED(GPIO_InitStruct->GPIO_MaxSpeed));
+	
+  if(!IS_GPIO_MDE(GPIO_InitStruct->GPIO_Mode))
+  {
+    GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+  }
+  if(!IS_GPIO_PUPD(GPIO_InitStruct->GPIO_Pull))
+  {
+    GPIO_InitStruct->GPIO_Pull = GPIO_Pull_NOPULL;
+  }
+  if(!IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OutType))
+  {
+    GPIO_InitStruct->GPIO_OutType = GPIO_OutType_PP;
+  }
+  if(!IS_GPIO_MAXSPEED(GPIO_InitStruct->GPIO_MaxSpeed))
+  {
+    GPIO_InitStruct->GPIO_MaxSpeed = GPIO_MaxSpeed_2MHz;
+  }
+
+  /*-------------------------- Configure the port pins -----------------------*/
+  /*-- GPIO Mode Configuration --*/
+  for (pinpos = 0x00; pinpos < 0x10; pinpos++)
+  {
+    pos = ((uint32_t)0x01) << pinpos;
+
+    /* Get the port pins position */
+    currentpin = (GPIO_InitStruct->GPIO_Pins) & pos;
+
+    if (currentpin == pos)
+    {
+      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_GPIO_MAXSPEED(GPIO_InitStruct->GPIO_MaxSpeed));
+
+        /* Speed mode configuration */
+        GPIOx->ODRVR &= ~(GPIO_ODRVR_ODRV0 << (pinpos * 2));
+        GPIOx->ODRVR |= ((uint32_t)(GPIO_InitStruct->GPIO_MaxSpeed) << (pinpos * 2));
+
+        /* Output mode configuration */
+        GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
+        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OutType) << ((uint16_t)pinpos));
+      }
+
+      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
+
+      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+
+      /* Pull-up Pull down resistor configuration */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
+      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_Pull) << (pinpos * 2));
+    }
+  }
+}
+
+/**
+  * @brief  Fills each GPIO_InitStruct member with its default value.
+  * @param  GPIO_InitStruct : pointer to a GPIO_InitType structure which will
+  *         be initialized.
+  * @retval None
+  */
+void GPIO_StructInit(GPIO_InitType* GPIO_InitStruct)
+{
+  GPIO_InitStruct->GPIO_Pins  = GPIO_Pins_All;
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStruct->GPIO_MaxSpeed = GPIO_MaxSpeed_2MHz;
+  GPIO_InitStruct->GPIO_OutType = GPIO_OutType_PP;
+  GPIO_InitStruct->GPIO_Pull = GPIO_Pull_NOPULL;
+}
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin:  specifies the port bit to read.
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+uint8_t GPIO_ReadInputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PINS(GPIO_Pin));
+
+  if ((GPIOx->IPTDT & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO input data port.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @retval GPIO input data port value.
+  */
+uint16_t GPIO_ReadInputData(GPIO_Type* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->IPTDT);
+}
+
+/**
+  * @brief  Reads the specified output data port bit.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin:  specifies the port bit to read.
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The output port pin value.
+  */
+uint8_t GPIO_ReadOutputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PINS(GPIO_Pin));
+
+  if ((GPIOx->OPTDT & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO output data port.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @retval GPIO output data port value.
+  */
+uint16_t GPIO_ReadOutputData(GPIO_Type* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->OPTDT);
+}
+
+/**
+  * @brief  Sets the selected data port bits.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_SetBits(GPIO_Type* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PINS(GPIO_Pin));
+
+  GPIOx->BSRE = GPIO_Pin;
+}
+
+/**
+  * @brief  Clears the selected data port bits.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_ResetBits(GPIO_Type* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PINS(GPIO_Pin));
+
+  GPIOx->BRE = GPIO_Pin;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *   This parameter can be one of GPIO_Pin_x where x can be (0..15).
+  * @param  BitVal: specifies the value to be written to the selected bit.
+  *   This parameter can be one of the BitState enum values:
+  *     @arg Bit_RESET: to clear the port pin
+  *     @arg Bit_SET: to set the port pin
+  * @retval None
+  */
+void GPIO_WriteBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin, BitState BitVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PINS(GPIO_Pin));
+  assert_param(IS_GPIO_BIT_STATE(BitVal));
+
+  if (BitVal != Bit_RESET)
+  {
+    GPIOx->BSRE = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BRE = GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  PortVal: specifies the value to be written to the port output data register.
+  * @retval None
+  */
+void GPIO_Write(GPIO_Type* GPIOx, uint16_t PortVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  GPIOx->OPTDT = PortVal;
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_PinsLockConfig(GPIO_Type* GPIOx, uint16_t GPIO_Pin)
+{
+  uint32_t tmp = 0x00010000;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PINS(GPIO_Pin));
+
+  tmp |= GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LOCK = tmp;
+  /* Reset LCKK bit */
+  GPIOx->LOCK =  GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LOCK = tmp;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LOCK;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LOCK;
+}
+
+/**
+  * @brief  Enables or disables to enhance slew rate of GPIO Pins.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @param  NewState: new state of the slew rate.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void GPIO_PinsEnhanceSlewRate(GPIO_Type* GPIOx, uint16_t GPIO_Pin, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PINS(GPIO_Pin));
+  if( ENABLE == NewState ){
+      GPIOx->SRCTR |= GPIO_Pin;
+  }else{
+      GPIOx->SRCTR &= ~GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Enables or disables GPIO Pins huge driven.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @param  NewState: new state of the slew rate.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void GPIO_PinsHugeDriven(GPIO_Type* GPIOx, uint16_t GPIO_Pin, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PINS(GPIO_Pin));
+  if( ENABLE == NewState ){
+      GPIOx->HDRV |= GPIO_Pin;
+  }else{
+      GPIOx->HDRV &= ~GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A or B) to select the GPIO peripheral.
+  * @param  GPIO_PinSource: specifies the pin for the Alternate function.
+  *          This parameter can be GPIO_PinSourcex where x can be (0..15).
+  * @param  GPIO_AF: selects the pin to used as Alternate function.
+  *          This parameter can be one of the following value:
+  *            @arg GPIO_AF_0: EVENTOUT, TIM15, SPI1, TIM17, MCO, SWDAT, SWCLK, TIM14,
+  *                            USART1, IR_OUT, SPI2 
+  *            @arg GPIO_AF_1: USART2, TMR3, USART1, USART2, EVENTOUT, I2C1, I2C2, TMR15, IR_OUT 
+  *            @arg GPIO_AF_2: TMR2, TMR1, EVENTOUT, TMR16, TMR17
+  *            @arg GPIO_AF_3: USART2, I2C1, TMR15, EVENTOUT 
+  *            @arg GPIO_AF_4: I2C2, TMR14, USART2, I2C1
+  *            @arg GPIO_AF_5: TMR1, TMR15, TMR16, TMR17, I2C2, MCO
+  *            @arg GPIO_AF_6: EVENTOUT, SPI2
+  *            @arg GPIO_AF_7: COMP1 OUT, COMP2 OUT, I2C2, SPI2
+  * @note   The pin should already been configured in Alternate Function mode(AF)
+  *         using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+  * @note   Refer to the Alternate function mapping table in the device datasheet 
+  *         for the detailed mapping of the system and peripherals'alternate 
+  *         function I/O pins.
+  * @retval None
+  */
+void GPIO_PinAFConfig(GPIO_Type* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
+{
+  uint32_t temp = 0x00;
+  uint32_t temp_2 = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PINS_SOURCE(GPIO_PinSource));
+  assert_param(IS_GPIO_AF(GPIO_AF));
+
+  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
+  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
+}
+
+#if defined (AT32F421PF4P7) || defined (AT32F421PF8P7)
+/**
+  * @brief  Unused GPIO pin Init.
+  * @note   The pin should been configured in analog mode(AN), This function just
+  *         only be called by AT32F421PFxP7 packages.
+  * @retval None
+  */
+void GPIO_F421PFxP7_LowPower(void)
+{
+  GPIO_InitType GPIO_InitStructure;
+  RCC_AHBPeriphClockCmd(RCC_AHBPERIPH_GPIOA | RCC_AHBPERIPH_GPIOB | RCC_AHBPERIPH_GPIOC | \
+                        RCC_AHBPERIPH_GPIOF, ENABLE);
+
+  GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
+  GPIO_InitStructure.GPIO_Pull = GPIO_Pull_NOPULL;
+
+  GPIO_InitStructure.GPIO_Pins = GPIO_Pins_11 | GPIO_Pins_12;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5 | \
+                                 GPIO_Pins_6 | GPIO_Pins_7 | GPIO_Pins_8 | GPIO_Pins_9 | GPIO_Pins_10| \
+                                 GPIO_Pins_11| GPIO_Pins_12| GPIO_Pins_13| GPIO_Pins_15;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pins = GPIO_Pins_13| GPIO_Pins_14| GPIO_Pins_15;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_6 | GPIO_Pins_7;
+  GPIO_Init(GPIOF, &GPIO_InitStructure);
+}
+#endif /* AT32F421PF4P7 || AT32F421PF8P7 */
+
+/**
+  * @}
+  */
+
+#endif /* AT32F421xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_iwdg.c

@@ -0,0 +1,182 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_iwdg.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx IWDG source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_iwdg.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup IWDG
+  * @brief IWDG driver modules
+  * @{
+  */
+
+/** @defgroup IWDG_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Defines
+  * @{
+  */
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KR register bit mask */
+#define KR_KEY_Reload           ((uint16_t)0xAAAA)
+#define KR_KEY_Enable           ((uint16_t)0xCCCC)
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  *   (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_ReloadCounter(void)
+{
+  IWDG->KEY = KR_KEY_Reload;
+}
+
+/**
+  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_Enable(void)
+{
+  IWDG->KEY = KR_KEY_Enable;
+}
+
+/**
+  * @brief  Checks whether the specified IWDG flag is set or not.
+  * @param  IWDG_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_FLAG_PSCF: Prescaler Value Update on going
+  *     @arg IWDG_FLAG_RLDF: Reload Value Update on going
+  * @retval The new state of IWDG_FLAG (SET or RESET).
+  */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+
+  if ((IWDG->STS & IWDG_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_KeyRegWrite_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+  *     @arg IWDG_KeyRegWrite_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+  * @retval None
+  */
+void IWDG_KeyRegWrite(uint16_t IWDG_WriteAccess)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_KEY_REG_WRITE(IWDG_WriteAccess));
+  IWDG->KEY = IWDG_WriteAccess;
+}
+
+/**
+  * @brief  Sets IWDG Prescaler value.
+  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_Psc_4: IWDG prescaler set to 4
+  *     @arg IWDG_Psc_8: IWDG prescaler set to 8
+  *     @arg IWDG_Psc_16: IWDG prescaler set to 16
+  *     @arg IWDG_Psc_32: IWDG prescaler set to 32
+  *     @arg IWDG_Psc_64: IWDG prescaler set to 64
+  *     @arg IWDG_Psc_128: IWDG prescaler set to 128
+  *     @arg IWDG_Psc_256: IWDG prescaler set to 256
+  * @retval None
+  */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_PSC(IWDG_Prescaler));
+  IWDG->PSC = IWDG_Prescaler;
+}
+
+/**
+  * @brief  Sets IWDG Reload value.
+  * @param  Reload: specifies the IWDG Reload value.
+  *   This parameter must be a number between 0 and 0x0FFF.
+  * @retval None
+  */
+void IWDG_SetReload(uint16_t Reload)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_RLD(Reload));
+  IWDG->RLD = Reload;
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_pwr.c

@@ -0,0 +1,440 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_pwr.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx PWR source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_pwr.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup PWR
+  * @brief PWR driver modules
+  * @{
+  */
+
+/** @defgroup PWR_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Defines
+  * @{
+  */
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET                  (PWR_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ---*/
+
+/* Alias word address of DBP bit */
+#define CTRL_OFFSET                 (PWR_OFFSET + 0x00)
+#define DBP_BitNumber                0x08
+#define CTRL_DBP_BB                 (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber              0x04
+#define CTRL_PVDE_BB                (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of EWUP bit */
+#define CTRLSTS_OFFSET              (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber              0x08
+#define CTRLSTS_EWUP_BB             (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+#if defined (AT32F421xx)
+  /* Alias word address of EWUP2 bit */
+  #define EWUP_BitNumber2           0x09
+  #define CTRLSTS_EWUP_BB2          (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (EWUP_BitNumber2 * 4))
+
+  /* Alias word address of EWUP6 bit */
+  #define EWUP_BitNumber6           0x0D
+  #define CTRLSTS_EWUP_BB6          (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (EWUP_BitNumber6 * 4))
+
+  /* Alias word address of EWUP7 bit */
+  #define EWUP_BitNumber7           0x0E
+  #define CTRLSTS_EWUP_BB7          (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (EWUP_BitNumber7 * 4))
+#endif
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CTRL register bit mask */
+#if defined (AT32F403xx) || defined (AT32F413xx)
+  #define CTRL_LPDS_MASK            ((uint32_t)0x00000002)
+#else
+  #define CTRL_LPDS_MASK            ((uint32_t)0x00000003)
+#endif
+#if defined (AT32F421xx)
+  #define CTRL2_LPDS1_MASK          ((uint32_t)0x00000020)
+#endif
+#define CTRL_PVDS_MASK              ((uint32_t)0x000000E0)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Checks whether the specified PWR flag is set or not.
+  * @param  PWR_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_FLAG_WUF: Wake Up flag
+  *     @arg PWR_FLAG_SBF: StandBy flag
+  *     @arg PWR_FLAG_PVDO: PVD Output
+  * @retval The new state of PWR_FLAG (SET or RESET).
+  */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+
+  if ((PWR->CTRLSTS & PWR_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the PWR's pending flags.
+  * @param  PWR_FLAG: specifies the flag to clear.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_FLAG_WUF: Wake Up flag
+  *     @arg PWR_FLAG_SBF: StandBy flag
+  * @retval None
+  */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+  PWR->CTRL |=  PWR_FLAG << 2;
+}
+
+/**
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void PWR_Reset(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_PWR, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_PWR, DISABLE);
+}
+
+/**
+  * @brief  Enables or disables access to the RTC and backup registers.
+  * @param  NewState: new state of the access to the RTC and backup registers.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_BackupAccessCtrl(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRL_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
+  * @param  NewState: new state of the PVD.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_PVDCtrl(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRL_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param  PWR_PVDLevel: specifies the PVD detection level
+  *   This parameter can be one of the following values:
+  *     @arg PWR_PVDS_2V2: PVD detection level set to 2.2V
+  *     @arg PWR_PVDS_2V3: PVD detection level set to 2.3V
+  *     @arg PWR_PVDS_2V4: PVD detection level set to 2.4V
+  *     @arg PWR_PVDS_2V5: PVD detection level set to 2.5V
+  *     @arg PWR_PVDS_2V6: PVD detection level set to 2.6V
+  *     @arg PWR_PVDS_2V7: PVD detection level set to 2.7V
+  *     @arg PWR_PVDS_2V8: PVD detection level set to 2.8V
+  *     @arg PWR_PVDS_2V9: PVD detection level set to 2.9V
+  * @retval None
+  */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+  tmpreg = PWR->CTRL;
+  /* Clear PLS[7:5] bits */
+  tmpreg &= ~CTRL_PVDS_MASK;
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+  tmpreg |= PWR_PVDLevel;
+  /* Store the new value */
+  PWR->CTRL = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the WakeUp Pin functionality.
+  * @param  NewState: new state of the WakeUp Pin functionality.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCtrl(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRLSTS_EWUP_BB = (uint32_t)NewState;
+}
+
+#if defined (AT32F421xx)
+/**
+  * @brief  Enables or disables the WakeUp Pin2 functionality.
+  * @param  NewState: new state of the WakeUp Pin2 functionality.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCtrl2(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRLSTS_EWUP_BB2 = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the WakeUp Pin6 functionality.
+  * @param  NewState: new state of the WakeUp Pin6 functionality.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCtrl6(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRLSTS_EWUP_BB6 = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the WakeUp Pin7 functionality.
+  * @param  NewState: new state of the WakeUp Pin7 functionality.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCtrl7(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRLSTS_EWUP_BB7 = (uint32_t)NewState;
+}
+#endif
+
+/**
+  * @brief  Enters Sleep mode.
+  * @note   In Sleep mode, all I/O pins keep the same state as in Run mode.
+  * @param  PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *             @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+  *             @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+  
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+}
+
+#if defined (AT32F403xx) || defined (AT32F413xx)
+/**
+  * @brief  Enters STOP mode.
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+  *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CTRL;
+  /* Clear PDDS bit */
+  tmpreg &= ~CTRL_LPDS_MASK;
+  /* Store the new value */
+  PWR->CTRL = tmpreg;
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+}
+#else
+/**
+  * @brief  Enters STOP mode.
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_Regulator_ON: STOP mode with regulator ON
+  *     @arg PWR_Regulator_LowPower: STOP mode with regulator LowPower
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+  *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+  
+#if defined (AT32F421xx)
+  PWR->CTRL2 &= ~CTRL2_LPDS1_MASK;
+  tmpreg = PWR_Regulator & CTRL2_LPDS1_MASK;
+  PWR->CTRL2 = tmpreg;
+#endif
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CTRL;
+  /* Clear PDDS bit */
+  tmpreg &= ~CTRL_LPDS_MASK;
+  /* Set PWR_Regulator value */
+  tmpreg |= PWR_Regulator & CTRL_LPDS_MASK;
+  /* Store the new value */
+  PWR->CTRL = tmpreg;
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+}
+#endif
+
+/**
+  * @brief  Enters STANDBY mode.
+  * @param  None
+  * @retval None
+  */
+void PWR_EnterSTANDBYMode(void)
+{
+  /* Clear Wake-up flag */
+  PWR->CTRL |= PWR_CTRL_CLWUF;
+  /* Select STANDBY mode */
+  PWR->CTRL |= PWR_CTRL_PDDS;
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+  /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM   )
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_rtc.c

@@ -0,0 +1,336 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_rtc.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx RTC source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_rtc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RTC
+  * @brief RTC driver modules
+  * @{
+  */
+
+#if defined (AT32F403xx) || defined (AT32F413xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+
+/** @defgroup RTC_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_Defines
+  * @{
+  */
+#define RTC_LSB_MASK            ((uint32_t)0x0000FFFF)  /*!< RTC LSB Mask */
+#define DIVH_MSB_MASK           ((uint32_t)0x000F0000)  /*!< RTC Prescaler MSB Mask */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Checks whether the specified RTC flag is set or not.
+  * @param  RTC_FLAG: specifies the flag to check.
+  *   This parameter can be one the following values:
+  *     @arg RTC_FLAG_RTF: RTC Operation OFF flag
+  *     @arg RTC_FLAG_RSYNF: Registers Synchronized flag
+  *     @arg RTC_FLAG_OV: Overflow flag
+  *     @arg RTC_FLAG_ALA: Alarm flag
+  *     @arg RTC_FLAG_PACE: Second flag
+  * @retval The new state of RTC_FLAG (SET or RESET).
+  */
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+  if ((RTC->CTRLL & RTC_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's pending flags.
+  * @param  RTC_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_FLAG_RSYNF: Registers Synchronized flag. This flag is cleared only after
+  *                        an APB reset or an APB Clock stop.
+  *     @arg RTC_FLAG_OV: Overflow flag
+  *     @arg RTC_FLAG_ALA: Alarm flag
+  *     @arg RTC_FLAG_PACE: Second flag
+  * @retval None
+  */
+void RTC_ClearFlag(uint16_t RTC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+  /* Clear the corresponding RTC flag */
+  RTC->CTRLL &= (uint16_t)~RTC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified RTC interrupt has occurred or not.
+  * @param  RTC_INT: specifies the RTC interrupts sources to check.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_INT_OV: Overflow interrupt
+  *     @arg RTC_INT_ALA: Alarm interrupt
+  *     @arg RTC_INT_PACE: Second interrupt
+  * @retval The new state of the RTC_INT (SET or RESET).
+  */
+ITStatus RTC_GetINTStatus(uint16_t RTC_INT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_INT(RTC_INT));
+
+  bitstatus = (ITStatus)(RTC->CTRLL & RTC_INT);
+
+  if (((RTC->CTRLH & RTC_INT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's interrupt pending bits.
+  * @param  RTC_INT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_INT_OV: Overflow interrupt
+  *     @arg RTC_INT_ALA: Alarm interrupt
+  *     @arg RTC_INT_PACE: Second interrupt
+  * @retval None
+  */
+void RTC_ClearINTPendingBit(uint16_t RTC_INT)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_INT(RTC_INT));
+
+  /* Clear the corresponding RTC pending bit */
+  RTC->CTRLL &= (uint16_t)~RTC_INT;
+}
+
+/**
+  * @brief  Enables or disables the specified RTC interrupts.
+  * @param  RTC_INT: specifies the RTC interrupts sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_INT_OV: Overflow interrupt
+  *     @arg RTC_INT_ALA: Alarm interrupt
+  *     @arg RTC_INT_PACE: Second interrupt
+  * @param  NewState: new state of the specified RTC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_INTConfig(uint16_t RTC_INT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_INT(RTC_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RTC->CTRLH |= RTC_INT;
+  }
+  else
+  {
+    RTC->CTRLH &= (uint16_t)~RTC_INT;
+  }
+}
+
+/**
+  * @brief  Sets the RTC counter value.
+  * @param  CounterValue: RTC counter new value.
+  * @retval None
+  */
+void RTC_SetCounter(uint32_t CounterValue)
+{
+  RTC_EnterConfigMode();
+  /* Set RTC COUNTER MSB word */
+  RTC->CNTH = CounterValue >> 16;
+  /* Set RTC COUNTER LSB word */
+  RTC->CNTL = (CounterValue & RTC_LSB_MASK);
+  RTC_ExitConfigMode();
+}
+
+/**
+  * @brief  Sets the RTC prescaler value.
+  * @param  PrescalerValue: RTC prescaler new value.
+  * @retval None
+  */
+void RTC_SetDIV(uint32_t PrescalerValue)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_DIV(PrescalerValue));
+
+  RTC_EnterConfigMode();
+  /* Set RTC PRESCALER MSB word */
+  RTC->DIVH = (PrescalerValue & DIVH_MSB_MASK) >> 16;
+  /* Set RTC PRESCALER LSB word */
+  RTC->DIVL = (PrescalerValue & RTC_LSB_MASK);
+  RTC_ExitConfigMode();
+}
+
+/**
+  * @brief  Sets the RTC alarm value.
+  * @param  AlarmValue: RTC alarm new value.
+  * @retval None
+  */
+void RTC_SetAlarmValue(uint32_t AlarmValue)
+{
+  RTC_EnterConfigMode();
+  /* Set the ALARM MSB word */
+  RTC->ALAH = AlarmValue >> 16;
+  /* Set the ALARM LSB word */
+  RTC->ALAL = (AlarmValue & RTC_LSB_MASK);
+  RTC_ExitConfigMode();
+}
+
+/**
+  * @brief  Gets the RTC divider value.
+  * @param  None
+  * @retval RTC Divider value.
+  */
+uint32_t RTC_GetDivider(void)
+{
+  uint32_t tmp = 0x00;
+  tmp = ((uint32_t)RTC->DIVCNTH & (uint32_t)0x000F) << 16;
+  tmp |= RTC->DIVCNTL;
+  return tmp;
+}
+
+/**
+  * @brief  Waits until last write operation on RTC registers has finished.
+  * @note   This function must be called before any write to RTC registers.
+  * @param  None
+  * @retval None
+  */
+void RTC_WaitForLastTask(void)
+{
+  /* Loop until RTOFF flag is set */
+  while ((RTC->CTRLL & RTC_FLAG_RTF) == (uint16_t)RESET)
+  {
+  }
+}
+
+/**
+  * @brief  Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+  *   are synchronized with RTC APB clock.
+  * @note   This function must be called before any read operation after an APB reset
+  *   or an APB clock stop.
+  * @param  None
+  * @retval None
+  */
+void RTC_WaitForSynchro(void)
+{
+  /* Clear RSF flag */
+  RTC->CTRLL &= (uint16_t)~RTC_FLAG_RSYNF;
+
+  /* Loop until RSF flag is set */
+  while ((RTC->CTRLL & RTC_FLAG_RSYNF) == (uint16_t)RESET)
+  {
+  }
+}
+
+/**
+  * @brief  Enters the RTC configuration mode.
+  * @param  None
+  * @retval None
+  */
+void RTC_EnterConfigMode(void)
+{
+  /* Set the CNF flag to enter in the Configuration Mode */
+  RTC->CTRLL |= RTC_CTRLL_CMF;
+}
+
+/**
+  * @brief  Exits from the RTC configuration mode.
+  * @param  None
+  * @retval None
+  */
+void RTC_ExitConfigMode(void)
+{
+  /* Reset the CNF flag to exit from the Configuration Mode */
+  RTC->CTRLL &= (uint16_t)~((uint16_t)RTC_CTRLL_CMF);
+}
+
+/**
+  * @brief  Gets the RTC counter value.
+  * @param  None
+  * @retval RTC counter value.
+  */
+uint32_t RTC_GetCounter(void)
+{
+  uint16_t tmp = 0;
+  tmp = RTC->CNTL;
+  return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
+}
+
+/**
+  * @}
+  */
+
+#endif /* AT32F403xx || AT32F413xx || AT32F403Axx || AT32F407xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_sdio.c

@@ -0,0 +1,920 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_sdio.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx SDIO source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_sdio.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SDIO
+  * @brief SDIO driver modules
+  * @{
+  */
+
+#if defined (AT32F403xx) || defined (AT32F413xx) || defined (AT32F415xx) || \
+    defined (AT32F403Axx)|| defined (AT32F407xx)
+
+/** @defgroup SDIO_Private_TypesDefinitions
+  * @{
+  */
+
+/* --- CLKCR Register ---*/
+
+/* SDIO CLKEN mask */
+#define CLKCTRL_CLKEN_Set           ((uint32_t)0x00000100)
+#define CLKCTRL_CLKEN_Rst           ((uint32_t)0xFFFFFEFF)
+
+
+/* --- CMD Register ---*/
+
+/* SDIO SDIOSUSPEND mask */
+#define CMD_SDIOSUSP_Set            ((uint32_t)0x00000800)
+#define CMD_SDIOSUSP_Rst            ((uint32_t)0xFFFFF7FF)
+
+/* SDIO ENCMDCOMPL mask */
+#define CMD_CMPLSGNLEN_Set          ((uint32_t)0x00001000)
+#define CMD_CMPLSGNLEN_Rst          ((uint32_t)0xFFFFEFFF)
+
+/* SDIO INTDIS mask */
+#define CMD_INTDIS_Set              ((uint32_t)0x00002000)
+#define CMD_INTDIS_Rst              ((uint32_t)0xFFFFDFFF)
+
+/* SDIO ATACMD mask */
+#define CMD_ATACMD_Set              ((uint32_t)0x00004000)
+#define CMD_ATACMD_Rst              ((uint32_t)0xFFFFBFFF)
+
+
+/* --- DTCTRL Register ---*/
+
+/* SDIO ATACMD mask */
+#define DTCTRL_DMAEN_Set            ((uint32_t)0x00000008)
+#define DTCTRL_DMAEN_Rst            ((uint32_t)0xFFFFFFF7)
+
+/* SDIO RWSTART mask */
+#define DTCTRL_RWSTART_Set          ((uint32_t)0x00000100)
+#define DTCTRL_RWSTART_Rst          ((uint32_t)0xFFFFFEFF)
+
+/* SDIO RWSTOP mask */
+#define DTCTRL_RWSTOP_Set           ((uint32_t)0x00000200)
+#define DTCTRL_RWSTOP_Rst           ((uint32_t)0xFFFFFDFF)
+
+/* SDIO RWMOD mask */
+#define DTCTRL_RWMOD_Set            ((uint32_t)0x00000400)
+
+/* SDIO SDIOEN mask */
+#define DTCTRL_SDIOEN_Set           ((uint32_t)0x00000800)
+#define DTCTRL_SDIOEN_Rst           ((uint32_t)0xFFFFF7FF)
+
+/* ---------------------- SDIO registers bit mask ------------------------ */
+
+/* --- CLKCR Register ---*/
+
+/* CLKCR register clear mask */
+#define CLKCTRL_CLEAR_MASK          ((uint32_t)0xFFFE0100)
+
+/* --- PWRCTRL Register ---*/
+
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK            ((uint32_t)0xFFFFFFFC)
+
+/* --- DTCTRL Register ---*/
+
+/* SDIO DTCTRL Clear Mask */
+#define DTCTRL_CLEAR_MASK           ((uint32_t)0xFFFFFF08)
+#define DTCTRL_RWMOD_MASK           ((uint32_t)0xFFFFFBFF)
+
+/* --- CMD Register ---*/
+
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK              ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address Offset */
+#define SDIO_RSP_ADDR_OFFSET        ((uint32_t)0x14)
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Fills each SDIO_CmdInitStruct member with its default value.
+  * @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitType
+  *         structure which will be initialized.
+  * @retval None
+  */
+void SDIO_CmdStructInit(SDIO_CmdInitType* SDIO_CmdInitStruct)
+{
+  /* SDIO_CmdInitStruct members default value */
+  SDIO_CmdInitStruct->SDIO_Argu = 0x00;
+  SDIO_CmdInitStruct->SDIO_CmdIdx = 0x00;
+  SDIO_CmdInitStruct->SDIO_Resp = SDIO_Rsp_No;
+  SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+/**
+  * @brief  Returns command index of last command for which response received.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @retval Returns the command index of the last command response received.
+  */
+uint8_t SDIO_GetCommandResponse(SDIO_Type * SDIOx)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  return (uint8_t)(SDIOx->RSPCMD);
+}
+
+/**
+  * @brief  Returns response received from the card for the last command.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_RESP: Specifies the SDIO response register.
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_RSP1: Response Register 1
+  *     @arg SDIO_RSP2: Response Register 2
+  *     @arg SDIO_RSP3: Response Register 3
+  *     @arg SDIO_RSP4: Response Register 4
+  * @retval The Corresponding response register value.
+  */
+uint32_t SDIO_GetResponse(SDIO_Type * SDIOx, uint32_t SDIO_RESP)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_RSP(SDIO_RESP));
+
+  tmp = (uint32_t)&SDIOx->RSP1 + SDIO_RESP;
+
+  return (*(__IO uint32_t *) tmp);
+}
+
+/**
+  * @brief  Initializes the SDIO data path according to the specified
+  *   parameters in the SDIO_DataInitStruct.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitType structure that
+  *   contains the configuration information for the SDIO command.
+  * @retval None
+  */
+void SDIO_DataConfig(SDIO_Type * SDIOx, SDIO_DataInitType* SDIO_DataInitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_DATA_LEN(SDIO_DataInitStruct->SDIO_DataLen));
+  assert_param(IS_SDIO_BLK_SIZE(SDIO_DataInitStruct->SDIO_DataBlkSize));
+  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
+  assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
+  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
+
+  /*---------------------------- SDIO DTIMER Configuration ---------------------*/
+  /* Set the SDIOx Data TimeOut value */
+  SDIOx->DTTMR = SDIO_DataInitStruct->SDIO_DataTimeOut;
+
+  /*---------------------------- SDIOx DLEN Configuration -----------------------*/
+  /* Set the SDIOx DataLength value */
+  SDIOx->DTLEN = SDIO_DataInitStruct->SDIO_DataLen;
+
+  /*---------------------------- SDIO DTCTRL Configuration ----------------------*/
+  /* Get the SDIOx DTCTRL value */
+  tmpreg = SDIOx->DTCTRL;
+  /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+  tmpreg &= DTCTRL_CLEAR_MASK;
+  /* Set DEN bit according to SDIO_DPSM value */
+  /* Set DTMODE bit according to SDIO_TransferMode value */
+  /* Set DTDIR bit according to SDIO_TransferDir value */
+  /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
+  tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlkSize | SDIO_DataInitStruct->SDIO_TransferDir
+            | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+  /* Write to SDIOx DTCTRL */
+  SDIOx->DTCTRL = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_DataInitStruct member with its default value.
+  * @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitType structure which
+  *         will be initialized.
+  * @retval None
+  */
+void SDIO_DataStructInit(SDIO_DataInitType* SDIO_DataInitStruct)
+{
+  /* SDIO_DataInitStruct members default value */
+  SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+  SDIO_DataInitStruct->SDIO_DataLen = 0x00;
+  SDIO_DataInitStruct->SDIO_DataBlkSize = SDIO_DataBlkSize_1b;
+  SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+  SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+/**
+  * @brief  Returns number of remaining data bytes to be transferred.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @retval Number of remaining data bytes to be transferred
+  */
+uint32_t SDIO_GetDataCounter(SDIO_Type * SDIOx)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  return SDIOx->DTCNTR;
+}
+
+/**
+  * @brief  Read one data word from Rx FIFO.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @retval Data received
+  */
+uint32_t SDIO_ReadData(SDIO_Type * SDIOx)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  return SDIOx->BUF;
+}
+
+/**
+  * @brief  Write one data word to Tx FIFO.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  Data: 32-bit data word to write.
+  * @retval None
+  */
+void SDIO_WriteData(SDIO_Type * SDIOx, uint32_t Data)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  SDIOx->BUF = Data;
+}
+
+/**
+  * @brief  Returns the number of words left to be written to or read from FIFO.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @retval Remaining number of words.
+  */
+uint32_t SDIO_GetBUFCount(SDIO_Type * SDIOx)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  return SDIOx->BUFCNTR;
+}
+
+/**
+  * @brief  Starts the SD I/O Read Wait operation.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of the Start SDIO Read Wait operation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_StartSDIOReadWait(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Start SDIO Read Wait operation. */
+    SDIOx->DTCTRL |= DTCTRL_RWSTART_Set;
+  }
+  else
+  {
+    /* Disable the Start SDIO Read Wait operation. */
+    SDIOx->DTCTRL &= DTCTRL_RWSTART_Rst;
+  }
+}
+
+/**
+  * @brief  Stops the SD I/O Read Wait operation.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of the Stop SDIO Read Wait operation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_StopSDIOReadWait(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Stop SDIO Read Wait operation. */
+    SDIOx->DTCTRL |= DTCTRL_RWSTOP_Set;
+  }
+  else
+  {
+    /* Disable the Stop SDIO Read Wait operation. */
+    SDIOx->DTCTRL &= DTCTRL_RWSTOP_Rst;
+  }
+}
+
+/**
+  * @brief  Sets one of the two options of inserting read wait interval.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
+  *   This parameter can be:
+  *     @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
+  *     @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
+  * @retval None
+  */
+void SDIO_SetSDIOReadWaitMode(SDIO_Type * SDIOx, uint32_t SDIO_ReadWaitMode)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
+
+  SDIOx->DTCTRL &= DTCTRL_RWMOD_MASK;
+
+  SDIOx->DTCTRL |= SDIO_ReadWaitMode;
+}
+
+/**
+  * @brief  Enables or disables the SD I/O Mode Operation.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of SDIO specific operation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SetSDIOOperation(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable SDIO specific operation. */
+    SDIOx->DTCTRL |= DTCTRL_SDIOEN_Set;
+  }
+  else
+  {
+    /* Disable SDIO specific operation. */
+    SDIOx->DTCTRL &= DTCTRL_SDIOEN_Rst;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SD I/O Mode suspend command sending.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of the SD I/O Mode suspend command.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SendSDIOSuspendCmd(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable SD I/O Mode suspend command. */
+    SDIOx->CMD |= CMD_SDIOSUSP_Set;
+  }
+  else
+  {
+    /* Disable SD I/O Mode suspend command. */
+    SDIOx->CMD &= CMD_SDIOSUSP_Rst;
+  }
+}
+
+/**
+  * @brief  Enables or disables the command completion signal.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of command completion signal.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_CommandCompletionCmd(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the command completion signal. */
+    SDIOx->CMD |= CMD_CMPLSGNLEN_Set;
+  }
+  else
+  {
+    /* Disable the command completion signal. */
+    SDIOx->CMD &= CMD_CMPLSGNLEN_Rst;
+  }
+}
+
+/**
+  * @brief  Enables or disables the CE-ATA interrupt.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_ATAINTCmd(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable ATA Interrupt. */
+    SDIOx->CMD &= CMD_INTDIS_Rst;
+  }
+  else
+  {
+    /* Disable CE-ATA command. */
+    SDIOx->CMD |= CMD_INTDIS_Set;
+  }
+}
+
+/**
+  * @brief  Sends CE-ATA command (CMD61).
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SendATACmd(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable CE-ATA command. */
+    SDIOx->CMD |= CMD_ATACMD_Set;
+  }
+  else
+  {
+    /* Disable CE-ATA command. */
+    SDIOx->CMD &= CMD_ATACMD_Rst;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified SDIO flag is set or not.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_FLG_CMDFAIL:    Command response received (CRC check failed)
+  *     @arg SDIO_FLG_DTFAIL:     Data block sent/received (CRC check failed)
+  *     @arg SDIO_FLG_CMDTIMEOUT: Command response timeout
+  *     @arg SDIO_FLG_DTTIMEOUT:  Data timeout
+  *     @arg SDIO_FLG_TXERRU:     Transmit FIFO underrun error
+  *     @arg SDIO_FLG_RXERRO:     Received FIFO overrun error
+  *     @arg SDIO_FLG_CMDRSPCMPL: Command response received (CRC check passed)
+  *     @arg SDIO_FLG_CMDCMPL:    Command sent (no response required)
+  *     @arg SDIO_FLG_DTCMPL:     Data end (data counter, SDIDCOUNT, is zero)
+  *     @arg SDIO_FLG_SBITERR:    Start bit not detected on all data signals in wide bus mode.
+  *     @arg SDIO_FLG_DTBLKCMPL:  Data block sent/received (CRC check passed)
+  *     @arg SDIO_FLG_DOCMD:      Command transfer in progress
+  *     @arg SDIO_FLG_DOTX:       Data transmit in progress
+  *     @arg SDIO_FLG_DORX:       Data receive in progress
+  *     @arg SDIO_FLG_TXBUF_H:    Transmit FIFO Half Empty
+  *     @arg SDIO_FLG_RXBUF_H:    Receive FIFO Half Full
+  *     @arg SDIO_FLG_TXBUF_F:    Transmit FIFO full
+  *     @arg SDIO_FLG_RXBUF_F:    Receive FIFO full
+  *     @arg SDIO_FLG_TXBUF_E:    Transmit FIFO empty
+  *     @arg SDIO_FLG_RXBUF_E:    Receive FIFO empty
+  *     @arg SDIO_FLG_TXBUF:      Data available in transmit FIFO
+  *     @arg SDIO_FLG_RXBUF:      Data available in receive FIFO
+  *     @arg SDIO_FLG_SDIOIF:     SD I/O interrupt received
+  *     @arg SDIO_FLG_ATACMPL:    CE-ATA command completion signal received for CMD61
+  * @retval The new state of SDIO_FLAG (SET or RESET).
+  */
+FlagStatus SDIO_GetFlagStatus(SDIO_Type * SDIOx, uint32_t SDIO_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_FLG(SDIO_FLAG));
+
+  if ((SDIOx->STS & SDIO_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SDIO's pending flags.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_FLAG: specifies the flag to clear.
+  *   This parameter can be one or a combination of the following values:
+  *     @arg SDIO_FLG_CMDFAIL:    Command response received (CRC check failed)
+  *     @arg SDIO_FLG_DTFAIL:     Data block sent/received (CRC check failed)
+  *     @arg SDIO_FLG_CMDTIMEOUT: Command response timeout
+  *     @arg SDIO_FLG_DTTIMEOUT:  Data timeout
+  *     @arg SDIO_FLG_TXERRU:     Transmit FIFO underrun error
+  *     @arg SDIO_FLG_RXERRO:     Received FIFO overrun error
+  *     @arg SDIO_FLG_CMDRSPCMPL: Command response received (CRC check passed)
+  *     @arg SDIO_FLG_CMDCMPL:    Command sent (no response required)
+  *     @arg SDIO_FLG_DTCMPL:     Data end (data counter, SDIDCOUNT, is zero)
+  *     @arg SDIO_FLG_SBITERR:    Start bit not detected on all data signals in wide bus mode
+  *     @arg SDIO_FLG_DTBLKCMPL:  Data block sent/received (CRC check passed)
+  *     @arg SDIO_FLG_SDIOIF:     SD I/O interrupt received
+  *     @arg SDIO_FLG_ATACMPL:    CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+void SDIO_ClearFlag(SDIO_Type * SDIOx, uint32_t SDIO_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_CLEAR_FLG(SDIO_FLAG));
+
+  SDIOx->INTCLR = SDIO_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_INT: specifies the SDIO interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_INT_CMDFAIL:    Command response received (CRC check failed) interrupt
+  *     @arg SDIO_INT_DTFAIL:     Data block sent/received (CRC check failed) interrupt
+  *     @arg SDIO_INT_CMDTIMEOUT: Command response timeout interrupt
+  *     @arg SDIO_INT_DTTIMEOUT:  Data timeout interrupt
+  *     @arg SDIO_INT_TXERRU:     Transmit FIFO underrun error interrupt
+  *     @arg SDIO_INT_RXERRO:     Received FIFO overrun error interrupt
+  *     @arg SDIO_INT_CMDRSPCMPL: Command response received (CRC check passed) interrupt
+  *     @arg SDIO_INT_CMDCMPL:    Command sent (no response required) interrupt
+  *     @arg SDIO_INT_DTCMPL:     Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *     @arg SDIO_INT_SBITERR:    Start bit not detected on all data signals in wide bus mode interrupt
+  *     @arg SDIO_INT_DTBLKCMPL:  Data block sent/received (CRC check passed) interrupt
+  *     @arg SDIO_INT_DOCMD:      Command transfer in progress interrupt
+  *     @arg SDIO_INT_DOTX:       Data transmit in progress interrupt
+  *     @arg SDIO_INT_DORX:       Data receive in progress interrupt
+  *     @arg SDIO_INT_TXBUF_H:    Transmit FIFO Half Empty interrupt
+  *     @arg SDIO_INT_RXBUF_H:    Receive FIFO Half Full interrupt
+  *     @arg SDIO_INT_TXBUF_F:    Transmit FIFO full interrupt
+  *     @arg SDIO_INT_RXBUF_F:    Receive FIFO full interrupt
+  *     @arg SDIO_INT_TXBUF_E:    Transmit FIFO empty interrupt
+  *     @arg SDIO_INT_RXBUF_E:    Receive FIFO empty interrupt
+  *     @arg SDIO_INT_TXBUF:      Data available in transmit FIFO interrupt
+  *     @arg SDIO_INT_RXBUF:      Data available in receive FIFO interrupt
+  *     @arg SDIO_INT_SDIOIF:     SD I/O interrupt received interrupt
+  *     @arg SDIO_INT_ATACMPL:    CE-ATA command completion signal received for CMD61 interrupt
+  * @retval The new state of SDIO_INT (SET or RESET).
+  */
+ITStatus SDIO_GetINTStatus(SDIO_Type * SDIOx, uint32_t SDIO_INT)
+{
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_GET_INT(SDIO_INT));
+
+  if ((SDIOx->STS & SDIO_INT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SDIO's interrupt pending bits.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_INT: specifies the interrupt pending bit to clear.
+  *   This parameter can be one or a combination of the following values:
+  *     @arg SDIO_INT_CMDFAIL:    Command response received (CRC check failed) interrupt
+  *     @arg SDIO_INT_DTFAIL:     Data block sent/received (CRC check failed) interrupt
+  *     @arg SDIO_INT_CMDTIMEOUT: Command response timeout interrupt
+  *     @arg SDIO_INT_DTTIMEOUT:  Data timeout interrupt
+  *     @arg SDIO_INT_TXERRU:     Transmit FIFO underrun error interrupt
+  *     @arg SDIO_INT_RXERRO:     Received FIFO overrun error interrupt
+  *     @arg SDIO_INT_CMDRSPCMPL: Command response received (CRC check passed) interrupt
+  *     @arg SDIO_INT_CMDCMPL:    Command sent (no response required) interrupt
+  *     @arg SDIO_INT_DTCMPL:     Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *     @arg SDIO_INT_SBITERR:    Start bit not detected on all data signals in wide bus mode interrupt
+  *     @arg SDIO_INT_SDIOIF:     SD I/O interrupt received interrupt
+  *     @arg SDIO_INT_ATACMPL:    CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+void SDIO_ClearINTPendingBit(SDIO_Type * SDIOx, uint32_t SDIO_INT)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_CLEAR_INT(SDIO_INT));
+
+  SDIOx->INTCLR = SDIO_INT;
+}
+
+/**
+  * @brief  Deinitializes the SDIO peripheral registers to their default reset values.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @retval None
+  */
+void SDIO_Reset(SDIO_Type * SDIOx)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  SDIOx->POWER = 0x00000000;
+  SDIOx->CLKCTRL = 0x00000000;
+  SDIOx->ARG = 0x00000000;
+  SDIOx->CMD = 0x00000000;
+  SDIOx->DTTMR = 0x00000000;
+  SDIOx->DTLEN = 0x00000000;
+  SDIOx->DTCTRL = 0x00000000;
+  SDIOx->INTCLR = 0x00C007FF;
+  SDIOx->INTEN = 0x00000000;
+}
+
+/**
+  * @brief  Initializes the SDIO peripheral according to the specified
+  *         parameters in the SDIO_InitStruct.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_InitStruct : pointer to a SDIO_InitType structure
+  *         that contains the configuration information for the SDIO peripheral.
+  * @retval None
+  */
+void SDIO_Init(SDIO_Type * SDIOx, SDIO_InitType* SDIO_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_CLK_EDGE(SDIO_InitStruct->SDIO_ClkEdge));
+  assert_param(IS_SDIO_CLK_BYPASS(SDIO_InitStruct->SDIO_ClkBypass));
+  assert_param(IS_SDIO_CLK_POWER_SAVE(SDIO_InitStruct->SDIO_ClkPowerSave));
+  assert_param(IS_SDIO_BUS_WIDTH(SDIO_InitStruct->SDIO_BusWidth));
+  assert_param(IS_SDIO_FLOW_CTRL(SDIO_InitStruct->SDIO_FlowCtrl));
+
+  /*---------------------------- SDIO CLKCR Configuration ------------------------*/
+  /* Get the SDIOx CLKCR value */
+  tmpreg = SDIOx->CLKCTRL;
+
+  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
+  tmpreg &= CLKCTRL_CLEAR_MASK;
+
+  /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
+  /* Set BYPASS bit according to SDIO_ClockBypass value */
+  /* Set WIDBUS bits according to SDIO_BusWide value */
+  /* Set NEGEDGE bits according to SDIO_ClockEdge value */
+  /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
+  tmpreg |= (SDIO_InitStruct->SDIO_ClkPowerSave | SDIO_InitStruct->SDIO_ClkBypass |
+             SDIO_InitStruct->SDIO_BusWidth | SDIO_InitStruct->SDIO_ClkEdge | SDIO_InitStruct->SDIO_FlowCtrl);
+
+  /* Set CLKDIV bits according to SDIO_ClockDiv value */
+  tmpreg |= ((SDIO_InitStruct->SDIO_ClkPsc & 0x00FF) | ((SDIO_InitStruct->SDIO_ClkPsc & 0x0300) << 7));
+  /* Write to SDIOx CLKCR */
+  SDIOx->CLKCTRL = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_InitStruct member with its default value.
+  * @param  SDIO_InitStruct: pointer to an SDIO_InitType structure which
+  *   will be initialized.
+  * @retval None
+  */
+void SDIO_StructInit(SDIO_InitType* SDIO_InitStruct)
+{
+  /* SDIO_InitStruct members default value */
+  SDIO_InitStruct->SDIO_ClkPsc = 0x00;
+  SDIO_InitStruct->SDIO_ClkEdge = SDIO_ClkEdge_Rising;
+  SDIO_InitStruct->SDIO_ClkBypass = SDIO_ClkBypass_Disable;
+  SDIO_InitStruct->SDIO_ClkPowerSave = SDIO_ClkPowerSave_Disable;
+  SDIO_InitStruct->SDIO_BusWidth = SDIO_BusWidth_1b;
+  SDIO_InitStruct->SDIO_FlowCtrl = SDIO_FlowCtrl_Disable;
+}
+
+/**
+  * @brief  Enables or disables the SDIO Clock.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_ClockCmd(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the SDIO Clock. */
+    SDIOx->CLKCTRL |= CLKCTRL_CLKEN_Set;
+  }
+  else
+  {
+    /* Disable the SDIO Clock. */
+    SDIOx->CLKCTRL &= CLKCTRL_CLKEN_Rst;
+  }
+}
+
+/**
+  * @brief  Sets the power status of the controller.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_PowerState: new state of the Power state.
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_PowerSave_OFF
+  *     @arg SDIO_PowerSave_ON
+  * @retval None
+  */
+void SDIO_SetPowerSaveState(SDIO_Type * SDIOx, uint32_t SDIO_PowerState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_POWER_SAVE(SDIO_PowerState));
+
+  SDIOx->POWER &= PWR_PWRCTRL_MASK;
+  SDIOx->POWER |= SDIO_PowerState;
+}
+
+/**
+  * @brief  Gets the power status of the controller.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @retval Power status of the controller. The returned value can
+  *   be one of the following:
+  * - 0x00: Power OFF
+  * - 0x02: Power UP
+  * - 0x03: Power ON
+  */
+uint32_t SDIO_GetPowerSaveState(SDIO_Type * SDIOx)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  return (SDIOx->POWER & (~PWR_PWRCTRL_MASK));
+}
+
+/**
+  * @brief  Enables or disables the SDIO interrupts.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_INT: specifies the SDIO interrupt sources to be enabled or disabled.
+  *   This parameter can be one or a combination of the following values:
+  *     @arg SDIO_INT_CMDFAIL:    Command response received (CRC check failed) interrupt
+  *     @arg SDIO_INT_DTFAIL:     Data block sent/received (CRC check failed) interrupt
+  *     @arg SDIO_INT_CMDTIMEOUT: Command response timeout interrupt
+  *     @arg SDIO_INT_DTTIMEOUT:  Data timeout interrupt
+  *     @arg SDIO_INT_TXERRU:     Transmit FIFO underrun error interrupt
+  *     @arg SDIO_INT_RXERRO:     Received FIFO overrun error interrupt
+  *     @arg SDIO_INT_CMDRSPCMPL: Command response received (CRC check passed) interrupt
+  *     @arg SDIO_INT_CMDCMPL:    Command sent (no response required) interrupt
+  *     @arg SDIO_INT_DTCMPL:     Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *     @arg SDIO_INT_SBITERR:    Start bit not detected on all data signals in wide bus mode interrupt
+  *     @arg SDIO_INT_DTBLKCMPL:  Data block sent/received (CRC check passed) interrupt
+  *     @arg SDIO_INT_DOCMD:      Command transfer in progress interrupt
+  *     @arg SDIO_INT_DOTX:       Data transmit in progress interrupt
+  *     @arg SDIO_INT_DORX:       Data receive in progress interrupt
+  *     @arg SDIO_INT_TXBUF_H:    Transmit FIFO Half Empty interrupt
+  *     @arg SDIO_INT_RXBUF_H:    Receive FIFO Half Full interrupt
+  *     @arg SDIO_INT_TXBUF_F:    Transmit FIFO full interrupt
+  *     @arg SDIO_INT_RXBUF_F:    Receive FIFO full interrupt
+  *     @arg SDIO_INT_TXBUF_E:    Transmit FIFO empty interrupt
+  *     @arg SDIO_INT_RXBUF_E:    Receive FIFO empty interrupt
+  *     @arg SDIO_INT_TXBUF:      Data available in transmit FIFO interrupt
+  *     @arg SDIO_INT_RXBUF:      Data available in receive FIFO interrupt
+  *     @arg SDIO_INT_SDIOIF:     SD I/O interrupt received interrupt
+  *     @arg SDIO_INT_ATACMPL:    CE-ATA command completion signal received for CMD61 interrupt
+  * @param  NewState: new state of the specified SDIO interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_INTConfig(SDIO_Type * SDIOx, uint32_t SDIO_INT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_INT(SDIO_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the SDIO interrupts */
+    SDIOx->INTEN |= SDIO_INT;
+  }
+  else
+  {
+    /* Disable the SDIO interrupts */
+    SDIOx->INTEN &= ~SDIO_INT;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SDIO DMA request.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of the selected SDIO DMA request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_DMACmd(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SDIO DMA request. */
+    SDIOx->DTCTRL |= DTCTRL_DMAEN_Set;
+  }
+  else
+  {
+    /* Disable the selected SDIO DMA request. */
+    SDIOx->DTCTRL &= DTCTRL_DMAEN_Rst;
+  }
+}
+
+/**
+  * @brief  Initializes the SDIO Command according to the specified
+  *         parameters in the SDIO_CmdInitStruct and send the command.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_CmdInitStruct : pointer to a SDIO_CmdInitType
+  *         structure that contains the configuration information for the SDIO command.
+  * @retval None
+  */
+void SDIO_SendCommand(SDIO_Type * SDIOx, SDIO_CmdInitType *SDIO_CmdInitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_CMD_IDX(SDIO_CmdInitStruct->SDIO_CmdIdx));
+  assert_param(IS_SDIO_RSP_TYPE(SDIO_CmdInitStruct->SDIO_Resp));
+  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
+  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
+
+  /*---------------------------- SDIOx ARG Configuration ------------------------*/
+  /* Set the SDIOx Argument value */
+  SDIOx->ARG = SDIO_CmdInitStruct->SDIO_Argu;
+
+  /*---------------------------- SDIOx CMD Configuration ------------------------*/
+  /* Get the SDIOx CMD value */
+  tmpreg = SDIOx->CMD;
+  /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
+  tmpreg &= CMD_CLEAR_MASK;
+  /* Set CMDINDEX bits according to SDIO_CmdIndex value */
+  /* Set WAITRESP bits according to SDIO_Response value */
+  /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
+  /* Set CPSMEN bits according to SDIO_CPSM value */
+  tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIdx | SDIO_CmdInitStruct->SDIO_Resp
+            | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
+
+  /* Write to SDIOx CMD */
+  SDIOx->CMD = tmpreg;
+}
+
+
+/**
+  * @}
+  */
+
+#endif /* AT32F403xx || AT32F413xx || AT32F415xx || \
+          AT32F403Axx|| AT32F407xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_spi.c

@@ -0,0 +1,916 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_spi.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx SPI source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_spi.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SPI
+  * @brief SPI driver modules
+  * @{
+  */
+
+/** @defgroup SPI_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_Private_Defines
+  * @{
+  */
+
+/* SPI SPE mask */
+#define CTRL1_SPIEN_SET         ((uint16_t)0x0040)
+#define CTRL1_SPIEN_RESET       ((uint16_t)0xFFBF)
+
+/* I2S I2SE mask */
+#define I2SCTRL_I2SEN_SET       ((uint16_t)0x0400)
+#define I2SCTRL_I2SEN_RESET     ((uint16_t)0xFBFF)
+
+/* SPI CRCNext mask */
+#define CTRL1_CTN_SET           ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CTRL1_CCE_SET           ((uint16_t)0x2000)
+#define CTRL1_CCE_RESET         ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CTRL2_NSSOE_SET         ((uint16_t)0x0004)
+#define CTRL2_NSSOE_RESET       ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CTRL1_CLEAR_MASK        ((uint16_t)0x3040)
+#define I2SCTRL_CLEAR_MASK      ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_MODE_SEL            ((uint16_t)0xF7FF)
+#define I2S_MODE_SEL            ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S2_CLK_SRC            ((uint32_t)(0x00020000))
+#define I2S3_CLK_SRC            ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK            ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK            ((uint32_t)(0x000000F0))
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Checks whether the specified SPI/I2S flag is set or not.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  *   - 2, 3, or 4 in I2S mode
+  * @param  SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_FLAG_TE: Transmit buffer empty flag.
+  *     @arg SPI_I2S_FLAG_RNE: Receive buffer not empty flag.
+  *     @arg SPI_I2S_FLAG_BUSY: Busy flag.
+  *     @arg SPI_I2S_FLAG_OVR: Overrun flag.
+  *     @arg SPI_FLAG_MODF: Mode Fault flag.
+  *     @arg SPI_FLAG_CERR: CRC Error flag.
+  *     @arg I2S_FLAG_UDR: Underrun Error flag.
+  *     @arg I2S_FLAG_CS: Channel Side flag.
+  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
+  */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_Type* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+
+  /* Check the status of the specified SPI/I2S flag */
+  if ((SPIx->STS & SPI_I2S_FLAG) != (uint16_t)RESET)
+  {
+    /* SPI_I2S_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_FLAG is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the SPI_I2S_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx  CRC Error(SPI_FLAG_CERR) flag.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to clear.
+  *   This function clears only CERR flag.This parameter can be as following values:
+  *     @arg SPI_INT_CERR: CRC error interrupt pending bit.
+  * @note
+  *   - SPI_I2S_FLAG_RNE 
+  *     RNE flag is cleared by a read operation to SPI_DT register(SPI_I2S_RxData()).
+  *   - SPI_I2S_FLAG_TE 
+  *     TE flag is cleared by a write operation to SPI_DT register (SPI_I2S_TxData()).
+  *   - I2S_FLAG_CS 
+  *     CS flag is readonly flag,cannot cleared by software.
+  *   - I2S_FLAG_UDR 
+  *     UDR flag is cleared by a read operation to SPI_STS register (SPI_I2S_GetFlagStatus()).
+  *   - SPI_FLAG_CERR
+  *     CERR flag is cleared by software write 0 operation to
+  *     SPI_STS register (SPI_I2S_ClearINTPendingBit()).
+  *   - SPI_FLAG_MODF
+  *     MODF flag is cleared by software sequence:
+  *     a read/write operation to SPI_STS register (SPI_I2S_GetFlagStatus() or SPI_I2S_ClearFlag())
+  *     followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
+  *   - SPI_I2S_FLAG_OVR
+  *     OVR flag is cleared by software sequence:
+  *     a read operation to SPI_DT register (SPI_I2S_RxData())
+  *     followed by a read operation to SPI_STS register (SPI_I2S_GetFlagStatus()).
+  *   - SPI_I2S_FLAG_BUSY
+  *     BUSY flag is readonly flag,cannot cleared by software.
+  * @retval None
+  */
+void SPI_I2S_ClearFlag(SPI_Type* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
+
+  /* Clear the selected SPI CRC Error (CRCERR) flag */
+  SPIx->STS = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  *   - 2, 3, or 4 in I2S mode
+  * @param  SPI_I2S_INT: specifies the SPI/I2S interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_INT_TE: Transmit buffer empty interrupt.
+  *     @arg SPI_I2S_INT_RNE: Receive buffer not empty interrupt.
+  *     @arg SPI_I2S_INT_OVR: Overrun interrupt.
+  *     @arg SPI_INT_MODF: Mode Fault interrupt.
+  *     @arg SPI_INT_CERR: CRC Error interrupt.
+  *     @arg I2S_INT_UDR: Underrun Error interrupt.
+  * @retval The new state of SPI_I2S_INT (SET or RESET).
+  */
+ITStatus SPI_I2S_GetITStatus(SPI_Type* SPIx, uint8_t SPI_I2S_INT)
+{
+  ITStatus bitstatus = RESET;
+  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_INT(SPI_I2S_INT));
+
+  /* Get the SPI/I2S INT index */
+  itpos = 0x01 << (SPI_I2S_INT & 0x0F);
+
+  /* Get the SPI/I2S INT mask */
+  itmask = SPI_I2S_INT >> 4;
+
+  /* Set the INT mask */
+  itmask = 0x01 << itmask;
+
+  /* Get the SPI_I2S_INT enable bit status */
+  enablestatus = (SPIx->CTRL2 & itmask) ;
+
+  /* Check the status of the specified SPI/I2S interrupt */
+  if (((SPIx->STS & itpos) != (uint16_t)RESET) && enablestatus)
+  {
+    /* SPI_I2S_INT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_INT is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the SPI_I2S_INT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx  CRC Error(SPI_INT_CERR) interrupt pending bit.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  * @param  SPI_I2S_INT: specifies the SPI interrupt pending bit to clear.
+  *   This function clears only CERR(SPI_INT_CERR) interrupt pending bit.This 
+  *   parameter can be as following values:
+  *     @arg SPI_INT_CERR: CRC error interrupt pending bit.
+  * @note
+  *   - SPI_INT_CERR
+  *     CERR interrupt pending bit is cleared by software write 0 operation to
+  *     SPI_STS register (SPI_I2S_ClearINTPendingBit()).
+  *   - SPI_I2S_INT_OVR
+  *     OVR interrupt pending bit is cleared by software sequence:
+  *     a read operation to SPI_DT register (SPI_I2S_RxData())
+  *     followed by a read operation to SPI_STS register (SPI_I2S_GetITStatus()).
+  *   - SPI_INT_MODF
+  *     MODF interrupt pending bit is cleared by software sequence:
+  *     a read/write operation to SPI_STS register (SPI_I2S_GetITStatus() or SPI_I2S_ClearINTPendingBit())
+  *     followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
+  *   - I2S_INT_UDR
+  *     UDR interrupt pending bit is cleared by a read operation to SPI_STS register (SPI_I2S_GetITStatus()).
+  * @retval None
+  */
+void SPI_I2S_ClearINTPendingBit(SPI_Type* SPIx, uint8_t SPI_I2S_INT)
+{
+  uint16_t itpos = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_CLEAR_INT(SPI_I2S_INT));
+
+  /* Get the SPI INT index */
+  itpos = 0x01 << (SPI_I2S_INT & 0x0F);
+
+  /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+  SPIx->STS = (uint16_t)~itpos;
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified
+  *         parameters in the I2S_InitStruct.
+  * @param  SPIx: where x can be 2, 3, or 4 to select the SPI peripheral
+  *         (configured in I2S mode).
+  * @param  I2S_InitStruct: pointer to an I2S_InitType structure that
+  *         contains the configuration information for the specified SPI peripheral
+  *         configured in I2S mode.
+  * @note
+  *  The function calculates the optimal prescaler needed to obtain the most
+  *  accurate audio frequency (depending on the I2S clock source, the PLL values
+  *  and the product configuration). But in case the prescaler value is greater
+  *  than 511, the default value (0x02) will be configured instead.  *
+  * @retval None
+  */
+void I2S_Init(SPI_Type* SPIx, I2S_InitType* I2S_InitStruct)
+{
+  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+  uint32_t tmp = 0;
+  RCC_ClockType RCC_Clocks;
+  uint32_t sourceclock = 0;
+
+  /* Check the I2S parameters */
+  assert_param(IS_SPI_I2S_PERIPH(SPIx));
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+  assert_param(IS_I2S_AUDIOPROTOCOL(I2S_InitStruct->I2s_AudioProtocol));
+  assert_param(IS_I2S_FRAMEFORMAT(I2S_InitStruct->I2S_FrameFormat));
+  assert_param(IS_I2S_MCLKOE(I2S_InitStruct->I2S_MCLKOE));
+  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
+
+  /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  SPIx->I2SCTRL &= I2SCTRL_CLEAR_MASK;
+  SPIx->I2SCLKP = 0x0002;
+
+  /* Get the I2SCFGR register value */
+  tmpreg = SPIx->I2SCTRL;
+
+  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+  if(I2S_InitStruct->I2S_AudioFreq == I2S_AUDIOFREQ_DEFAULT)
+  {
+    i2sodd = (uint16_t)0;
+    i2sdiv = (uint16_t)2;
+  }
+  /* If the requested audio frequency is not the default, compute the prescaler */
+  else
+  {
+    /* Check the frame length (For the Prescaler computing) */
+    if(I2S_InitStruct->I2S_FrameFormat == I2S_FRAMEFORMAT_DL16BIT_CHL16BIT)
+    {
+      /* Packet length is 16 bits */
+      packetlength = 1;
+    }
+    else
+    {
+      /* Packet length is 32 bits */
+      packetlength = 2;
+    }
+
+    /* Get the I2S clock source mask depending on the peripheral number */
+    if(((uint32_t)SPIx) == SPI2_BASE)
+    {
+      /* The mask is relative to I2S2 */
+      tmp = I2S2_CLK_SRC;
+    }
+    else
+    {
+      /* The mask is relative to I2S3 */
+      tmp = I2S3_CLK_SRC;
+    }
+
+    /* Check the I2S clock source configuration depending on the Device */
+    /* I2S Clock source is System clock: Get System Clock frequency */
+    RCC_GetClocksFreq(&RCC_Clocks);
+
+    /* Get the source clock value: based on System Clock value */
+    sourceclock = RCC_Clocks.SYSCLK_Freq;
+
+    /* Compute the Real divider depending on the MCLK output state with a floating point */
+    if(I2S_InitStruct->I2S_MCLKOE == I2S_MCLKOE_ENABLE)
+    {
+      /* MCLK output is enabled */
+      tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    else
+    {
+      /* MCLK output is disabled */
+      tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+
+    /* Remove the floating point */
+    tmp = tmp / 10;
+
+    /* Check the parity of the divider */
+    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+    /* Compute the i2sdiv prescaler */
+    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+    i2sodd = (uint16_t) (i2sodd << 8);
+  }
+
+  /* Test if the divider is 1 or 0 or greater than 0xFF */
+  if ((i2sdiv < 2) || (i2sdiv > I2S_DIV_VALUE_MAX))
+  {
+    /* Set the default values */
+    i2sdiv = 2;
+    i2sodd = 0;
+  }
+  else if (i2sdiv & I2S_DIV_EXT_VALUE_MASK)
+  {
+    /* Shift I2SDIV[9:8] to SPI_I2SCLKP[11:10] */
+    i2sdiv |= ((i2sdiv & I2S_DIV_EXT_VALUE_MASK) << I2S_DIV_EXT_VALUE_LSHIFT_OFFSET);
+    i2sdiv &= ~I2S_DIV_EXT_VALUE_MASK;
+  }
+
+  /* Write to SPIx I2SPR register the computed value */
+  SPIx->I2SCLKP = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOE));
+
+  /* Configure the I2S with the SPI_InitStruct values */
+  tmpreg |= (uint16_t)(I2S_MODE_SEL | (uint16_t)(I2S_InitStruct->I2S_Mode | \
+                       (uint16_t)(I2S_InitStruct->I2s_AudioProtocol | (uint16_t)(I2S_InitStruct->I2S_FrameFormat | \
+                                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
+
+  /* Write to SPIx I2SCFGR */
+  SPIx->I2SCTRL = tmpreg;
+}
+
+/**
+  * @brief  Fills each SPI_InitStruct member with its default value.
+  * @param  SPI_InitStruct : pointer to a SPI_InitType structure which will be initialized.
+  * @retval None
+  */
+void SPI_DefaultInitParaConfig(SPI_InitType* SPI_InitStruct)
+{
+  /*--------------- Reset SPI init structure parameters values -----------------*/
+  /* Initialize the SPI_Direction member */
+  SPI_InitStruct->SPI_TransMode = SPI_TRANSMODE_FULLDUPLEX;
+  /* initialize the SPI_Mode member */
+  SPI_InitStruct->SPI_Mode = SPI_MODE_SLAVE;
+  /* initialize the SPI_DataSize member */
+  SPI_InitStruct->SPI_FrameSize = SPI_FRAMESIZE_8BIT;
+  /* Initialize the SPI_CPOL member */
+  SPI_InitStruct->SPI_CPOL = SPI_CPOL_LOW;
+  /* Initialize the SPI_CPHA member */
+  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1EDGE;
+  /* Initialize the SPI_NSS member */
+  SPI_InitStruct->SPI_NSSSEL = SPI_NSSSEL_HARD;
+  /* Initialize the SPI_BaudRatePrescaler member */
+  SPI_InitStruct->SPI_MCLKP = SPI_MCLKP_2;
+  /* Initialize the SPI_FirstBit member */
+  SPI_InitStruct->SPI_FirstBit = SPI_FIRSTBIT_MSB;
+  /* Initialize the SPI_CRCPolynomial member */
+  SPI_InitStruct->SPI_CPOLY = 7;
+}
+
+/**
+  * @brief  Fills each I2S_InitStruct member with its default value.
+  * @param  I2S_InitStruct : pointer to a I2S_InitType structure which will be initialized.
+  * @retval None
+  */
+void I2S_DefaultInit(I2S_InitType* I2S_InitStruct)
+{
+  /*--------------- Reset I2S init structure parameters values -----------------*/
+  /* Initialize the I2S_Mode member */
+  I2S_InitStruct->I2S_Mode = I2S_MODE_SLAVETX;
+
+  /* Initialize the I2S_Standard member */
+  I2S_InitStruct->I2s_AudioProtocol = I2S_AUDIOPROTOCOL_PHILLIPS;
+
+  /* Initialize the I2S_DataFormat member */
+  I2S_InitStruct->I2S_FrameFormat = I2S_FRAMEFORMAT_DL16BIT_CHL16BIT;
+
+  /* Initialize the I2S_MCLKOutput member */
+  I2S_InitStruct->I2S_MCLKOE = I2S_MCLKOE_DISABLE;
+
+  /* Initialize the I2S_AudioFreq member */
+  I2S_InitStruct->I2S_AudioFreq = I2S_AUDIOFREQ_DEFAULT;
+
+  /* Initialize the I2S_CPOL member */
+  I2S_InitStruct->I2S_CPOL = I2S_CPOL_LOW;
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_Enable(SPI_Type* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral */
+    SPIx->CTRL1 |= CTRL1_SPIEN_SET;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral */
+    SPIx->CTRL1 &= CTRL1_SPIEN_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
+  * @param  SPIx: where x can be 2, 3, or 4 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2S_Enable(SPI_Type* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_I2S_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral (in I2S mode) */
+    SPIx->I2SCTRL |= I2SCTRL_I2SEN_SET;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral (in I2S mode) */
+    SPIx->I2SCTRL &= I2SCTRL_I2SEN_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI/I2S interrupts.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  *   - 2, 3, or 4 in I2S mode
+  * @param  SPI_I2S_INT: specifies the SPI/I2S interrupt source to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_INT_TE: Tx buffer empty interrupt mask
+  *     @arg SPI_I2S_INT_RNE: Rx buffer not empty interrupt mask
+  *     @arg SPI_I2S_INT_ERR: Error interrupt mask
+  * @param  NewState: new state of the specified SPI/I2S interrupt.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_INTConfig(SPI_Type* SPIx, uint8_t SPI_I2S_INT, FunctionalState NewState)
+{
+  uint16_t itpos = 0, itmask = 0 ;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_CONFIG_INT(SPI_I2S_INT));
+
+  /* Get the SPI/I2S INT index */
+  itpos = SPI_I2S_INT >> 4;
+
+  /* Set the INT mask */
+  itmask = (uint16_t)1 << (uint16_t)itpos;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI/I2S interrupt */
+    SPIx->CTRL2 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected SPI/I2S interrupt */
+    SPIx->CTRL2 &= (uint16_t)~itmask;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  *   - 2, 3, or 4 in I2S mode
+  * @param  SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg SPI_I2S_DMA_TX: Tx buffer DMA transfer request
+  *     @arg SPI_I2S_DMA_RX: Rx buffer DMA transfer request
+  * @param  NewState: new state of the selected SPI/I2S DMA transfer request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_DMAEnable(SPI_Type* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_DMA(SPI_I2S_DMAReq));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI/I2S DMA requests */
+    SPIx->CTRL2 |= SPI_I2S_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected SPI/I2S DMA requests */
+    SPIx->CTRL2 &= (uint16_t)~SPI_I2S_DMAReq;
+  }
+}
+
+/**
+  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  *   - 2, 3, or 4 in I2S mode
+  * @param  Data : Data to be transmitted.
+  * @retval None
+  */
+void SPI_I2S_TxData(SPI_Type* SPIx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Write in the DR register the data to be sent */
+  SPIx->DT = Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  *   - 2, 3, or 4 in I2S mode
+  * @retval The value of the received data.
+  */
+uint16_t SPI_I2S_RxData(SPI_Type* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Return the data in the DR register */
+  return SPIx->DT;
+}
+
+/**
+  * @brief  Configures internally by software the NSS pin for the selected SPI.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_ISS_SET: Set NSS pin internally
+  *     @arg SPI_ISS_RESET: Reset NSS pin internally
+  * @retval None
+  */
+void SPI_NSSInternalSoftwareConfig(SPI_Type* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_ISS(SPI_NSSInternalSoft));
+
+  if (SPI_NSSInternalSoft != SPI_ISS_RESET)
+  {
+    /* Set NSS pin internally by software */
+    SPIx->CTRL1 |= SPI_ISS_SET;
+  }
+  else
+  {
+    /* Reset NSS pin internally by software */
+    SPIx->CTRL1 &= SPI_ISS_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SS output for the selected SPI.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx SS output.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_NSSHardwareOutputEnable(SPI_Type* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI SS output */
+    SPIx->CTRL2 |= CTRL2_NSSOE_SET;
+  }
+  else
+  {
+    /* Disable the selected SPI SS output */
+    SPIx->CTRL2 &= CTRL2_NSSOE_RESET;
+  }
+}
+
+/**
+  * @brief  Configures the data size for the selected SPI.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  SPI_DataSize: specifies the SPI data size.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_FRAMESIZE_16BIT: Set data frame format to 16bit
+  *     @arg SPI_FRAMESIZE_8BIT: Set data frame format to 8bit
+  * @retval None
+  */
+void SPI_FrameSizeConfig(SPI_Type* SPIx, uint16_t SPI_DataSize)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_FRAMESIZE(SPI_DataSize));
+  /* Clear DFF bit */
+  SPIx->CTRL1 &= (uint16_t)~SPI_FRAMESIZE_16BIT;
+  /* Set new DFF bit value */
+  SPIx->CTRL1 |= SPI_DataSize;
+}
+
+/**
+  * @brief  Transmit the SPIx CRC value.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @retval None
+  */
+void SPI_TxCRC(SPI_Type* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Enable the selected SPI CRC transmission */
+  SPIx->CTRL1 |= CTRL1_CTN_SET;
+}
+
+/**
+  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx CRC value calculation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_CRCEN(SPI_Type* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI CRC calculation */
+    SPIx->CTRL1 |= CTRL1_CCE_SET;
+  }
+  else
+  {
+    /* Disable the selected SPI CRC calculation */
+    SPIx->CTRL1 &= CTRL1_CCE_RESET;
+  }
+}
+
+/**
+  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  SPI_CRC: specifies the CRC register to be read.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_CRC_TX: Selects Tx CRC register
+  *     @arg SPI_CRC_RX: Selects Rx CRC register
+  * @retval The selected CRC register value..
+  */
+uint16_t SPI_GetCRC(SPI_Type* SPIx, uint8_t SPI_CRC)
+{
+  uint16_t crcreg = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CRC(SPI_CRC));
+
+  if (SPI_CRC != SPI_CRC_RX)
+  {
+    /* Get the Tx CRC register */
+    crcreg = SPIx->TCRC;
+  }
+  else
+  {
+    /* Get the Rx CRC register */
+    crcreg = SPIx->RCRC;
+  }
+
+  /* Return the selected CRC register */
+  return crcreg;
+}
+
+/**
+  * @brief  Returns the CRC Polynomial register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @retval The CRC Polynomial register value.
+  */
+uint16_t SPI_GetCRCPolynomial(SPI_Type* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Return the CRC polynomial register */
+  return SPIx->CPOLY;
+}
+
+/**
+  * @brief  Selects the data transfer direction in bi-directional mode for the specified SPI.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  SPI_Direction: specifies the data transfer direction in bi-directional mode.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_HALFDUPLEX_TX: Selects Tx transmission direction
+  *     @arg SPI_HALFDUPLEX_RX: Selects Rx receive direction
+  * @retval None
+  */
+void SPI_HalfDuplexTransModeConfig(SPI_Type* SPIx, uint16_t SPI_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DIRECTION(SPI_Direction));
+
+  if (SPI_Direction == SPI_HALFDUPLEX_TX)
+  {
+    /* Set the Tx only mode */
+    SPIx->CTRL1 |= SPI_HALFDUPLEX_TX;
+  }
+  else
+  {
+    /* Set the Rx only mode */
+    SPIx->CTRL1 &= SPI_HALFDUPLEX_RX;
+  }
+}
+
+/**
+  * @brief  Deinitializes the SPIx peripheral registers to their default
+  *         reset values (Affects also the I2Ss).
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @retval None
+  */
+void SPI_I2S_Reset(SPI_Type* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  if (SPIx == SPI1)
+  {
+    /* Enable SPI1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_SPI1, ENABLE);
+    /* Release SPI1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_SPI1, DISABLE);
+  }
+  else if (SPIx == SPI2)
+  {
+    /* Enable SPI2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_SPI2, ENABLE);
+    /* Release SPI2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_SPI2, DISABLE);
+  }
+#if defined (AT32F403xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+  else if (SPIx == SPI3)
+  {
+    /* Enable SPI3 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_SPI3, ENABLE);
+    /* Release SPI3 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_SPI3, DISABLE);
+  }
+  else if (SPIx == SPI4)
+  {
+    /* Enable SPI4 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_SPI4, ENABLE);
+    /* Release SPI4 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_SPI4, DISABLE);
+  }
+#endif
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified
+  *         parameters in the SPI_InitStruct.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  SPI_InitStruct: pointer to a SPI_InitType structure that
+  *         contains the configuration information for the specified SPI peripheral.
+  * @retval None
+  */
+void SPI_Init(SPI_Type* SPIx, SPI_InitType* SPI_InitStruct)
+{
+  uint16_t tmpreg = 0;
+
+  /* check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Check the SPI parameters */
+  assert_param(IS_SPI_TRANS_MODE(SPI_InitStruct->SPI_TransMode));
+  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+  assert_param(IS_SPI_FRAMESIZE(SPI_InitStruct->SPI_FrameSize));
+  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+  assert_param(IS_SPI_NSSSEL(SPI_InitStruct->SPI_NSSSEL));
+  assert_param(IS_SPI_MCLKP(SPI_InitStruct->SPI_MCLKP));
+  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+  assert_param(IS_SPI_CPOLY(SPI_InitStruct->SPI_CPOLY));
+
+  /*---------------------------- SPIx CTRL1 Configuration ------------------------*/
+  /* Get the SPIx CTRL1 value */
+  tmpreg = SPIx->CTRL1;
+  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+  tmpreg &= CTRL1_CLEAR_MASK;
+  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+     master/salve mode, CPOL and CPHA */
+  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+  /* Set LSBFirst bit according to SPI_FirstBit value */
+  /* Set BR bits according to SPI_BaudRatePrescaler value */
+  /* Set CPOL bit according to SPI_CPOL value */
+  /* Set CPHA bit according to SPI_CPHA value */
+
+  if (SPI_InitStruct->SPI_MCLKP & SPI_MCLKP_OVER_256)
+  {
+    /* MCLKP is over 256 */
+    SPIx->CTRL2 |= SPI_CTRL2_MCLKP_3;
+  }
+  else
+  {
+    SPIx->CTRL2 &= ~SPI_CTRL2_MCLKP_3;
+  }
+
+  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_TransMode | SPI_InitStruct->SPI_Mode |
+                       SPI_InitStruct->SPI_FrameSize | SPI_InitStruct->SPI_CPOL |
+                       SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSSSEL |
+                       (SPI_InitStruct->SPI_MCLKP & 0x7FFF) | SPI_InitStruct->SPI_FirstBit);
+  /* Write to SPIx CTRL1 */
+  SPIx->CTRL1 = tmpreg;
+
+
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+  SPIx->I2SCTRL &= SPI_MODE_SEL;
+
+  /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+  /* Write to SPIx CRCPOLY */
+  SPIx->CPOLY = SPI_InitStruct->SPI_CPOLY;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_syscfg.c

@@ -0,0 +1,186 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_syscfg.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx syscfg source file
+  **************************************************************************
+  */
+
+#include "at32f4xx_syscfg.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+#if defined (AT32F421xx)
+
+/** @defgroup SYSCFG 
+  * @brief SYSCFG driver modules
+  * @{
+  */
+
+/** @defgroup SYSCFG_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SYSCFG registers to their default reset values.
+  * @param  None
+  * @retval None
+  * @note   MEM_MODE bits are not affected by APB reset.
+  * @note   MEM_MODE bits took the value from the user option bytes.
+  * @note   CFGR2 register is not affected by APB reset.
+  * @note   CLABBB configuration bits are locked when set.
+  * @note   To unlock the configuration, perform a system reset.
+  */
+void SYSCFG_DeInit(void)
+{
+  /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
+  SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
+  /* Set EXTICRx registers to reset value */
+  SYSCFG->EXTICR[0] = 0;
+  SYSCFG->EXTICR[1] = 0;
+  SYSCFG->EXTICR[2] = 0;
+  SYSCFG->EXTICR[3] = 0;
+}
+
+/**
+  * @brief  Configures the memory mapping at address 0x00000000.
+  * @param  SYSCFG_MemoryRemap: selects the memory remapping.
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000  
+  *            @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
+  *            @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
+  * @retval None
+  */
+void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
+{
+  uint32_t tmpctrl = 0;
+
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
+
+  /* Get CFGR1 register value */
+  tmpctrl = SYSCFG->CFGR1;
+
+  /* Clear MEM_MODE bits */
+  tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
+
+  /* Set the new MEM_MODE bits value */
+  tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
+
+  /* Set CFGR1 register with the new memory remap configuration */
+  SYSCFG->CFGR1 = tmpctrl;
+}
+
+/**
+  * @brief  Configure the DMA channels remapping.
+  * @param  SYSCFG_DMARemap: selects the DMA channels remap.
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2
+  *            @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4
+  *            @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5
+  *            @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4
+  *            @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2
+  * @param  NewState: new state of the DMA channel remapping. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   When enabled, DMA channel of the selected peripheral is remapped
+  * @note   When disabled, Default DMA channel is mapped to the selected peripheral
+  * @note   By default TIM17 DMA requests is mapped to channel 1, 
+  *         use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap
+  *         TIM17 DMA requests to channel 2 and use
+  *         SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map
+  *         TIM17 DMA requests to channel 1 (default mapping)
+  * @retval None
+  */
+void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Remap the DMA channel */
+    SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
+  }
+  else
+  {
+    /* use the default DMA channel mapping */
+    SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
+  }
+}
+
+/**
+  * @brief  Selects the GPIO pin used as EXTI Line.
+  * @param  EXTI_PortSourceGPIOx: selects the GPIO port to be used as source 
+  *                               for EXTI lines where x can be (A, B, C, D or F).
+  * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
+  *         This parameter can be EXTI_PinSourcex where x can be (0..15)
+  * @retval None
+  */
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
+{
+  uint32_t tmp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
+  assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
+  
+  tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
+}
+
+/**
+  * @brief  Selects the IRTMR_Mode for IRTMR.
+  * @param  IRTMR_Mode: The mode for IRTMR.
+  * @param  IR_Pol    : The polarity for IRTMR output.
+  * @retval None
+  */
+void SYSCFG_IRTMRConfig(uint32_t IRTMR_Mode,uint32_t IR_Pol)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_IRTMR_MODE(IRTMR_Mode));
+  assert_param(IS_SYSCFG_IRTMR_POL(IR_Pol));
+  
+  SYSCFG->CFGR1 |= (uint32_t)((uint32_t)IRTMR_Mode | (uint32_t)IR_Pol);
+}
+
+/**
+  * @brief  PA11 and PA12 remapping bit only for small packages (28 and 20 pins).
+  * @param  NewState: new state of GPIO(PA11 and PA12) remapping. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SYSCFG_GPIORemapConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Remap GPIO */
+    SYSCFG->CFGR1 |= (uint32_t)(SYSCFG_GPIORemap_PA11_PA12);
+  }
+  else
+  {
+    /* use the default GPIO */
+    SYSCFG->CFGR1 &= (uint32_t)(~(SYSCFG_GPIORemap_PA11_PA12));
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#endif /* AT32F421xx */
+
+/**
+  * @}
+  */

StdPeriph_Driver/src/at32f4xx_wwdg.c

@@ -0,0 +1,214 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_wwdg.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx WWDG source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_wwdg.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup WWDG
+  * @brief WWDG driver modules
+  * @{
+  */
+
+/** @defgroup WWDG_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_Defines
+  * @{
+  */
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFSET         (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFG_OFFSET          (WWDG_OFFSET + 0x04)
+#define EWIEN_BitPos        0x09
+#define CFG_EWIEN_BBMAP     (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (EWIEN_BitPos * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CTRL_EN_Set         ((uint32_t)0x00000080)
+
+/* CFR register bit mask */
+#define CFG_PSC_Mask        ((uint32_t)0xFFFFFE7F)
+#define CFG_WCNTR_Mask      ((uint32_t)0xFFFFFF80)
+#define BIT_Mask            ((uint8_t)0x7F)
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Enables WWDG and load the counter value.
+  * @param  Counter: specifies the watchdog counter value.
+  *   This parameter must be a number between 0x40 and 0x7F.
+  * @retval None
+  */
+void WWDG_Enable(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_CNTR(Counter));
+  WWDG->CTRL = CTRL_EN_Set | Counter;
+}
+
+/**
+  * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
+  * @param  None
+  * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
+  */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+  return (FlagStatus)(WWDG->STS);
+}
+
+/**
+  * @brief  Clears Early Wakeup interrupt flag.
+  * @param  None
+  * @retval None
+  */
+void WWDG_ClearFlag(void)
+{
+  WWDG->STS = (uint32_t)RESET;
+}
+
+/**
+  * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void WWDG_Reset(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_WWDG, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_WWDG, DISABLE);
+}
+
+/**
+  * @brief  Sets the WWDG Prescaler.
+  * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg WWDG_Psc_1: WWDG counter clock = (PCLK1/4096)/1
+  *     @arg WWDG_Psc_2: WWDG counter clock = (PCLK1/4096)/2
+  *     @arg WWDG_Psc_4: WWDG counter clock = (PCLK1/4096)/4
+  *     @arg WWDG_Psc_8: WWDG counter clock = (PCLK1/4096)/8
+  * @retval None
+  */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_WWDG_PSC(WWDG_Prescaler));
+  /* Clear WDGTB[1:0] bits */
+  tmpreg = WWDG->CFG & CFG_PSC_Mask;
+  /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+  tmpreg |= WWDG_Prescaler;
+  /* Store the new value */
+  WWDG->CFG = tmpreg;
+}
+
+/**
+  * @brief  Sets the WWDG window value.
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
+  *   This parameter value must be lower than 0x80.
+  * @retval None
+  */
+void WWDG_SetWindowCounter(uint8_t WindowValue)
+{
+  __IO uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_WWDG_WCNTR(WindowValue));
+  /* Clear W[6:0] bits */
+
+  tmpreg = WWDG->CFG & CFG_WCNTR_Mask;
+
+  /* Set W[6:0] bits according to WindowValue value */
+  tmpreg |= WindowValue & (uint32_t) BIT_Mask;
+
+  /* Store the new value */
+  WWDG->CFG = tmpreg;
+}
+
+/**
+  * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
+  * @param  None
+  * @retval None
+  */
+void WWDG_EnableINT(void)
+{
+  *(__IO uint32_t *) CFG_EWIEN_BBMAP = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Sets the WWDG counter value.
+  * @param  Counter: specifies the watchdog counter value.
+  *   This parameter must be a number between 0x40 and 0x7F.
+  * @retval None
+  */
+void WWDG_SetCounter(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_CNTR(Counter));
+  /* Write to T[6:0] bits to configure the counter value, no need to do
+     a read-modify-write; writing a 0 to WDGA bit does nothing */
+  WWDG->CTRL = Counter & BIT_Mask;
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/at32f4xx_xmc.c

@@ -0,0 +1,884 @@
+/**
+  **************************************************************************
+  * File   : at32f4xx_xmc.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx XMC source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_xmc.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup XMC
+  * @brief XMC driver modules
+  * @{
+  */
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+
+/** @defgroup XMC_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Private_Defines
+  * @{
+  */
+
+/* --------------------- XMC registers bit mask ---------------------------- */
+
+/* XMC BCRx Mask */
+#define BK1CTRLx_EN_Set                     ((uint32_t)0x00000001)
+#define BK1CTRLx_EN_Reset                   ((uint32_t)0x000FFFFE)
+#define BK1CTRLx_NOREN_Set                  ((uint32_t)0x00000040)
+
+/* XMC PCRx Mask */
+#define BKxCTRL_EN_Set                      ((uint32_t)0x00000004)
+#define BKxCTRL_EN_Reset                    ((uint32_t)0x000FFFFB)
+#define BKxCTRL_ECCEN_Set                   ((uint32_t)0x00000040)
+#define BKxCTRL_ECCEN_Reset                 ((uint32_t)0x000FFFBF)
+#define BKxCTRL_Device_NAND                 ((uint32_t)0x00000008)
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the PCCARD Memory Bank.
+  * @param  NewState: new state of the PCCARD Memory Bank.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void XMC_PCCARDCmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
+    XMC_Bank4->BK4CTRL |= BKxCTRL_EN_Set;
+  }
+  else
+  {
+    /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
+    XMC_Bank4->BK4CTRL &= BKxCTRL_EN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the XMC NAND ECC feature.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  * @param  NewState: new state of the XMC NAND ECC feature.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void XMC_NANDECCCmd(uint32_t XMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_XMC_NAND_BANK(XMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
+    if(XMC_Bank == XMC_Bank2_NAND)
+    {
+      XMC_Bank2->BK2CTRL |= BKxCTRL_ECCEN_Set;
+    }
+    else
+    {
+      XMC_Bank3->BK3CTRL |= BKxCTRL_ECCEN_Set;
+    }
+  }
+  else
+  {
+    /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
+    if(XMC_Bank == XMC_Bank2_NAND)
+    {
+      XMC_Bank2->BK2CTRL &= BKxCTRL_ECCEN_Reset;
+    }
+    else
+    {
+      XMC_Bank3->BK3CTRL &= BKxCTRL_ECCEN_Reset;
+    }
+  }
+}
+
+/**
+  * @brief  Returns the error correction code register value.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  * @retval The Error Correction Code (ECC) value.
+  */
+uint32_t XMC_GetECC(uint32_t XMC_Bank)
+{
+  uint32_t eccval = 0x00000000;
+
+  if(XMC_Bank == XMC_Bank2_NAND)
+  {
+    /* Get the BK2ECC register value */
+    eccval = XMC_Bank2->BK2ECC;
+  }
+  else
+  {
+    /* Get the BK3ECC register value */
+    eccval = XMC_Bank3->BK3ECC;
+  }
+
+  /* Return the error correction code value */
+  return(eccval);
+}
+
+/**
+  * @brief  Enables or disables the specified XMC interrupts.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  *     @arg XMC_Bank4_PCCARD: XMC Bank4 PCCARD
+  * @param  XMC_INT: specifies the XMC interrupt sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg XMC_INT_RisingEdge: Rising edge detection interrupt.
+  *     @arg XMC_INT_Level: Level edge detection interrupt.
+  *     @arg XMC_INT_FallingEdge: Falling edge detection interrupt.
+  * @param  NewState: new state of the specified XMC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void XMC_INTConfig(uint32_t XMC_Bank, uint32_t XMC_INT, FunctionalState NewState)
+{
+  assert_param(IS_XMC_INT_BANK(XMC_Bank));
+  assert_param(IS_XMC_INT(XMC_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected XMC_Bank2 interrupts */
+    if(XMC_Bank == XMC_Bank2_NAND)
+    {
+      XMC_Bank2->BK2STS |= XMC_INT;
+    }
+    /* Enable the selected XMC_Bank3 interrupts */
+    else if (XMC_Bank == XMC_Bank3_NAND)
+    {
+      XMC_Bank3->BK3STS |= XMC_INT;
+    }
+    /* Enable the selected XMC_Bank4 interrupts */
+    else
+    {
+      XMC_Bank4->BK4STS |= XMC_INT;
+    }
+  }
+  else
+  {
+    /* Disable the selected XMC_Bank2 interrupts */
+    if(XMC_Bank == XMC_Bank2_NAND)
+    {
+
+      XMC_Bank2->BK2STS &= (uint32_t)~XMC_INT;
+    }
+    /* Disable the selected XMC_Bank3 interrupts */
+    else if (XMC_Bank == XMC_Bank3_NAND)
+    {
+      XMC_Bank3->BK3STS &= (uint32_t)~XMC_INT;
+    }
+    /* Disable the selected XMC_Bank4 interrupts */
+    else
+    {
+      XMC_Bank4->BK4STS &= (uint32_t)~XMC_INT;
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified XMC flag is set or not.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  *     @arg XMC_Bank4_PCCARD: XMC Bank4 PCCARD
+  * @param  XMC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg XMC_FLAG_RisingEdge: Rising egde detection Flag.
+  *     @arg XMC_FLAG_Level: Level detection Flag.
+  *     @arg XMC_FLAG_FallingEdge: Falling egde detection Flag.
+  *     @arg XMC_FLAG_FEMPT: Fifo empty Flag.
+  * @retval The new state of XMC_FLAG (SET or RESET).
+  */
+FlagStatus XMC_GetFlagStatus(uint32_t XMC_Bank, uint32_t XMC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpsr = 0x00000000;
+
+  /* Check the parameters */
+  assert_param(IS_XMC_GETFLAG_BANK(XMC_Bank));
+  assert_param(IS_XMC_GET_FLAG(XMC_FLAG));
+
+  if(XMC_Bank == XMC_Bank2_NAND)
+  {
+    tmpsr = XMC_Bank2->BK2STS;
+  }
+  else if(XMC_Bank == XMC_Bank3_NAND)
+  {
+    tmpsr = XMC_Bank3->BK3STS;
+  }
+  /* XMC_Bank4_PCCARD*/
+  else
+  {
+    tmpsr = XMC_Bank4->BK4STS;
+  }
+
+  /* Get the flag status */
+  if ((tmpsr & XMC_FLAG) != (uint16_t)RESET )
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the XMC's pending flags.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  *     @arg XMC_Bank4_PCCARD: XMC Bank4 PCCARD
+  * @param  XMC_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg XMC_FLAG_RisingEdge: Rising egde detection Flag.
+  *     @arg XMC_FLAG_Level: Level detection Flag.
+  *     @arg XMC_FLAG_FallingEdge: Falling egde detection Flag.
+  * @retval None
+  */
+void XMC_ClearFlag(uint32_t XMC_Bank, uint32_t XMC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_XMC_GETFLAG_BANK(XMC_Bank));
+  assert_param(IS_XMC_CLEAR_FLAG(XMC_FLAG)) ;
+
+  if(XMC_Bank == XMC_Bank2_NAND)
+  {
+    XMC_Bank2->BK2STS &= ~XMC_FLAG;
+  }
+  else if(XMC_Bank == XMC_Bank3_NAND)
+  {
+    XMC_Bank3->BK3STS &= ~XMC_FLAG;
+  }
+  /* XMC_Bank4_PCCARD*/
+  else
+  {
+    XMC_Bank4->BK4STS &= ~XMC_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified XMC interrupt has occurred or not.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  *     @arg XMC_Bank4_PCCARD: XMC Bank4 PCCARD
+  * @param  XMC_INT: specifies the XMC interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg XMC_INT_RisingEdge: Rising edge detection interrupt.
+  *     @arg XMC_INT_Level: Level edge detection interrupt.
+  *     @arg XMC_INT_FallingEdge: Falling edge detection interrupt.
+  * @retval The new state of XMC_INT (SET or RESET).
+  */
+ITStatus XMC_GetINTStatus(uint32_t XMC_Bank, uint32_t XMC_INT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_XMC_INT_BANK(XMC_Bank));
+  assert_param(IS_XMC_GET_INT(XMC_INT));
+
+  if(XMC_Bank == XMC_Bank2_NAND)
+  {
+    tmpsr = XMC_Bank2->BK2STS;
+  }
+  else if(XMC_Bank == XMC_Bank3_NAND)
+  {
+    tmpsr = XMC_Bank3->BK3STS;
+  }
+  /* XMC_Bank4_PCCARD*/
+  else
+  {
+    tmpsr = XMC_Bank4->BK4STS;
+  }
+
+  itstatus = tmpsr & XMC_INT;
+
+  itenable = tmpsr & (XMC_INT >> 3);
+
+  if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the XMC's interrupt pending bits.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  *     @arg XMC_Bank4_PCCARD: XMC Bank4 PCCARD
+  * @param  XMC_INT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg XMC_INT_RisingEdge: Rising edge detection interrupt.
+  *     @arg XMC_INT_Level: Level edge detection interrupt.
+  *     @arg XMC_INT_FallingEdge: Falling edge detection interrupt.
+  * @retval None
+  */
+void XMC_ClearINTPendingBit(uint32_t XMC_Bank, uint32_t XMC_INT)
+{
+  /* Check the parameters */
+  assert_param(IS_XMC_INT_BANK(XMC_Bank));
+  assert_param(IS_XMC_INT(XMC_INT));
+
+  if(XMC_Bank == XMC_Bank2_NAND)
+  {
+    XMC_Bank2->BK2STS &= ~(XMC_INT >> 3);
+  }
+  else if(XMC_Bank == XMC_Bank3_NAND)
+  {
+    XMC_Bank3->BK3STS &= ~(XMC_INT >> 3);
+  }
+  /* XMC_Bank4_PCCARD*/
+  else
+  {
+    XMC_Bank4->BK4STS &= ~(XMC_INT >> 3);
+  }
+}
+
+/**
+  * @brief  Initializes the XMC NOR/SRAM Banks according to the specified
+  *         parameters in the XMC_NORSRAMInitStruct.
+  * @param  XMC_NORSRAMInitStruct : pointer to a XMC_NORSRAMInitType
+  *         structure that contains the configuration information for
+  *        the XMC NOR/SRAM specified Banks.
+  * @retval None
+  */
+void XMC_NORSRAMInit(XMC_NORSRAMInitType* XMC_NORSRAMInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_XMC_NORSRAM_REGION(XMC_NORSRAMInitStruct->XMC_Bank));
+  assert_param(IS_XMC_MUX(XMC_NORSRAMInitStruct->XMC_DataAdrMux));
+  assert_param(IS_XMC_DEVICE(XMC_NORSRAMInitStruct->XMC_Dev));
+  assert_param(IS_XMC_BUS_TYPE(XMC_NORSRAMInitStruct->XMC_BusType));
+  assert_param(IS_XMC_BURSTMODE(XMC_NORSRAMInitStruct->XMC_EnableBurstMode));
+  assert_param(IS_XMC_ASYNWAIT(XMC_NORSRAMInitStruct->XMC_EnableAsynWait));
+  assert_param(IS_XMC_WAIT_SIGNAL_LEVEL(XMC_NORSRAMInitStruct->XMC_WaitSignalLv));
+  assert_param(IS_XMC_BURSTMODE_SPLIT(XMC_NORSRAMInitStruct->XMC_EnableBurstModeSplit));
+  assert_param(IS_XMC_WAIT_SIGNAL_CONFIG(XMC_NORSRAMInitStruct->XMC_WaitSignalConfig));
+  assert_param(IS_XMC_WRITE_OPERATION(XMC_NORSRAMInitStruct->XMC_EnableWrite));
+  assert_param(IS_XMC_WAIT_SIGNAL(XMC_NORSRAMInitStruct->XMC_EnableWaitSignal));
+  assert_param(IS_XMC_WRITE_TIMING(XMC_NORSRAMInitStruct->XMC_EnableWriteTiming));
+  assert_param(IS_XMC_WRITE_BURST_SYN(XMC_NORSRAMInitStruct->XMC_WriteBurstSyn));
+  assert_param(IS_XMC_ADDRESS_OP_TIME(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_AdrOpTime));
+  assert_param(IS_XMC_ADDRESS_HOLD_TIME(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_AdrHoldTime));
+  assert_param(IS_XMC_DATA_OP_TIME(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_DataOpTime));
+  assert_param(IS_XMC_INTERVAL_BETWEEN_OP_TIME(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_IntervalBetweenOP));
+  assert_param(IS_XMC_CLK_DIV(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_CLKPsc));
+  assert_param(IS_XMC_DATA_STABLE_TIME(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_DataStableTime));
+  assert_param(IS_XMC_MODE(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_Mode));
+
+  /* Bank1 NOR/SRAM control register configuration */
+  XMC_Bank1->BK1CTRLR[XMC_NORSRAMInitStruct->XMC_Bank] =
+    (uint32_t)XMC_NORSRAMInitStruct->XMC_DataAdrMux |
+    XMC_NORSRAMInitStruct->XMC_Dev |
+    XMC_NORSRAMInitStruct->XMC_BusType |
+    XMC_NORSRAMInitStruct->XMC_EnableBurstMode |
+    XMC_NORSRAMInitStruct->XMC_EnableAsynWait |
+    XMC_NORSRAMInitStruct->XMC_WaitSignalLv |
+    XMC_NORSRAMInitStruct->XMC_EnableBurstModeSplit |
+    XMC_NORSRAMInitStruct->XMC_WaitSignalConfig |
+    XMC_NORSRAMInitStruct->XMC_EnableWrite |
+    XMC_NORSRAMInitStruct->XMC_EnableWaitSignal |
+    XMC_NORSRAMInitStruct->XMC_EnableWriteTiming |
+    XMC_NORSRAMInitStruct->XMC_WriteBurstSyn;
+
+  if(XMC_NORSRAMInitStruct->XMC_Dev == XMC_Dev_NOR)
+  {
+    XMC_Bank1->BK1CTRLR[XMC_NORSRAMInitStruct->XMC_Bank] |= (uint32_t)BK1CTRLx_NOREN_Set;
+  }
+
+  /* Bank1 NOR/SRAM timing register configuration */
+  XMC_Bank1->BK1CTRLR[XMC_NORSRAMInitStruct->XMC_Bank + 1] =
+    (uint32_t)XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_AdrOpTime |
+    (XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_AdrHoldTime << 4) |
+    (XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_DataOpTime << 8) |
+    (XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_IntervalBetweenOP << 16) |
+    (XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_CLKPsc << 20) |
+    (XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_DataStableTime << 24) |
+    XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_Mode;
+
+
+  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
+  if(XMC_NORSRAMInitStruct->XMC_EnableWriteTiming == XMC_WriteTiming_Enable)
+  {
+    assert_param(IS_XMC_ADDRESS_OP_TIME(XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_AdrOpTime));
+    assert_param(IS_XMC_ADDRESS_HOLD_TIME(XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_AdrHoldTime));
+    assert_param(IS_XMC_DATA_OP_TIME(XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_DataOpTime));
+    assert_param(IS_XMC_CLK_DIV(XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_CLKPsc));
+    assert_param(IS_XMC_DATA_STABLE_TIME(XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_DataStableTime));
+    assert_param(IS_XMC_MODE(XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_Mode));
+    XMC_Bank1E->BK1TMGWR[XMC_NORSRAMInitStruct->XMC_Bank] =
+      (uint32_t)XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_AdrOpTime |
+      (XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_AdrHoldTime << 4 ) |
+      (XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_DataOpTime << 8) |
+      (XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_CLKPsc << 20) |
+      (XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_DataStableTime << 24) |
+      XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_Mode;
+  }
+  else
+  {
+    XMC_Bank1E->BK1TMGWR[XMC_NORSRAMInitStruct->XMC_Bank] = 0x0FFFFFFF;
+  }
+}
+
+/**
+  * @brief  Initializes the XMC NAND Banks according to the specified
+  *         parameters in the XMC_NANDInitStruct.
+  * @param  XMC_NANDInitStruct : pointer to a XMC_NANDInitType
+  *         structure that contains the configuration information for the XMC
+  *         NAND specified Banks.
+  * @retval None
+  */
+void XMC_NANDInit(XMC_NANDInitType* XMC_NANDInitStruct)
+{
+  uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
+
+  /* Check the parameters */
+  assert_param( IS_XMC_NAND_BANK(XMC_NANDInitStruct->XMC_Bank));
+  assert_param( IS_XMC_WAIT_OPERATION(XMC_NANDInitStruct->XMC_EnableWait));
+  assert_param( IS_XMC_BUS_TYPE(XMC_NANDInitStruct->XMC_BusType));
+  assert_param( IS_XMC_ECC_OPERATION(XMC_NANDInitStruct->XMC_EnableECC));
+  assert_param( IS_XMC_ECCPAGE_SIZE(XMC_NANDInitStruct->XMC_ECCPageSize));
+  assert_param( IS_XMC_DELAY_CR_TIME(XMC_NANDInitStruct->XMC_DelayTimeCR));
+  assert_param( IS_XMC_DELAY_AR_TIME(XMC_NANDInitStruct->XMC_DelayTimeAR));
+  assert_param(IS_XMC_SETUP_TIME(XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_SetupTime));
+  assert_param(IS_XMC_OP_TIME(XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_OpTime));
+  assert_param(IS_XMC_HOLD_TIME(XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_HoldTime));
+  assert_param(IS_XMC_WRITE_SETUP_TIME(XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_WriteSetupTime));
+  assert_param(IS_XMC_SETUP_TIME(XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_SetupTime));
+  assert_param(IS_XMC_OP_TIME(XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_OpTime));
+  assert_param(IS_XMC_HOLD_TIME(XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_HoldTime));
+  assert_param(IS_XMC_WRITE_SETUP_TIME(XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_WriteSetupTime));
+
+  /* Set the tmppcr value according to XMC_NANDInitStruct parameters */
+  tmppcr = (uint32_t)XMC_NANDInitStruct->XMC_EnableWait |
+           BKxCTRL_Device_NAND |
+           XMC_NANDInitStruct->XMC_BusType |
+           XMC_NANDInitStruct->XMC_EnableECC |
+           XMC_NANDInitStruct->XMC_ECCPageSize |
+           (XMC_NANDInitStruct->XMC_DelayTimeCR << 9 ) |
+           (XMC_NANDInitStruct->XMC_DelayTimeAR << 13);
+
+  /* Set tmppmem value according to XMC_CommonSpaceTimingStructure parameters */
+  tmppmem = (uint32_t)XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_SetupTime |
+            (XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_OpTime << 8) |
+            (XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_HoldTime << 16) |
+            (XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_WriteSetupTime << 24);
+
+  /* Set tmppatt value according to XMC_AttributeSpaceTimingStructure parameters */
+  tmppatt = (uint32_t)XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_SetupTime |
+            (XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_OpTime << 8) |
+            (XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_HoldTime << 16) |
+            (XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_WriteSetupTime << 24);
+
+  if(XMC_NANDInitStruct->XMC_Bank == XMC_Bank2_NAND)
+  {
+    /* XMC_Bank2_NAND registers configuration */
+    XMC_Bank2->BK2CTRL = tmppcr;
+    XMC_Bank2->BK2TMGMEM = tmppmem;
+    XMC_Bank2->BK2TMGATT = tmppatt;
+  }
+  else
+  {
+    /* XMC_Bank3_NAND registers configuration */
+    XMC_Bank3->BK3CTRL = tmppcr;
+    XMC_Bank3->BK3TMGMEM = tmppmem;
+    XMC_Bank3->BK3TMGATT = tmppatt;
+  }
+}
+
+/**
+  * @brief  Initializes the XMC PCCARD Bank according to the specified
+  *         parameters in the XMC_PCCARDInitStruct.
+  * @param  XMC_PCCARDInitStruct : pointer to a XMC_PCCARDInitType
+  *         structure that contains the configuration information for the XMC
+  *         PCCARD Bank.
+  * @retval None
+  */
+void XMC_PCCARDInit(XMC_PCCARDInitType* XMC_PCCARDInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_XMC_WAIT_OPERATION(XMC_PCCARDInitStruct->XMC_EnableWait));
+  assert_param(IS_XMC_DELAY_CR_TIME(XMC_PCCARDInitStruct->XMC_DelayTimeCR));
+  assert_param(IS_XMC_DELAY_AR_TIME(XMC_PCCARDInitStruct->XMC_DelayTimeAR));
+
+  assert_param(IS_XMC_SETUP_TIME(XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_SetupTime));
+  assert_param(IS_XMC_OP_TIME(XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_OpTime));
+  assert_param(IS_XMC_HOLD_TIME(XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_HoldTime));
+  assert_param(IS_XMC_WRITE_SETUP_TIME(XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_WriteSetupTime));
+
+  assert_param(IS_XMC_SETUP_TIME(XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_SetupTime));
+  assert_param(IS_XMC_OP_TIME(XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_OpTime));
+  assert_param(IS_XMC_HOLD_TIME(XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_HoldTime));
+  assert_param(IS_XMC_WRITE_SETUP_TIME(XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_WriteSetupTime));
+  assert_param(IS_XMC_SETUP_TIME(XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_SetupTime));
+  assert_param(IS_XMC_OP_TIME(XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_OpTime));
+  assert_param(IS_XMC_HOLD_TIME(XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_HoldTime));
+  assert_param(IS_XMC_WRITE_SETUP_TIME(XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_WriteSetupTime));
+
+  /* Set the PCR4 register value according to XMC_PCCARDInitStruct parameters */
+  XMC_Bank4->BK4CTRL = (uint32_t)XMC_PCCARDInitStruct->XMC_EnableWait |
+                       XMC_BusType_16b |
+                       (XMC_PCCARDInitStruct->XMC_DelayTimeCR << 9) |
+                       (XMC_PCCARDInitStruct->XMC_DelayTimeAR << 13);
+
+  /* Set PMEM4 register value according to XMC_CommonSpaceTimingStructure parameters */
+  XMC_Bank4->BK4TMGMEM = (uint32_t)XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_SetupTime |
+                         (XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_OpTime << 8) |
+                         (XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_HoldTime << 16) |
+                         (XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_WriteSetupTime << 24);
+
+  /* Set PATT4 register value according to XMC_AttributeSpaceTimingStructure parameters */
+  XMC_Bank4->BK4TMGATT = (uint32_t)XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_SetupTime |
+                         (XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_OpTime << 8) |
+                         (XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_HoldTime << 16) |
+                         (XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_WriteSetupTime << 24);
+
+  /* Set PIO4 register value according to XMC_IOSpaceTimingStructure parameters */
+  XMC_Bank4->BK4TMGIO = (uint32_t)XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_SetupTime |
+                        (XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_OpTime << 8) |
+                        (XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_HoldTime << 16) |
+                        (XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_WriteSetupTime << 24);
+}
+
+/**
+  * @brief  Fills each XMC_NORSRAMInitStruct member with its default value.
+  * @param  XMC_NORSRAMInitStruct: pointer to a XMC_NORSRAMInitType
+  *         structure which will be initialized.
+  * @retval None
+  */
+void XMC_NORSRAMStructInit(XMC_NORSRAMInitType* XMC_NORSRAMInitStruct)
+{
+  /* Reset NOR/SRAM Init structure parameters values */
+  XMC_NORSRAMInitStruct->XMC_Bank = XMC_Bank1_NORSRAM1;
+  XMC_NORSRAMInitStruct->XMC_DataAdrMux = XMC_DataAdrMux_Enable;
+  XMC_NORSRAMInitStruct->XMC_Dev = XMC_Dev_SRAM;
+  XMC_NORSRAMInitStruct->XMC_BusType = XMC_BusType_8b;
+  XMC_NORSRAMInitStruct->XMC_EnableBurstMode = XMC_BurstMode_Disable;
+  XMC_NORSRAMInitStruct->XMC_EnableAsynWait = XMC_AsynWait_Disable;
+  XMC_NORSRAMInitStruct->XMC_WaitSignalLv = XMC_WaitSignalLv_Low;
+  XMC_NORSRAMInitStruct->XMC_EnableBurstModeSplit = XMC_BurstModeSplit_Disable;
+  XMC_NORSRAMInitStruct->XMC_WaitSignalConfig = XMC_WaitSignalConfig_BeforeWaitState;
+  XMC_NORSRAMInitStruct->XMC_EnableWrite = XMC_WriteOperation_Enable;
+  XMC_NORSRAMInitStruct->XMC_EnableWaitSignal = XMC_WaitSignal_Enable;
+  XMC_NORSRAMInitStruct->XMC_EnableWriteTiming = XMC_WriteTiming_Disable;
+  XMC_NORSRAMInitStruct->XMC_WriteBurstSyn = XMC_WriteBurstSyn_Disable;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_AdrOpTime = 0xF;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_AdrHoldTime = 0xF;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_DataOpTime = 0xFF;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_IntervalBetweenOP = 0xF;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_CLKPsc = 0xF;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_DataStableTime = 0xF;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_Mode = XMC_Mode_A;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_AdrOpTime = 0xF;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_AdrHoldTime = 0xF;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_DataOpTime = 0xFF;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_IntervalBetweenOP = 0xF;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_CLKPsc = 0xF;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_DataStableTime = 0xF;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_Mode = XMC_Mode_A;
+}
+
+/**
+  * @brief  Fills each XMC_NANDInitStruct member with its default value.
+  * @param  XMC_NANDInitStruct: pointer to a XMC_NANDInitType
+  *         structure which will be initialized.
+  * @retval None
+  */
+void XMC_NANDStructInit(XMC_NANDInitType* XMC_NANDInitStruct)
+{
+  /* Reset NAND Init structure parameters values */
+  XMC_NANDInitStruct->XMC_Bank = XMC_Bank2_NAND;
+  XMC_NANDInitStruct->XMC_EnableWait = XMC_WaitOperation_Disable;
+  XMC_NANDInitStruct->XMC_BusType = XMC_BusType_8b;
+  XMC_NANDInitStruct->XMC_EnableECC = XMC_ECCOperation_Disable;
+  XMC_NANDInitStruct->XMC_ECCPageSize = XMC_ECCPageSize_256Bytes;
+  XMC_NANDInitStruct->XMC_DelayTimeCR = 0x0;
+  XMC_NANDInitStruct->XMC_DelayTimeAR = 0x0;
+  XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_SetupTime = 0xFC;
+  XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_OpTime = 0xFC;
+  XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_HoldTime = 0xFC;
+  XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_WriteSetupTime = 0xFC;
+  XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_SetupTime = 0xFC;
+  XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_OpTime = 0xFC;
+  XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_HoldTime = 0xFC;
+  XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_WriteSetupTime = 0xFC;
+}
+
+/**
+  * @brief  Fills each XMC_PCCARDInitStruct member with its default value.
+  * @param  XMC_PCCARDInitStruct: pointer to a XMC_PCCARDInitType
+  *         structure which will be initialized.
+  * @retval None
+  */
+void XMC_PCCARDStructInit(XMC_PCCARDInitType* XMC_PCCARDInitStruct)
+{
+  /* Reset PCCARD Init structure parameters values */
+  XMC_PCCARDInitStruct->XMC_EnableWait = XMC_WaitOperation_Disable;
+  XMC_PCCARDInitStruct->XMC_DelayTimeCR = 0x0;
+  XMC_PCCARDInitStruct->XMC_DelayTimeAR = 0x0;
+  XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_SetupTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_OpTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_HoldTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_WriteSetupTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_SetupTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_OpTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_HoldTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_WriteSetupTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_SetupTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_OpTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_HoldTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_WriteSetupTime = 0xFC;
+}
+
+/**
+  * @brief  Config the bus turnaround phase
+  * @param  XMC_SubBank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_SubBank1_NORSRAM1: XMC SubBank1 NOR/SRAM1
+  *     @arg XMC_SubBank1_NORSRAM2: XMC SubBank1 NOR/SRAM2
+  *     @arg XMC_SubBank1_NORSRAM3: XMC SubBank1 NOR/SRAM3
+  *     @arg XMC_SubBank1_NORSRAM4: XMC SubBank1 NOR/SRAM4
+  * @param  W2W_Timing: Bus turnaround phase for consecutive write duration.from 0 to 255 HCLK, default:8 HCLK
+  * @param  R2R_Timing: Bus turnaround phase for consecutive read duration.from 0 to 255 HCLK, default:8 HCLK
+  * @retval None
+  */
+void XMC_ExtTimingConfig(uint32_t XMC_SubBank, uint8_t W2W_Timing, uint8_t R2R_Timing)
+{
+  assert_param(IS_XMC_Sub_NORSRAM_REGION(XMC_SubBank)); 
+  
+  XMC_Bank1H->BK1EXT[XMC_SubBank] &= 0;
+  XMC_Bank1H->BK1EXT[XMC_SubBank] |= (W2W_Timing|(R2R_Timing<<8));  
+}
+
+/**
+  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank1_NORSRAM1: XMC Bank1 NOR/SRAM1
+  *     @arg XMC_Bank1_NORSRAM2: XMC Bank1 NOR/SRAM2
+  *     @arg XMC_Bank1_NORSRAM3: XMC Bank1 NOR/SRAM3
+  *     @arg XMC_Bank1_NORSRAM4: XMC Bank1 NOR/SRAM4
+  * @param  NewState: new state of the XMC_Bank. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void XMC_NORSRAMCmd(uint32_t XMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_XMC_NORSRAM_REGION(XMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
+    XMC_Bank1->BK1CTRLR[XMC_Bank] |= BK1CTRLx_EN_Set;
+  }
+  else
+  {
+    /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
+    XMC_Bank1->BK1CTRLR[XMC_Bank] &= BK1CTRLx_EN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified NAND Memory Bank.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  * @param  NewState: new state of the XMC_Bank. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void XMC_NANDCmd(uint32_t XMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_XMC_NAND_BANK(XMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
+    if(XMC_Bank == XMC_Bank2_NAND)
+    {
+      XMC_Bank2->BK2CTRL |= BKxCTRL_EN_Set;
+    }
+    else
+    {
+      XMC_Bank3->BK3CTRL |= BKxCTRL_EN_Set;
+    }
+  }
+  else
+  {
+    /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
+    if(XMC_Bank == XMC_Bank2_NAND)
+    {
+      XMC_Bank2->BK2CTRL &= BKxCTRL_EN_Reset;
+    }
+    else
+    {
+      XMC_Bank3->BK3CTRL &= BKxCTRL_EN_Reset;
+    }
+  }
+}
+/**
+  * @brief  Deinitializes the XMC NOR/SRAM Banks registers to their default
+  *         reset values.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank1_NORSRAM1: XMC Bank1 NOR/SRAM1
+  *     @arg XMC_Bank1_NORSRAM2: XMC Bank1 NOR/SRAM2
+  *     @arg XMC_Bank1_NORSRAM3: XMC Bank1 NOR/SRAM3
+  *     @arg XMC_Bank1_NORSRAM4: XMC Bank1 NOR/SRAM4
+  * @retval None
+  */
+void XMC_NORSRAMReset(uint32_t XMC_Bank)
+{
+  /* Check the parameter */
+  assert_param(IS_XMC_NORSRAM_REGION(XMC_Bank));
+
+  /* XMC_Bank1_NORSRAM1 */
+  if(XMC_Bank == XMC_Bank1_NORSRAM1)
+  {
+    XMC_Bank1->BK1CTRLR[XMC_Bank] = 0x000030DB;
+  }
+  /* XMC_Bank1_NORSRAM2,  XMC_Bank1_NORSRAM3 or XMC_Bank1_NORSRAM4 */
+  else
+  {
+    XMC_Bank1->BK1CTRLR[XMC_Bank] = 0x000030D2;
+  }
+
+  XMC_Bank1->BK1CTRLR[XMC_Bank + 1] = 0x0FFFFFFF;
+  XMC_Bank1E->BK1TMGWR[XMC_Bank] = 0x0FFFFFFF;
+}
+
+/**
+  * @brief  Deinitializes the XMC NAND Banks registers to their default reset values.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  * @retval None
+  */
+void XMC_NANDReset(uint32_t XMC_Bank)
+{
+  /* Check the parameter */
+  assert_param(IS_XMC_NAND_BANK(XMC_Bank));
+
+  if(XMC_Bank == XMC_Bank2_NAND)
+  {
+    /* Set the XMC_Bank2 registers to their reset values */
+    XMC_Bank2->BK2CTRL = 0x00000018;
+    XMC_Bank2->BK2STS = 0x00000040;
+    XMC_Bank2->BK2TMGMEM = 0xFCFCFCFC;
+    XMC_Bank2->BK2TMGATT = 0xFCFCFCFC;
+  }
+  /* XMC_Bank3_NAND */
+  else
+  {
+    /* Set the XMC_Bank3 registers to their reset values */
+    XMC_Bank3->BK3CTRL = 0x00000018;
+    XMC_Bank3->BK3STS = 0x00000040;
+    XMC_Bank3->BK3TMGMEM = 0xFCFCFCFC;
+    XMC_Bank3->BK3TMGATT = 0xFCFCFCFC;
+  }
+}
+
+/**
+  * @brief  Deinitializes the XMC PCCARD Bank registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void XMC_PCCARDReset(void)
+{
+  /* Set the XMC_Bank4 registers to their reset values */
+  XMC_Bank4->BK4CTRL = 0x00000018;
+  XMC_Bank4->BK4STS = 0x00000000;
+  XMC_Bank4->BK4TMGMEM = 0xFCFCFCFC;
+  XMC_Bank4->BK4TMGATT = 0xFCFCFCFC;
+  XMC_Bank4->BK4TMGIO = 0xFCFCFCFC;
+}
+
+
+/**
+  * @}
+  */
+
+#endif /* AT32F403xx || AT32F403Axx || AT32F407xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

StdPeriph_Driver/src/misc.c

@@ -0,0 +1,214 @@
+/**
+  **************************************************************************
+  * File   : misc.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : at32f4xx MISC source file
+  **************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "misc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup MISC
+  * @brief MISC driver modules
+  * @{
+  */
+
+/** @defgroup MISC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Defines
+  * @{
+  */
+
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+  *                                4 bits for subpriority
+  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+  *                                3 bits for subpriority
+  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+  *                                2 bits for subpriority
+  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+  *                                1 bits for subpriority
+  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+  *                                0 bits for subpriority
+  * @retval None
+  */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitType structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * @retval None
+  */
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct)
+{
+  uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08;
+    tmppre = (0x4 - tmppriority);
+    tmpsub = tmpsub >> tmppriority;
+
+    tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+    tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+    tmppriority = tmppriority << 0x04;
+
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+}
+
+/**
+  * @brief  Sets the vector table location and Offset.
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_VectTab_RAM
+  *     @arg NVIC_VectTab_FLASH
+  * @param  Offset: Vector Table base offset field. This value must be a multiple
+  *         of 0x200.
+  * @retval None
+  */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+  assert_param(IS_NVIC_OFFSET(Offset));
+
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+  * @brief  Selects the condition for the system to enter low power mode.
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_LP_SEVONPEND
+  *     @arg NVIC_LP_SLEEPDEEP
+  *     @arg NVIC_LP_SLEEPONEXIT
+  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_LP(LowPowerMode));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    SCB->SCR |= LowPowerMode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+  }
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.
+  *   This parameter can be one of the following values:
+  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+  {
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

User/at32f4xx_it.c

@@ -0,0 +1,143 @@
+/**
+  ******************************************************************************
+  * File   : Templates/at32f4xx_it.c
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  */ 
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_it.h"
+/** @addtogroup AT32F403A_StdPeriph_Templates
+  * @{
+  */
+
+/** @addtogroup GPIO_LED_Toggle
+  * @{
+  */
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*                 at32f4xx Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_at32f403_xx.s).                                            */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

User/inc/at32f4xx_it.h

@@ -0,0 +1,36 @@
+/**
+  ******************************************************************************
+  * File   : Templates/at32f4xx_it.h 
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  */ 
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_IT_H
+#define __AT32F4XX_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+#endif /* __AT32F4XX_IT_H */
+

User/main.c

@@ -0,0 +1,177 @@
+/**
+  ******************************************************************************
+  * File   : Templates/main.c 
+  * Version: V1.3.0
+  * Date   : 2021-03-18
+  * Brief  : Main program body
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdio.h>
+#include "at32f4xx.h"
+#include "at32_board.h"
+/** @addtogroup AT32F403A_StdPeriph_Templates
+  * @{
+  */
+
+/** @addtogroup Template
+  * @{
+  */
+
+/* Private define ------------------------------------------------------------*/
+#define DELAY          100
+#define FAST           1
+#define SLOW           4
+
+/* Extern variables ---------------------------------------------------------*/
+extern GPIO_Type *BUTTON_GPIO_PORT[BUTTON_NUM];
+extern uint16_t BUTTON_GPIO_PIN[BUTTON_NUM];
+extern uint32_t BUTTON_GPIO_RCC_CLK[BUTTON_NUM];
+
+/* Private variables ---------------------------------------------------------*/
+uint16_t BUTTON_EXTI_LINE[BUTTON_NUM] = {EXTI_Line0, EXTI_Line13};
+uint16_t BUTTON_EXTI_IRQ[BUTTON_NUM] = {EXTI0_IRQn, EXTI15_10_IRQn};
+uint8_t BUTTON_EXTI_SOURCE_PORT[BUTTON_NUM] = {GPIO_PortSourceGPIOA, GPIO_PortSourceGPIOC};
+uint8_t BUTTON_EXTI_SOURCE_PIN[BUTTON_NUM] = {GPIO_PinsSource0, GPIO_PinsSource13};
+
+BUTTON_Type gButtonType = BUTTON_WAKEUP;
+uint8_t gSpeed = FAST;
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Config Clock Out Function.
+  * @param  None
+  * @retval None
+  */
+void MCO_Config(void) {
+    GPIO_InitType GPIO_InitStructure;
+    RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_GPIOA, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pins = GPIO_Pins_8;
+    GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+    /*PA8Êä³öPLL/4*/
+    RCC_CLKOUTConfig(RCC_CLKOUT_PLL_Div4, RCC_MCOPRE_1);
+}
+
+/**
+  * @brief  Configure Button EXTI   
+  * @param  Button: Specifies the Button to be configured.
+  * @retval None
+  */
+void BUTTON_EXTI_Init(BUTTON_Type button) {
+    EXTI_InitType EXTI_InitStructure;
+    NVIC_InitType NVIC_InitStructure;
+
+    GPIO_EXTILineConfig(BUTTON_EXTI_SOURCE_PORT[button], BUTTON_EXTI_SOURCE_PIN[button]);
+    EXTI_StructInit(&EXTI_InitStructure);
+    EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[button];
+    EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+    EXTI_InitStructure.EXTI_LineEnable = ENABLE;
+    EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+    EXTI_Init(&EXTI_InitStructure);
+
+    NVIC_InitStructure.NVIC_IRQChannel = BUTTON_EXTI_IRQ[button];
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
+    NVIC_Init(&NVIC_InitStructure);
+}
+
+/**
+  * @brief  Button EXTI0 Interrupt Handler
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void) {
+    Delay_ms(5);
+    EXTI_ClearIntPendingBit(BUTTON_EXTI_LINE[gButtonType]);
+    if ((GPIO_ReadInputData(BUTTON_GPIO_PORT[gButtonType]) & BUTTON_GPIO_PIN[gButtonType]) == \
+      BUTTON_GPIO_PIN[gButtonType]) {
+        if (gSpeed == SLOW)
+            gSpeed = FAST;
+        else
+            gSpeed = SLOW;
+    }
+}
+
+/**
+  * @brief  Button EXTI13 Interrupt Handler
+  * @param  None
+  * @retval None
+  */
+void EXTI15_10_IRQHandler(void) {
+    Delay_ms(5);
+    EXTI_ClearIntPendingBit(BUTTON_EXTI_LINE[gButtonType]);
+    if ((GPIO_ReadInputData(BUTTON_GPIO_PORT[gButtonType]) & BUTTON_GPIO_PIN[gButtonType]) == \
+      BUTTON_GPIO_PIN[gButtonType]) {
+        if (gSpeed == SLOW)
+            gSpeed = FAST;
+        else
+            gSpeed = SLOW;
+    }
+}
+
+/**
+  * @brief  Main Function.
+  * @param  None
+  * @retval None
+  */
+int main(void) {
+    gButtonType = BUTTON_WAKEUP;
+
+    RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_AFIO, ENABLE);
+
+    AT32_Board_Init();
+
+    MCO_Config();
+
+    BUTTON_EXTI_Init(gButtonType);
+    UART_Print_Init(115200);
+    for (;;) {
+        printf("Hello,true Linker,clion,test float! %f\r\n", 2.1f);
+        AT32_LEDn_Toggle(LED2);
+        Delay_ms(gSpeed * DELAY);
+        AT32_LEDn_Toggle(LED3);
+        Delay_ms(gSpeed * DELAY);
+        AT32_LEDn_Toggle(LED4);
+        Delay_ms(gSpeed * DELAY);
+    }
+}
+
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {}
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+