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https://github.com/xiaotianbc/AT32_BSPV1_Clion_Template.git
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739 lines
26 KiB
C
739 lines
26 KiB
C
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/**
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**************************************************************************
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* File : at32f4xx_xmc.h
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* Version: V1.3.0
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* Date : 2021-03-18
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* Brief : at32f4xx XMC header file
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**************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F4XX_XMC_H
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#define __AT32F4XX_XMC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "at32f4xx.h"
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/** @addtogroup at32f4xx_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup XMC
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* @{
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*/
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/** @defgroup XMC_Exported_Types
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* @{
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*/
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/**
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* @brief Timing parameters For NOR/SRAM Banks
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*/
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typedef struct
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{
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uint32_t XMC_AdrOpTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the address setup time.
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This parameter can be a value between 0 and 0xF.
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@note: It is not used with synchronous NOR Flash memories. */
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uint32_t XMC_AdrHoldTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the address hold time.
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This parameter can be a value between 0 and 0xF.
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@note: It is not used with synchronous NOR Flash memories.*/
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uint32_t XMC_DataOpTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the data setup time.
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This parameter can be a value between 0 and 0xFF.
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@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
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uint32_t XMC_IntervalBetweenOP; /*!< Defines the number of HCLK cycles to configure
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the duration of the bus turnaround.
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This parameter can be a value between 0 and 0xF.
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@note: It is only used for multiplexed NOR Flash memories. */
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uint32_t XMC_CLKPsc; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
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This parameter can be a value between 1 and 0xF.
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@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
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uint32_t XMC_DataStableTime; /*!< Defines the number of memory clock cycles to issue
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to the memory before getting the first data.
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The value of this parameter depends on the memory type as shown below:
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- It must be set to 0 in case of a CRAM
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- It is don't care in asynchronous NOR, SRAM or ROM accesses
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- It may assume a value between 0 and 0xF in NOR Flash memories
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with synchronous burst mode enable */
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uint32_t XMC_Mode; /*!< Specifies the asynchronous access mode.
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This parameter can be a value of @ref XMC_Access_Mode */
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} XMC_NORSRAMTimingInitType;
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/**
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* @brief XMC NOR/SRAM Init structure definition
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*/
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typedef struct
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{
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uint32_t XMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
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This parameter can be a value of @ref XMC_NORSRAM_Bank */
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uint32_t XMC_DataAdrMux; /*!< Specifies whether the address and data values are
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multiplexed on the databus or not.
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This parameter can be a value of @ref XMC_Data_Address_Bus_Multiplexing */
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uint32_t XMC_Dev; /*!< Specifies the type of external memory attached to
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the corresponding memory bank.
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This parameter can be a value of @ref XMC_Memory_Type */
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uint32_t XMC_BusType; /*!< Specifies the external memory device width.
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This parameter can be a value of @ref XMC_Data_Width */
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uint32_t XMC_EnableBurstMode; /*!< Enables or disables the burst access mode for Flash memory,
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valid only with synchronous burst Flash memories.
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This parameter can be a value of @ref XMC_Burst_Access_Mode */
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uint32_t XMC_EnableAsynWait; /*!< Enables or disables wait signal during asynchronous transfers,
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valid only with asynchronous Flash memories.
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This parameter can be a value of @ref XMC_EnableAsynWait */
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uint32_t XMC_WaitSignalLv; /*!< Specifies the wait signal polarity, valid only when accessing
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the Flash memory in burst mode.
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This parameter can be a value of @ref XMC_Wait_Signal_Polarity */
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uint32_t XMC_EnableBurstModeSplit; /*!< Enables or disables the Wrapped burst access mode for Flash
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memory, valid only when accessing Flash memories in burst mode.
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This parameter can be a value of @ref XMC_Wrap_Mode */
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uint32_t XMC_WaitSignalConfig; /*!< Specifies if the wait signal is asserted by the memory one
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clock cycle before the wait state or during the wait state,
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valid only when accessing memories in burst mode.
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This parameter can be a value of @ref XMC_Wait_Timing */
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uint32_t XMC_EnableWrite; /*!< Enables or disables the write operation in the selected bank by the XMC.
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This parameter can be a value of @ref XMC_Write_Operation */
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uint32_t XMC_EnableWaitSignal; /*!< Enables or disables the wait-state insertion via wait
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signal, valid for Flash memory access in burst mode.
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This parameter can be a value of @ref XMC_Wait_Signal */
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uint32_t XMC_EnableWriteTiming; /*!< Enables or disables the extended mode.
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This parameter can be a value of @ref XMC_Extended_Mode */
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uint32_t XMC_WriteBurstSyn; /*!< Enables or disables the write burst operation.
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This parameter can be a value of @ref XMC_Write_Burst */
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XMC_NORSRAMTimingInitType* XMC_RWTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
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XMC_NORSRAMTimingInitType* XMC_WTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
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} XMC_NORSRAMInitType;
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/**
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* @brief Timing parameters For XMC NAND and PCCARD Banks
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*/
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typedef struct
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{
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uint32_t XMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
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the command assertion for NAND-Flash read or write access
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to common/Attribute or I/O memory space (depending on
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the memory space timing to be configured).
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This parameter can be a value between 0 and 0xFF.*/
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uint32_t XMC_OpTime; /*!< Defines the minimum number of HCLK cycles to assert the
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command for NAND-Flash read or write access to
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common/Attribute or I/O memory space (depending on the
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memory space timing to be configured).
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This parameter can be a number between 0x00 and 0xFF */
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uint32_t XMC_HoldTime; /*!< Defines the number of HCLK clock cycles to hold address
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(and data for write access) after the command deassertion
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for NAND-Flash read or write access to common/Attribute
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or I/O memory space (depending on the memory space timing
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to be configured).
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This parameter can be a number between 0x00 and 0xFF */
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uint32_t XMC_WriteSetupTime; /*!< Defines the number of HCLK clock cycles during which the
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databus is kept in HiZ after the start of a NAND-Flash
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write access to common/Attribute or I/O memory space (depending
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on the memory space timing to be configured).
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This parameter can be a number between 0x00 and 0xFF */
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} XMC_NAND_PCCARDTimingInitType;
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/**
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* @brief XMC NAND Init structure definition
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*/
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typedef struct
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{
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uint32_t XMC_Bank; /*!< Specifies the NAND memory bank that will be used.
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This parameter can be a value of @ref XMC_NAND_Bank */
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uint32_t XMC_EnableWait; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
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This parameter can be any value of @ref XMC_Wait_feature */
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uint32_t XMC_BusType; /*!< Specifies the external memory device width.
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This parameter can be any value of @ref XMC_Data_Width */
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uint32_t XMC_EnableECC; /*!< Enables or disables the ECC computation.
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This parameter can be any value of @ref XMC_EnableECC */
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uint32_t XMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
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This parameter can be any value of @ref XMC_ECC_Page_Size */
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uint32_t XMC_DelayTimeCR; /*!< Defines the number of HCLK cycles to configure the
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delay between CLE low and RE low.
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This parameter can be a value between 0 and 0xFF. */
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uint32_t XMC_DelayTimeAR; /*!< Defines the number of HCLK cycles to configure the
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delay between ALE low and RE low.
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This parameter can be a number between 0x0 and 0xFF */
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XMC_NAND_PCCARDTimingInitType* XMC_CommonSpaceTimingStruct; /*!< XMC Common Space Timing */
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XMC_NAND_PCCARDTimingInitType* XMC_AttributeSpaceTimingStruct; /*!< XMC Attribute Space Timing */
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} XMC_NANDInitType;
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/**
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* @brief XMC PCCARD Init structure definition
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*/
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typedef struct
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{
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uint32_t XMC_EnableWait; /*!< Enables or disables the Wait feature for the Memory Bank.
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This parameter can be any value of @ref XMC_Wait_feature */
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uint32_t XMC_DelayTimeCR; /*!< Defines the number of HCLK cycles to configure the
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delay between CLE low and RE low.
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This parameter can be a value between 0 and 0xFF. */
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uint32_t XMC_DelayTimeAR; /*!< Defines the number of HCLK cycles to configure the
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delay between ALE low and RE low.
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This parameter can be a number between 0x0 and 0xFF */
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XMC_NAND_PCCARDTimingInitType* XMC_CommonSpaceTimingStruct; /*!< XMC Common Space Timing */
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XMC_NAND_PCCARDTimingInitType* XMC_AttributeSpaceTimingStruct; /*!< XMC Attribute Space Timing */
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XMC_NAND_PCCARDTimingInitType* XMC_IOSpaceTimingStruct; /*!< XMC IO Space Timing */
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} XMC_PCCARDInitType;
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/**
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* @}
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*/
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/** @defgroup XMC_Exported_Constants
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* @{
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*/
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/** @defgroup XMC_NORSRAM_Bank
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* @{
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*/
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#define XMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
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#define XMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
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#define XMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
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#define XMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
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/**
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* @}
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*/
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/** @defgroup XMC_SubBank
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* @{
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*/
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#define XMC_SubBank1_NORSRAM1 ((uint32_t)0x00000000)
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#define XMC_SubBank1_NORSRAM2 ((uint32_t)0x00000001)
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#define XMC_SubBank1_NORSRAM3 ((uint32_t)0x00000002)
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#define XMC_SubBank1_NORSRAM4 ((uint32_t)0x00000003)
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/**
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* @}
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*/
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/** @defgroup XMC_NAND_Bank
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* @{
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*/
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#define XMC_Bank2_NAND ((uint32_t)0x00000010)
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#define XMC_Bank3_NAND ((uint32_t)0x00000100)
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/**
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* @}
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*/
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/** @defgroup XMC_PCCARD_Bank
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* @{
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*/
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#define XMC_Bank4_PCCARD ((uint32_t)0x00001000)
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/**
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* @}
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*/
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#define IS_XMC_Sub_NORSRAM_REGION(REGION) (((REGION) == XMC_SubBank1_NORSRAM1) || \
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((REGION) == XMC_SubBank1_NORSRAM2) || \
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((REGION) == XMC_SubBank1_NORSRAM3) || \
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((REGION) == XMC_SubBank1_NORSRAM4))
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#define IS_XMC_NORSRAM_REGION(REGION) (((REGION) == XMC_Bank1_NORSRAM1) || \
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((REGION) == XMC_Bank1_NORSRAM2) || \
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((REGION) == XMC_Bank1_NORSRAM3) || \
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((REGION) == XMC_Bank1_NORSRAM4))
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#define IS_XMC_NAND_BANK(BANK) (((BANK) == XMC_Bank2_NAND) || \
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((BANK) == XMC_Bank3_NAND))
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#define IS_XMC_GETFLAG_BANK(BANK) (((BANK) == XMC_Bank2_NAND) || \
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((BANK) == XMC_Bank3_NAND) || \
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((BANK) == XMC_Bank4_PCCARD))
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#define IS_XMC_INT_BANK(BANK) (((BANK) == XMC_Bank2_NAND) || \
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((BANK) == XMC_Bank3_NAND) || \
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((BANK) == XMC_Bank4_PCCARD))
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/** @defgroup NOR_SRAM_Controller
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* @{
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*/
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/** @defgroup XMC_Data_Address_Bus_Multiplexing
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* @{
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*/
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#define XMC_DataAdrMux_Disable ((uint32_t)0x00000000)
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#define XMC_DataAdrMux_Enable ((uint32_t)0x00000002)
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#define IS_XMC_MUX(MUX) (((MUX) == XMC_DataAdrMux_Disable) || \
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((MUX) == XMC_DataAdrMux_Enable))
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/**
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* @}
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*/
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/** @defgroup XMC_Memory_Type
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* @{
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*/
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#define XMC_Dev_SRAM ((uint32_t)0x00000000)
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#define XMC_Dev_PSRAM ((uint32_t)0x00000004)
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#define XMC_Dev_NOR ((uint32_t)0x00000008)
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#define IS_XMC_DEVICE(DEVICE) (((DEVICE) == XMC_Dev_SRAM) || \
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((DEVICE) == XMC_Dev_PSRAM)|| \
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((DEVICE) == XMC_Dev_NOR))
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/**
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* @}
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*/
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/** @defgroup XMC_Data_Width
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* @{
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*/
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#define XMC_BusType_8b ((uint32_t)0x00000000)
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#define XMC_BusType_16b ((uint32_t)0x00000010)
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#define IS_XMC_BUS_TYPE(TYPE) (((TYPE) == XMC_BusType_8b) || \
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((TYPE) == XMC_BusType_16b))
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/**
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* @}
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*/
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/** @defgroup XMC_Burst_Access_Mode
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* @{
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*/
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#define XMC_BurstMode_Disable ((uint32_t)0x00000000)
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#define XMC_BurstMode_Enable ((uint32_t)0x00000100)
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|
#define IS_XMC_BURSTMODE(STATE) (((STATE) == XMC_BurstMode_Disable) || \
|
||
|
|
((STATE) == XMC_BurstMode_Enable))
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_AsynchronousWait
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define XMC_AsynWait_Disable ((uint32_t)0x00000000)
|
||
|
|
#define XMC_AsynWait_Enable ((uint32_t)0x00008000)
|
||
|
|
#define IS_XMC_ASYNWAIT(STATE) (((STATE) == XMC_AsynWait_Disable) || \
|
||
|
|
((STATE) == XMC_AsynWait_Enable))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Wait_Signal_Polarity
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define XMC_WaitSignalLv_Low ((uint32_t)0x00000000)
|
||
|
|
#define XMC_WaitSignalLv_High ((uint32_t)0x00000200)
|
||
|
|
#define IS_XMC_WAIT_SIGNAL_LEVEL(LEVEL) (((LEVEL) == XMC_WaitSignalLv_Low) || \
|
||
|
|
((LEVEL) == XMC_WaitSignalLv_High))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Wrap_Mode
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define XMC_BurstModeSplit_Disable ((uint32_t)0x00000000)
|
||
|
|
#define XMC_BurstModeSplit_Enable ((uint32_t)0x00000400)
|
||
|
|
#define IS_XMC_BURSTMODE_SPLIT(MODE) (((MODE) == XMC_BurstModeSplit_Disable) || \
|
||
|
|
((MODE) == XMC_BurstModeSplit_Enable))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Wait_Timing
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define XMC_WaitSignalConfig_BeforeWaitState ((uint32_t)0x00000000)
|
||
|
|
#define XMC_WaitSignalConfig_DuringWaitState ((uint32_t)0x00000800)
|
||
|
|
#define IS_XMC_WAIT_SIGNAL_CONFIG(CONFIG) (((CONFIG) == XMC_WaitSignalConfig_BeforeWaitState) || \
|
||
|
|
((CONFIG) == XMC_WaitSignalConfig_DuringWaitState))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Write_Operation
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define XMC_WriteOperation_Disable ((uint32_t)0x00000000)
|
||
|
|
#define XMC_WriteOperation_Enable ((uint32_t)0x00001000)
|
||
|
|
#define IS_XMC_WRITE_OPERATION(OPERATION) (((OPERATION) == XMC_WriteOperation_Disable) || \
|
||
|
|
((OPERATION) == XMC_WriteOperation_Enable))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Wait_Signal
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define XMC_WaitSignal_Disable ((uint32_t)0x00000000)
|
||
|
|
#define XMC_WaitSignal_Enable ((uint32_t)0x00002000)
|
||
|
|
#define IS_XMC_WAIT_SIGNAL(SIGNAL) (((SIGNAL) == XMC_WaitSignal_Disable) || \
|
||
|
|
((SIGNAL) == XMC_WaitSignal_Enable))
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Extended_Mode
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define XMC_WriteTiming_Disable ((uint32_t)0x00000000)
|
||
|
|
#define XMC_WriteTiming_Enable ((uint32_t)0x00004000)
|
||
|
|
|
||
|
|
#define IS_XMC_WRITE_TIMING(STATE) (((STATE) == XMC_WriteTiming_Disable) || \
|
||
|
|
((STATE) == XMC_WriteTiming_Enable))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Write_Burst
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define XMC_WriteBurstSyn_Disable ((uint32_t)0x00000000)
|
||
|
|
#define XMC_WriteBurstSyn_Enable ((uint32_t)0x00080000)
|
||
|
|
#define IS_XMC_WRITE_BURST_SYN(SYN) (((SYN) == XMC_WriteBurstSyn_Disable) || \
|
||
|
|
((SYN) == XMC_WriteBurstSyn_Enable))
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Address_Setup_Time
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IS_XMC_ADDRESS_OP_TIME(TIME) ((TIME) <= 0xF)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Address_Hold_Time
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IS_XMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Data_Setup_Time
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IS_XMC_DATA_OP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Bus_Turn_around_Duration
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IS_XMC_INTERVAL_BETWEEN_OP_TIME(TIME) ((TIME) <= 0xF)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_CLK_Division
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IS_XMC_CLK_DIV(DIV) ((DIV) <= 0xF)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Data_Latency
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IS_XMC_DATA_STABLE_TIME(TIME) ((TIME) <= 0xF)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Access_Mode
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define XMC_Mode_A ((uint32_t)0x00000000)
|
||
|
|
#define XMC_Mode_B ((uint32_t)0x10000000)
|
||
|
|
#define XMC_Mode_C ((uint32_t)0x20000000)
|
||
|
|
#define XMC_Mode_D ((uint32_t)0x30000000)
|
||
|
|
#define IS_XMC_MODE(MODE) (((MODE) == XMC_Mode_A) || \
|
||
|
|
((MODE) == XMC_Mode_B) || \
|
||
|
|
((MODE) == XMC_Mode_C) || \
|
||
|
|
((MODE) == XMC_Mode_D))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup NAND_PCCARD_Controller
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Wait_feature
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define XMC_WaitOperation_Disable ((uint32_t)0x00000000)
|
||
|
|
#define XMC_WaitOperation_Enable ((uint32_t)0x00000002)
|
||
|
|
#define IS_XMC_WAIT_OPERATION(OPERATION) (((OPERATION) == XMC_WaitOperation_Disable) || \
|
||
|
|
((OPERATION) == XMC_WaitOperation_Enable))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
/** @defgroup XMC_EnableECC
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define XMC_ECCOperation_Disable ((uint32_t)0x00000000)
|
||
|
|
#define XMC_ECCOperation_Enable ((uint32_t)0x00000040)
|
||
|
|
#define IS_XMC_ECC_OPERATION(OPERATION) (((OPERATION) == XMC_ECCOperation_Disable) || \
|
||
|
|
((OPERATION) == XMC_ECCOperation_Enable))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_ECC_Page_Size
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define XMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
|
||
|
|
#define XMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
|
||
|
|
#define XMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
|
||
|
|
#define XMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
|
||
|
|
#define XMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
|
||
|
|
#define XMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
|
||
|
|
#define IS_XMC_ECCPAGE_SIZE(SIZE) (((SIZE) == XMC_ECCPageSize_256Bytes) || \
|
||
|
|
((SIZE) == XMC_ECCPageSize_512Bytes) || \
|
||
|
|
((SIZE) == XMC_ECCPageSize_1024Bytes) || \
|
||
|
|
((SIZE) == XMC_ECCPageSize_2048Bytes) || \
|
||
|
|
((SIZE) == XMC_ECCPageSize_4096Bytes) || \
|
||
|
|
((SIZE) == XMC_ECCPageSize_8192Bytes))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_TCLR_Setup_Time
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IS_XMC_DELAY_CR_TIME(TIME) ((TIME) <= 0xFF)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_TAR_Setup_Time
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IS_XMC_DELAY_AR_TIME(TIME) ((TIME) <= 0xFF)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Setup_Time
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IS_XMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Wait_Setup_Time
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IS_XMC_OP_TIME(TIME) ((TIME) <= 0xFF)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Hold_Setup_Time
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IS_XMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_HiZ_Setup_Time
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IS_XMC_WRITE_SETUP_TIME(TIME) ((TIME) <= 0xFF)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Interrupt_sources
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define XMC_INT_RisingEdge ((uint32_t)0x00000008)
|
||
|
|
#define XMC_INT_Level ((uint32_t)0x00000010)
|
||
|
|
#define XMC_INT_FallingEdge ((uint32_t)0x00000020)
|
||
|
|
#define IS_XMC_INT(INT) ((((INT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((INT) != 0x00000000))
|
||
|
|
#define IS_XMC_GET_INT(INT) (((INT) == XMC_INT_RisingEdge) || \
|
||
|
|
((INT) == XMC_INT_Level) || \
|
||
|
|
((INT) == XMC_INT_FallingEdge))
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Flags
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define XMC_FLAG_RisingEdge ((uint32_t)0x00000001)
|
||
|
|
#define XMC_FLAG_Level ((uint32_t)0x00000002)
|
||
|
|
#define XMC_FLAG_FallingEdge ((uint32_t)0x00000004)
|
||
|
|
#define XMC_FLAG_FEMPT ((uint32_t)0x00000040)
|
||
|
|
#define IS_XMC_GET_FLAG(FLAG) (((FLAG) == XMC_FLAG_RisingEdge) || \
|
||
|
|
((FLAG) == XMC_FLAG_Level) || \
|
||
|
|
((FLAG) == XMC_FLAG_FallingEdge) || \
|
||
|
|
((FLAG) == XMC_FLAG_FEMPT))
|
||
|
|
|
||
|
|
#define IS_XMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Exported_Macros
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup XMC_Exported_Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
void XMC_NANDCmd(uint32_t XMC_Bank, FunctionalState NewState);
|
||
|
|
void XMC_PCCARDCmd(FunctionalState NewState);
|
||
|
|
void XMC_NANDECCCmd(uint32_t XMC_Bank, FunctionalState NewState);
|
||
|
|
uint32_t XMC_GetECC(uint32_t XMC_Bank);
|
||
|
|
void XMC_INTConfig(uint32_t XMC_Bank, uint32_t XMC_INT, FunctionalState NewState);
|
||
|
|
FlagStatus XMC_GetFlagStatus(uint32_t XMC_Bank, uint32_t XMC_FLAG);
|
||
|
|
void XMC_NORSRAMStructInit(XMC_NORSRAMInitType* XMC_NORSRAMInitStruct);
|
||
|
|
void XMC_NANDStructInit(XMC_NANDInitType* XMC_NANDInitStruct);
|
||
|
|
void XMC_PCCARDStructInit(XMC_PCCARDInitType* XMC_PCCARDInitStruct);
|
||
|
|
void XMC_NORSRAMCmd(uint32_t XMC_Bank, FunctionalState NewState);
|
||
|
|
void XMC_ClearFlag(uint32_t XMC_Bank, uint32_t XMC_FLAG);
|
||
|
|
ITStatus XMC_GetINTStatus(uint32_t XMC_Bank, uint32_t XMC_INT);
|
||
|
|
void XMC_ClearINTPendingBit(uint32_t XMC_Bank, uint32_t XMC_INT);
|
||
|
|
void XMC_ExtTimingConfig(uint32_t XMC_SubBank, uint8_t W2W_Timing, uint8_t R2R_Timing);
|
||
|
|
void XMC_NORSRAMReset(uint32_t XMC_Bank);
|
||
|
|
void XMC_NANDReset(uint32_t XMC_Bank);
|
||
|
|
void XMC_PCCARDReset(void);
|
||
|
|
void XMC_NORSRAMInit(XMC_NORSRAMInitType* XMC_NORSRAMInitStruct);
|
||
|
|
void XMC_NANDInit(XMC_NANDInitType* XMC_NANDInitStruct);
|
||
|
|
void XMC_PCCARDInit(XMC_PCCARDInitType* XMC_PCCARDInitStruct);
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /*__AT32F4XX_XMC_H */
|
||
|
|
/**
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* @}
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*/
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||
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/**
|
||
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* @}
|
||
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*/
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||
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||
|
|
/**
|
||
|
|
* @}
|
||
|
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*/
|
||
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||
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