yemai/AT32F413_Firmware_Library
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update version to v2.1.0

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Artery-MCU
2023-08-08 19:29:14 +08:00
parent 704a2ff779
commit fb61391d00
363 changed files with 144902 additions and 1210 deletions
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4
project/at_start_f413/examples/tmr/6_steps/readme.txt
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@@ -7,7 +7,7 @@
this demo is based on the at-start board, in this demo, shows how to configure
the tmr1 peripheral to generate 6 steps. a software com event is generated
each 100 ms: using the systick interrupt. the break polarity is used at high level.
each 100 ms: using the systick interrupt. the brake polarity is used at high level.
the following table describes the tmr1 channels states:
-----------------------------------------------
| step1 | step2 | step3 | step4 | step5 | step6 |
@@ -33,4 +33,4 @@
- tmr1_ch1 ---> pa8
- tmr1_ch2c ---> pb14
for more detailed information. please refer to the application note document AN0085.
for more detailed information. please refer to the application note document AN0085.

6
project/at_start_f413/examples/tmr/6_steps/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

2
project/at_start_f413/examples/tmr/6_steps/src/main.c
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@@ -146,7 +146,7 @@ int main(void)
tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_3, &tmr_output_struct);
tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_3, 511);
/* automatic output enable, break, dead time and lock configuration */
/* automatic output enable, brake, dead time and lock configuration */
tmr_brkdt_default_para_init(&tmr_brkdt_config_struct);
tmr_brkdt_config_struct.brk_enable = TRUE;
tmr_brkdt_config_struct.auto_output_enable = TRUE;

2
project/at_start_f413/examples/tmr/7_pwm_output/readme.txt
View File

@@ -29,4 +29,4 @@
- tmr1_ch3c ---> pb15
- tmr1_ch4 ---> pa11
for more detailed information. please refer to the application note document AN0085.
for more detailed information. please refer to the application note document AN0085.

6
project/at_start_f413/examples/tmr/7_pwm_output/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/cascade_synchro/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

8
project/at_start_f413/examples/tmr/complementary_signals/readme.txt
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@@ -7,7 +7,7 @@
this demo is based on the at-start board, in this demo, shows how to configure
the tmr1 peripheral to generate three complementary tmr1 signals, to insert
a defined dead time value, to use the break feature and to lock the desired
a defined dead time value, to use the brake feature and to lock the desired
parameters.
tmr1 configuration to:
@@ -28,7 +28,7 @@
- channelxpulse = duty_cycle * (tim1_period - 1) / 100
step2: insert a dead time equal to 11/system_core_clock ns
step3: configure the break feature, active at high level, and using the automatic
step3: configure the brake feature, active at high level, and using the automatic
output enable feature
step4: use the locking parameters level1.
@@ -43,7 +43,7 @@
- tmr1_ch3 pin (pa.10)
- tmr1_ch3c pin (pb.15)
- connect the tmr1 break pin tmr1_brkin pin (pb.12) to the gnd. to generate a
break event, switch this pin level from 0v to 3.3v.
- connect the tmr1 brake pin tmr1_brkin pin (pb.12) to the gnd. to generate a
brake event, switch this pin level from 0v to 3.3v.
for more detailed information. please refer to the application note document AN0085.

6
project/at_start_f413/examples/tmr/complementary_signals/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

2
project/at_start_f413/examples/tmr/complementary_signals/src/main.c
View File

@@ -105,7 +105,7 @@ int main(void)
- channelxpulse = duty_cycle * (tmr1_period - 1) / 100
2/ insert a dead time equal to 11/system_core_clock ns
3/ configure the break feature, active at high level, and using the automatic
3/ configure the brake feature, active at high level, and using the automatic
output enable feature
4/ use the locking parameters level1. */

2
project/at_start_f413/examples/tmr/dma/readme.txt
View File

@@ -15,4 +15,4 @@
- tmr1 ch3 ---> pa10
- tmr1 ch3c ---> pb15
for more detailed information. please refer to the application note document AN0085.
for more detailed information. please refer to the application note document AN0085.

6
project/at_start_f413/examples/tmr/dma/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/dma_burst/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

2
project/at_start_f413/examples/tmr/encoder_tmr2/readme.txt
View File

@@ -11,4 +11,4 @@
- pa0 <---> pa2
- pa1 <---> pa3
for more detailed information. please refer to the application note document AN0085.
for more detailed information. please refer to the application note document AN0085.

6
project/at_start_f413/examples/tmr/encoder_tmr2/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/external_clock/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/hall_xor_tmr2/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/hang_mode/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/input_capture/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/oc_high/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/oc_low/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/oc_toggle_tmr3/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/oc_toggle_tmr9/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/one_cycle/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/parallel_synchro/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/pwm_input/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/pwm_input_dma/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/pwm_output_simulate/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

2
project/at_start_f413/examples/tmr/pwm_output_tmr10/readme.txt
View File

@@ -7,4 +7,4 @@
this demo is based on the at-start board, in this demo, pb8 output pwm waveform.
for more detailed information. please refer to the application note document AN0085.
for more detailed information. please refer to the application note document AN0085.

6
project/at_start_f413/examples/tmr/pwm_output_tmr10/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

2
project/at_start_f413/examples/tmr/pwm_output_tmr3/readme.txt
View File

@@ -12,4 +12,4 @@
tmr3 channel3 duty cycle = (tmr3_c3dt/ tmr3_pr)* 100 = 25%
tmr3 channel4 duty cycle = (tmr3_c4dt/ tmr3_pr)* 100 = 12.5%
for more detailed information. please refer to the application note document AN0085.
for more detailed information. please refer to the application note document AN0085.

6
project/at_start_f413/examples/tmr/pwm_output_tmr3/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/timer_base/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

6
project/at_start_f413/examples/tmr/tmr1_synchro/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000

2
project/at_start_f413/examples/tmr/tmr2_32bit/readme.txt
View File

@@ -14,4 +14,4 @@
ch3 duty_cycle = 12.5%
ch4 duty_cycle = 6.25%
for more detailed information. please refer to the application note document AN0085.
for more detailed information. please refer to the application note document AN0085.

6
project/at_start_f413/examples/tmr/tmr2_32bit/src/at32f413_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 192000000
* - ahbdiv = 1
* - ahbclk = 192000000