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update version to v2.0.4

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Artery-MCU
2022-04-11 19:27:58 +08:00
parent d2285506f0
commit eab9bf65de
1451 changed files with 221506 additions and 13129 deletions
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66
libraries/drivers/inc/at32f413_acc.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_acc.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 acc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -32,8 +32,8 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f413.h"
@@ -48,7 +48,7 @@ extern "C" {
/** @defgroup ACC_exported_constants
* @{
*/
#define ACC_CAL_HICKCAL ((uint16_t)0x0000) /*!< acc hick calibration */
#define ACC_CAL_HICKTRIM ((uint16_t)0x0002) /*!< acc hick trim */
@@ -70,10 +70,10 @@ extern "C" {
* @brief type define acc register all
*/
typedef struct
{
{
/**
* @brief acc sts register, offset:0x00
* @brief acc sts register, offset:0x00
*/
union
{
@@ -81,13 +81,13 @@ typedef struct
struct
{
__IO uint32_t calrdy : 1; /* [0] */
__IO uint32_t rslost : 1; /* [1] */
__IO uint32_t rslost : 1; /* [1] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} sts_bit;
};
/**
* @brief acc ctrl1 register, offset:0x04
* @brief acc ctrl1 register, offset:0x04
*/
union
{
@@ -95,18 +95,18 @@ typedef struct
struct
{
__IO uint32_t calon : 1; /* [0] */
__IO uint32_t entrim : 1; /* [1] */
__IO uint32_t reserved1 : 2; /* [3:2] */
__IO uint32_t entrim : 1; /* [1] */
__IO uint32_t reserved1 : 2; /* [3:2] */
__IO uint32_t eien : 1; /* [4] */
__IO uint32_t calrdyien : 1; /* [5] */
__IO uint32_t reserved2 : 2; /* [7:6] */
__IO uint32_t step : 4; /* [11:8] */
__IO uint32_t calrdyien : 1; /* [5] */
__IO uint32_t reserved2 : 2; /* [7:6] */
__IO uint32_t step : 4; /* [11:8] */
__IO uint32_t reserved3 : 20;/* [31:12] */
} ctrl1_bit;
};
/**
* @brief acc ctrl2 register, offset:0x08
* @brief acc ctrl2 register, offset:0x08
*/
union
{
@@ -114,13 +114,13 @@ typedef struct
struct
{
__IO uint32_t hickcal : 8; /* [7:0] */
__IO uint32_t hicktrim : 6; /* [13:8] */
__IO uint32_t hicktrim : 6; /* [13:8] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} ctrl2_bit;
};
/**
* @brief acc acc_c1 register, offset:0x0C
* @brief acc acc_c1 register, offset:0x0C
*/
union
{
@@ -131,9 +131,9 @@ typedef struct
__IO uint32_t reserved1 : 16;/* [31:16] */
} c1_bit;
};
/**
* @brief acc acc_c2 register, offset:0x10
* @brief acc acc_c2 register, offset:0x10
*/
union
{
@@ -144,9 +144,9 @@ typedef struct
__IO uint32_t reserved1 : 16;/* [31:16] */
} c2_bit;
};
/**
* @brief acc acc_c3 register, offset:0x14
* @brief acc acc_c3 register, offset:0x14
*/
union
{
@@ -156,8 +156,8 @@ typedef struct
__IO uint32_t c3 : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} c3_bit;
};
} acc_type;
};
} acc_type;
/**
* @}
@@ -167,7 +167,7 @@ typedef struct
/** @defgroup ACC_exported_functions
* @{
*/
*/
void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state);
void acc_step_set(uint8_t step_value);

270
libraries/drivers/inc/at32f413_adc.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_adc.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 adc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,8 +31,8 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f413.h"
@@ -45,10 +45,10 @@ extern "C" {
*/
/** @defgroup ADC_interrupts_definition
* @brief adc interrupt
* @brief adc interrupt
* @{
*/
#define ADC_CCE_INT ((uint32_t)0x00000020) /*!< channels conversion end interrupt */
#define ADC_VMOR_INT ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
#define ADC_PCCE_INT ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
@@ -58,10 +58,10 @@ extern "C" {
*/
/** @defgroup ADC_flags_definition
* @brief adc flag
* @brief adc flag
* @{
*/
#define ADC_VMOR_FLAG ((uint8_t)0x01) /*!< voltage monitoring out of range flag */
#define ADC_CCE_FLAG ((uint8_t)0x02) /*!< channels conversion end flag */
#define ADC_PCCE_FLAG ((uint8_t)0x04) /*!< preempt channels conversion end flag */
@@ -77,7 +77,7 @@ extern "C" {
*/
/**
* @brief adc combine mode type(these options are reserved in adc2)
* @brief adc combine mode type(these options are reserved in adc2)
*/
typedef enum
{
@@ -94,7 +94,7 @@ typedef enum
} adc_combine_mode_type;
/**
* @brief adc data align type
* @brief adc data align type
*/
typedef enum
{
@@ -103,7 +103,7 @@ typedef enum
} adc_data_align_type;
/**
* @brief adc channel select type
* @brief adc channel select type
*/
typedef enum
{
@@ -128,7 +128,7 @@ typedef enum
} adc_channel_select_type;
/**
* @brief adc sampletime select type
* @brief adc sampletime select type
*/
typedef enum
{
@@ -143,7 +143,7 @@ typedef enum
} adc_sampletime_select_type;
/**
* @brief adc ordinary group trigger event select type
* @brief adc ordinary group trigger event select type
*/
typedef enum
{
@@ -162,7 +162,7 @@ typedef enum
} adc_ordinary_trig_select_type;
/**
* @brief adc preempt group trigger event select type
* @brief adc preempt group trigger event select type
*/
typedef enum
{
@@ -178,10 +178,10 @@ typedef enum
ADC12_PREEMPT_TRIG_TMR1CH1 = 0x0D, /*!< timer1 ch1 event as trigger source of adc1/adc2 preempt sequence */
ADC12_PREEMPT_TRIG_TMR8CH1 = 0x0E, /*!< timer8 ch1 event as trigger source of adc1/adc2 preempt sequence */
ADC12_PREEMPT_TRIG_TMR8TRGOUT = 0x0F, /*!< timer8 trgout event as trigger source of adc1/adc2 preempt sequence */
} adc_preempt_trig_select_type;
} adc_preempt_trig_select_type;
/**
* @brief adc preempt channel type
* @brief adc preempt channel type
*/
typedef enum
{
@@ -192,7 +192,7 @@ typedef enum
} adc_preempt_channel_type;
/**
* @brief adc voltage_monitoring type
* @brief adc voltage_monitoring type
*/
typedef enum
{
@@ -203,10 +203,10 @@ typedef enum
ADC_VMONITOR_ALL_PREEMPT = 0x00400000, /*!< voltage_monitoring on all preempt channel */
ADC_VMONITOR_ALL_ORDINARY_PREEMPT = 0x00C00000, /*!< voltage_monitoring on all ordinary and preempt channel */
ADC_VMONITOR_NONE = 0x00000000 /*!< no channel guarded by the voltage_monitoring */
} adc_voltage_monitoring_type;
} adc_voltage_monitoring_type;
/**
* @brief adc base config type
/**
* @brief adc base config type
*/
typedef struct
{
@@ -220,10 +220,10 @@ typedef struct
* @brief type define adc register all
*/
typedef struct
{
{
/**
* @brief adc sts register, offset:0x00
* @brief adc sts register, offset:0x00
*/
union
{
@@ -234,13 +234,13 @@ typedef struct
__IO uint32_t cce : 1; /* [1] */
__IO uint32_t pcce : 1; /* [2] */
__IO uint32_t pccs : 1; /* [3] */
__IO uint32_t occs : 1; /* [4] */
__IO uint32_t occs : 1; /* [4] */
__IO uint32_t reserved1 : 27;/* [31:5] */
} sts_bit;
};
/**
* @brief adc ctrl1 register, offset:0x04
* @brief adc ctrl1 register, offset:0x04
*/
union
{
@@ -248,7 +248,7 @@ typedef struct
struct
{
__IO uint32_t vmcsel : 5; /* [4:0] */
__IO uint32_t cceien : 1; /* [5] */
__IO uint32_t cceien : 1; /* [5] */
__IO uint32_t vmorien : 1; /* [6] */
__IO uint32_t pcceien : 1; /* [7] */
__IO uint32_t sqen : 1; /* [8] */
@@ -258,15 +258,15 @@ typedef struct
__IO uint32_t pcpen : 1; /* [12] */
__IO uint32_t ocpcnt : 3; /* [15:13] */
__IO uint32_t mssel : 4; /* [19:16] */
__IO uint32_t reserved1 : 2; /* [21:20] */
__IO uint32_t reserved1 : 2; /* [21:20] */
__IO uint32_t pcvmen : 1; /* [22] */
__IO uint32_t ocvmen : 1; /* [23] */
__IO uint32_t ocvmen : 1; /* [23] */
__IO uint32_t reserved2 : 8; /* [31:24] */
} ctrl1_bit;
};
/**
* @brief adc ctrl2 register, offset:0x08
* @brief adc ctrl2 register, offset:0x08
*/
union
{
@@ -274,29 +274,29 @@ typedef struct
struct
{
__IO uint32_t adcen : 1; /* [0] */
__IO uint32_t rpen : 1; /* [1] */
__IO uint32_t rpen : 1; /* [1] */
__IO uint32_t adcal : 1; /* [2] */
__IO uint32_t adcalinit : 1; /* [3] */
__IO uint32_t adcalinit : 1; /* [3] */
__IO uint32_t reserved1 : 4; /* [7:4] */
__IO uint32_t ocdmaen : 1; /* [8] */
__IO uint32_t ocdmaen : 1; /* [8] */
__IO uint32_t reserved2 : 2; /* [10:9] */
__IO uint32_t dtalign : 1; /* [11] */
__IO uint32_t dtalign : 1; /* [11] */
__IO uint32_t pctesel_l : 3; /* [14:12] */
__IO uint32_t pcten : 1; /* [15] */
__IO uint32_t pcten : 1; /* [15] */
__IO uint32_t reserved3 : 1; /* [16] */
__IO uint32_t octesel_l : 3; /* [19:17] */
__IO uint32_t octesel_l : 3; /* [19:17] */
__IO uint32_t octen : 1; /* [20] */
__IO uint32_t pcswtrg : 1; /* [21] */
__IO uint32_t pcswtrg : 1; /* [21] */
__IO uint32_t ocswtrg : 1; /* [22] */
__IO uint32_t itsrven : 1; /* [23] */
__IO uint32_t itsrven : 1; /* [23] */
__IO uint32_t pctesel_h : 1; /* [24] */
__IO uint32_t octesel_h : 1; /* [25] */
__IO uint32_t octesel_h : 1; /* [25] */
__IO uint32_t reserved4 : 6; /* [31:26] */
} ctrl2_bit;
};
/**
* @brief adc spt1 register, offset:0x0C
* @brief adc spt1 register, offset:0x0C
*/
union
{
@@ -305,18 +305,18 @@ typedef struct
{
__IO uint32_t cspt10 : 3; /* [2:0] */
__IO uint32_t cspt11 : 3; /* [5:3] */
__IO uint32_t cspt12 : 3; /* [8:6] */
__IO uint32_t cspt12 : 3; /* [8:6] */
__IO uint32_t cspt13 : 3; /* [11:9] */
__IO uint32_t cspt14 : 3; /* [14:12] */
__IO uint32_t cspt15 : 3; /* [17:15] */
__IO uint32_t cspt16 : 3; /* [20:18] */
__IO uint32_t cspt17 : 3; /* [23:21] */
__IO uint32_t cspt15 : 3; /* [17:15] */
__IO uint32_t cspt16 : 3; /* [20:18] */
__IO uint32_t cspt17 : 3; /* [23:21] */
__IO uint32_t reserved1 : 8;/* [31:24] */
} spt1_bit;
};
/**
* @brief adc spt2 register, offset:0x10
* @brief adc spt2 register, offset:0x10
*/
union
{
@@ -325,237 +325,237 @@ typedef struct
{
__IO uint32_t cspt0 : 3;/* [2:0] */
__IO uint32_t cspt1 : 3;/* [5:3] */
__IO uint32_t cspt2 : 3;/* [8:6] */
__IO uint32_t cspt2 : 3;/* [8:6] */
__IO uint32_t cspt3 : 3;/* [11:9] */
__IO uint32_t cspt4 : 3;/* [14:12] */
__IO uint32_t cspt5 : 3;/* [17:15] */
__IO uint32_t cspt6 : 3;/* [20:18] */
__IO uint32_t cspt7 : 3;/* [23:21] */
__IO uint32_t cspt8 : 3;/* [26:24] */
__IO uint32_t cspt9 : 3;/* [29:27] */
__IO uint32_t cspt5 : 3;/* [17:15] */
__IO uint32_t cspt6 : 3;/* [20:18] */
__IO uint32_t cspt7 : 3;/* [23:21] */
__IO uint32_t cspt8 : 3;/* [26:24] */
__IO uint32_t cspt9 : 3;/* [29:27] */
__IO uint32_t reserved1 : 2;/* [31:30] */
} spt2_bit;
};
/**
* @brief adc pcdto1 register, offset:0x14
* @brief adc pcdto1 register, offset:0x14
*/
union
{
__IO uint32_t pcdto1;
struct
{
__IO uint32_t pcdto1 : 12; /* [11:0] */
__IO uint32_t pcdto1 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto1_bit;
};
};
/**
* @brief adc pcdto2 register, offset:0x18
* @brief adc pcdto2 register, offset:0x18
*/
union
{
__IO uint32_t pcdto2;
struct
{
__IO uint32_t pcdto2 : 12; /* [11:0] */
__IO uint32_t pcdto2 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto2_bit;
};
};
/**
* @brief adc pcdto3 register, offset:0x1C
* @brief adc pcdto3 register, offset:0x1C
*/
union
{
__IO uint32_t pcdto3;
struct
{
__IO uint32_t pcdto3 : 12; /* [11:0] */
__IO uint32_t pcdto3 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto3_bit;
};
};
/**
* @brief adc pcdto4 register, offset:0x20
* @brief adc pcdto4 register, offset:0x20
*/
union
{
__IO uint32_t pcdto4;
struct
{
__IO uint32_t pcdto4 : 12; /* [11:0] */
__IO uint32_t pcdto4 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto4_bit;
};
};
/**
* @brief adc vmhb register, offset:0x24
* @brief adc vmhb register, offset:0x24
*/
union
{
__IO uint32_t vmhb;
struct
{
__IO uint32_t vmhb : 12; /* [11:0] */
__IO uint32_t vmhb : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} vmhb_bit;
};
};
/**
* @brief adc vmlb register, offset:0x28
* @brief adc vmlb register, offset:0x28
*/
union
{
__IO uint32_t vmlb;
struct
{
__IO uint32_t vmlb : 12; /* [11:0] */
__IO uint32_t vmlb : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} vmlb_bit;
};
};
/**
* @brief adc osq1 register, offset:0x2C
* @brief adc osq1 register, offset:0x2C
*/
union
{
__IO uint32_t osq1;
struct
{
__IO uint32_t osn13 : 5; /* [4:0] */
__IO uint32_t osn14 : 5; /* [9:5] */
__IO uint32_t osn15 : 5; /* [14:10] */
__IO uint32_t osn13 : 5; /* [4:0] */
__IO uint32_t osn14 : 5; /* [9:5] */
__IO uint32_t osn15 : 5; /* [14:10] */
__IO uint32_t osn16 : 5; /* [19:15] */
__IO uint32_t oclen : 4; /* [23:20] */
__IO uint32_t oclen : 4; /* [23:20] */
__IO uint32_t reserved1 : 8; /* [31:24] */
} osq1_bit;
};
};
/**
* @brief adc osq2 register, offset:0x30
* @brief adc osq2 register, offset:0x30
*/
union
{
__IO uint32_t osq2;
struct
{
__IO uint32_t osn7 : 5; /* [4:0] */
__IO uint32_t osn8 : 5; /* [9:5] */
__IO uint32_t osn9 : 5; /* [14:10] */
__IO uint32_t osn7 : 5; /* [4:0] */
__IO uint32_t osn8 : 5; /* [9:5] */
__IO uint32_t osn9 : 5; /* [14:10] */
__IO uint32_t osn10 : 5; /* [19:15] */
__IO uint32_t osn11 : 5; /* [24:20] */
__IO uint32_t osn12 : 5; /* [29:25] */
__IO uint32_t osn11 : 5; /* [24:20] */
__IO uint32_t osn12 : 5; /* [29:25] */
__IO uint32_t reserved1 : 2; /* [31:30] */
} osq2_bit;
};
};
/**
* @brief adc osq3 register, offset:0x34
* @brief adc osq3 register, offset:0x34
*/
union
{
__IO uint32_t osq3;
struct
{
__IO uint32_t osn1 : 5; /* [4:0] */
__IO uint32_t osn2 : 5; /* [9:5] */
__IO uint32_t osn3 : 5; /* [14:10] */
__IO uint32_t osn1 : 5; /* [4:0] */
__IO uint32_t osn2 : 5; /* [9:5] */
__IO uint32_t osn3 : 5; /* [14:10] */
__IO uint32_t osn4 : 5; /* [19:15] */
__IO uint32_t osn5 : 5; /* [24:20] */
__IO uint32_t osn6 : 5; /* [29:25] */
__IO uint32_t osn5 : 5; /* [24:20] */
__IO uint32_t osn6 : 5; /* [29:25] */
__IO uint32_t reserved1 : 2; /* [31:30] */
} osq3_bit;
};
};
/**
* @brief adc psq register, offset:0x38
* @brief adc psq register, offset:0x38
*/
union
{
__IO uint32_t psq;
struct
{
__IO uint32_t psn1 : 5; /* [4:0] */
__IO uint32_t psn2 : 5; /* [9:5] */
__IO uint32_t psn3 : 5; /* [14:10] */
__IO uint32_t psn1 : 5; /* [4:0] */
__IO uint32_t psn2 : 5; /* [9:5] */
__IO uint32_t psn3 : 5; /* [14:10] */
__IO uint32_t psn4 : 5; /* [19:15] */
__IO uint32_t pclen : 2; /* [21:20] */
__IO uint32_t pclen : 2; /* [21:20] */
__IO uint32_t reserved1 : 10;/* [31:22] */
} psq_bit;
};
};
/**
* @brief adc pdt1 register, offset:0x3C
* @brief adc pdt1 register, offset:0x3C
*/
union
{
__IO uint32_t pdt1;
struct
{
__IO uint32_t pdt1 : 16; /* [15:0] */
__IO uint32_t pdt1 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt1_bit;
};
};
/**
* @brief adc pdt2 register, offset:0x40
* @brief adc pdt2 register, offset:0x40
*/
union
{
__IO uint32_t pdt2;
struct
{
__IO uint32_t pdt2 : 16; /* [15:0] */
__IO uint32_t pdt2 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt2_bit;
};
};
/**
* @brief adc pdt3 register, offset:0x44
* @brief adc pdt3 register, offset:0x44
*/
union
{
__IO uint32_t pdt3;
struct
{
__IO uint32_t pdt3 : 16; /* [15:0] */
__IO uint32_t pdt3 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt3_bit;
};
};
/**
* @brief adc pdt4 register, offset:0x48
* @brief adc pdt4 register, offset:0x48
*/
union
{
__IO uint32_t pdt4;
struct
{
__IO uint32_t pdt4 : 16; /* [15:0] */
__IO uint32_t pdt4 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt4_bit;
};
};
/**
* @brief adc odt register, offset:0x4C
* @brief adc odt register, offset:0x4C
*/
union
{
__IO uint32_t odt;
struct
{
__IO uint32_t odt : 16; /* [15:0] */
__IO uint32_t odt : 16; /* [15:0] */
__IO uint32_t adc2odt : 16; /* [31:16] */
} odt_bit;
};
};
} adc_type;
} adc_type;
/**
* @}
*/
#define ADC1 ((adc_type *) ADC1_BASE)
#define ADC2 ((adc_type *) ADC2_BASE)

12
libraries/drivers/inc/at32f413_bpr.h
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f413_bpr.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 bpr header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -43,19 +43,19 @@ extern "C" {
/** @addtogroup BPR
* @{
*/
/** @defgroup BPR_flags_definition
* @brief bpr flag
* @brief bpr flag
* @{
*/
#define BPR_TAMPER_INTERRUPT_FLAG ((uint32_t)0x00000001) /*!< bpr tamper interrupt flag */
#define BPR_TAMPER_EVENT_FLAG ((uint32_t)0x00000002) /*!< bpr tamper event flag */
/**
* @}
*/
/** @defgroup BPR_exported_types
* @{
*/

534
libraries/drivers/inc/at32f413_can.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_can.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 can header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -42,12 +42,12 @@ extern "C" {
/** @addtogroup CAN
* @{
*/
*/
/** @defgroup CAN_timeout_count
* @{
*/
*/
#define FZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for fzc bit */
#define DZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for dzc bit */
@@ -57,10 +57,10 @@ extern "C" {
*/
/** @defgroup CAN_flags_definition
* @brief can flag
* @brief can flag
* @{
*/
#define CAN_EAF_FLAG ((uint32_t)0x01) /*!< error active flag */
#define CAN_EPF_FLAG ((uint32_t)0x02) /*!< error passive flag */
#define CAN_BOF_FLAG ((uint32_t)0x03) /*!< bus-off flag */
@@ -84,7 +84,7 @@ extern "C" {
*/
/** @defgroup CAN_interrupts_definition
* @brief can interrupt
* @brief can interrupt
* @{
*/
@@ -281,7 +281,7 @@ typedef enum
typedef enum
{
CAN_ENTER_DOZE_FAILED = 0x00, /*!< can enter the doze mode failed */
CAN_ENTER_DOZE_SUCCESSFUL = 0x01 /*!< can enter the doze mode successful */
CAN_ENTER_DOZE_SUCCESSFUL = 0x01 /*!< can enter the doze mode successful */
} can_enter_doze_status_type;
/**
@@ -290,7 +290,7 @@ typedef enum
typedef enum
{
CAN_QUIT_DOZE_FAILED = 0x00, /*!< can quit doze mode failed */
CAN_QUIT_DOZE_SUCCESSFUL = 0x01 /*!< can quit doze mode successful */
CAN_QUIT_DOZE_SUCCESSFUL = 0x01 /*!< can quit doze mode successful */
} can_quit_doze_status_type;
/**
@@ -299,7 +299,7 @@ typedef enum
typedef enum
{
CAN_DISCARDING_FIRST_RECEIVED = 0x00, /*!< can discarding the first received message */
CAN_DISCARDING_LAST_RECEIVED = 0x01 /*!< can discarding the last received message */
CAN_DISCARDING_LAST_RECEIVED = 0x01 /*!< can discarding the last received message */
} can_msg_discarding_rule_type;
/**
@@ -308,7 +308,7 @@ typedef enum
typedef enum
{
CAN_SENDING_BY_ID = 0x00, /*!< can sending the minimum id message first*/
CAN_SENDING_BY_REQUEST = 0x01 /*!< can sending the first request message first */
CAN_SENDING_BY_REQUEST = 0x01 /*!< can sending the first request message first */
} can_msg_sending_rule_type;
/**
@@ -323,7 +323,7 @@ typedef enum
CAN_ERRORRECORD_BITRECESSIVEERR = 0x04, /*!< bit recessive error */
CAN_ERRORRECORD_BITDOMINANTERR = 0x05, /*!< bit dominant error */
CAN_ERRORRECORD_CRCERR = 0x06, /*!< crc error */
CAN_ERRORRECORD_SOFTWARESETERR = 0x07 /*!< software set error */
CAN_ERRORRECORD_SOFTWARESETERR = 0x07 /*!< software set error */
} can_error_record_type;
/**
@@ -331,20 +331,20 @@ typedef enum
*/
typedef struct
{
can_mode_type mode_selection; /*!< specifies the can mode.*/
confirm_state ttc_enable; /*!< time triggered communication mode enable */
can_mode_type mode_selection; /*!< specifies the can mode.*/
confirm_state ttc_enable; /*!< time triggered communication mode enable */
confirm_state aebo_enable; /*!< automatic exit bus-off enable */
confirm_state aed_enable; /*!< automatic exit doze mode enable */
confirm_state prsf_enable; /*!< prohibit retransmission when sending fails enable */
can_msg_discarding_rule_type mdrsel_selection; /*!< message discarding rule select when overflow */
confirm_state prsf_enable; /*!< prohibit retransmission when sending fails enable */
can_msg_discarding_rule_type mdrsel_selection; /*!< message discarding rule select when overflow */
can_msg_sending_rule_type mmssr_selection; /*!< multiple message sending sequence rule */
} can_base_type;
/**
@@ -352,14 +352,14 @@ typedef struct
*/
typedef struct
{
uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/
can_rsaw_type rsaw_size; /*!< resynchronization adjust width */
uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/
can_rsaw_type rsaw_size; /*!< resynchronization adjust width */
can_bts1_type bts1_size; /*!< bit time segment 1 */
can_bts2_type bts2_size; /*!< bit time segment 2 */
} can_baudrate_type;
/**
@@ -368,24 +368,24 @@ typedef struct
typedef struct
{
confirm_state filter_activate_enable; /*!< enable or disable the filter activate.*/
can_filter_mode_type filter_mode; /*!< config the filter mode mask or list.*/
can_filter_fifo_type filter_fifo; /*!< config the fifo which will be assigned to the filter. */
uint8_t filter_number; /*!< config the filter number, parameter ranges from 0 to 13. */
can_filter_bit_width_type filter_bit; /*!< config the filter bit width 16bit or 32bit.*/
uint16_t filter_id_high; /*!< config the filter identification, for 32-bit configuration
it's high 16 bits, for 16-bit configuration it's first. */
uint16_t filter_id_low; /*!< config the filter identification, for 32-bit configuration
it's low 16 bits, for 16-bit configuration it's second. */
can_filter_mode_type filter_mode; /*!< config the filter mode mask or list.*/
can_filter_fifo_type filter_fifo; /*!< config the fifo which will be assigned to the filter. */
uint8_t filter_number; /*!< config the filter number, parameter ranges from 0 to 13. */
can_filter_bit_width_type filter_bit; /*!< config the filter bit width 16bit or 32bit.*/
uint16_t filter_id_high; /*!< config the filter identification, for 32-bit configuration
it's high 16 bits, for 16-bit configuration it's first. */
uint16_t filter_id_low; /*!< config the filter identification, for 32-bit configuration
it's low 16 bits, for 16-bit configuration it's second. */
uint16_t filter_mask_high; /*!< config the filter mask or identification, according to the filtering mode,
for 32-bit configuration it's high 16 bits, for 16-bit configuration it's first. */
for 32-bit configuration it's high 16 bits, for 16-bit configuration it's first. */
uint16_t filter_mask_low; /*!< config the filter mask or identification, according to the filtering mode,
for 32-bit configuration it's low 16 bits, for 16-bit configuration it's second. */
} can_filter_init_type;
@@ -397,19 +397,19 @@ typedef struct
{
uint32_t standard_id; /*!< specifies the 11 bits standard identifier.
this parameter can be a value between 0 to 0x7FF. */
uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
this parameter can be a value between 0 to 0x1FFFFFFF. */
can_identifier_type id_type; /*!< specifies identifier type for the transmit message.*/
can_trans_frame_type frame_type; /*!< specifies frame type for the transmit message.*/
uint8_t dlc; /*!< specifies frame data length that will be transmitted.
uint8_t dlc; /*!< specifies frame data length that will be transmitted.
this parameter can be a value between 0 to 8 */
uint8_t data[8]; /*!< contains the transmit data. it ranges from 0 to 0xFF. */
} can_tx_message_type;
/**
@@ -417,22 +417,22 @@ typedef struct
*/
typedef struct
{
uint32_t standard_id; /*!< specifies the 11 bits standard identifier
uint32_t standard_id; /*!< specifies the 11 bits standard identifier
this parameter can be a value between 0 to 0x7FF. */
uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
this parameter can be a value between 0 to 0x1FFFFFFF. */
can_identifier_type id_type; /*!< specifies identifier type for the receive message.*/
can_trans_frame_type frame_type; /*!< specifies frame type for the receive message.*/
uint8_t dlc; /*!< specifies the frame data length that will be received.
this parameter can be a value between 0 to 8 */
uint8_t data[8]; /*!< contains the receive data. it ranges from 0 to 0xFF.*/
uint8_t filter_index; /*!< specifies the message stored in which filter
uint8_t filter_index; /*!< specifies the message stored in which filter
this parameter can be a value between 0 to 0xFF */
} can_rx_message_type;
@@ -443,36 +443,36 @@ typedef struct
{
/**
* @brief can tmi register
*/
*/
union
{
__IO uint32_t tmi;
struct
{
__IO uint32_t tmsr : 1; /* [0] */
__IO uint32_t tmsr : 1; /* [0] */
__IO uint32_t tmfrsel : 1; /* [1] */
__IO uint32_t tmidsel : 1; /* [2] */
__IO uint32_t tmeid : 18;/* [20:3] */
__IO uint32_t tmsid : 11;/* [31:21] */
} tmi_bit;
};
__IO uint32_t tmeid : 18;/* [20:3] */
__IO uint32_t tmsid : 11;/* [31:21] */
} tmi_bit;
};
/**
* @brief can tmc register
*/
*/
union
{
__IO uint32_t tmc;
struct
{
__IO uint32_t tmdtbl : 4; /* [3:0] */
__IO uint32_t reserved1 : 4; /* [7:4] */
__IO uint32_t tmdtbl : 4; /* [3:0] */
__IO uint32_t reserved1 : 4; /* [7:4] */
__IO uint32_t tmtsten : 1; /* [8] */
__IO uint32_t reserved2 : 7; /* [15:9] */
__IO uint32_t tmts : 16;/* [31:16] */
} tmc_bit;
__IO uint32_t reserved2 : 7; /* [15:9] */
__IO uint32_t tmts : 16;/* [31:16] */
} tmc_bit;
};
/**
* @brief can tmdtl register
*/
@@ -481,13 +481,13 @@ typedef struct
__IO uint32_t tmdtl;
struct
{
__IO uint32_t tmdt0 : 8; /* [7:0] */
__IO uint32_t tmdt1 : 8; /* [15:8] */
__IO uint32_t tmdt2 : 8; /* [23:16] */
__IO uint32_t tmdt3 : 8; /* [31:24] */
} tmdtl_bit;
__IO uint32_t tmdt0 : 8; /* [7:0] */
__IO uint32_t tmdt1 : 8; /* [15:8] */
__IO uint32_t tmdt2 : 8; /* [23:16] */
__IO uint32_t tmdt3 : 8; /* [31:24] */
} tmdtl_bit;
};
/**
* @brief can tmdth register
*/
@@ -496,11 +496,11 @@ typedef struct
__IO uint32_t tmdth;
struct
{
__IO uint32_t tmdt4 : 8; /* [7:0] */
__IO uint32_t tmdt5 : 8; /* [15:8] */
__IO uint32_t tmdt6 : 8; /* [23:16] */
__IO uint32_t tmdt7 : 8; /* [31:24] */
} tmdth_bit;
__IO uint32_t tmdt4 : 8; /* [7:0] */
__IO uint32_t tmdt5 : 8; /* [15:8] */
__IO uint32_t tmdt6 : 8; /* [23:16] */
__IO uint32_t tmdt7 : 8; /* [31:24] */
} tmdth_bit;
};
} can_tx_mailbox_type;
@@ -517,28 +517,28 @@ typedef struct
__IO uint32_t rfi;
struct
{
__IO uint32_t reserved1 : 1; /* [0] */
__IO uint32_t rffri : 1; /* [1] */
__IO uint32_t rfidi : 1; /* [2] */
__IO uint32_t rfeid : 18;/* [20:3] */
__IO uint32_t rfsid : 11;/* [31:21] */
} rfi_bit;
__IO uint32_t reserved1 : 1; /* [0] */
__IO uint32_t rffri : 1; /* [1] */
__IO uint32_t rfidi : 1; /* [2] */
__IO uint32_t rfeid : 18;/* [20:3] */
__IO uint32_t rfsid : 11;/* [31:21] */
} rfi_bit;
};
/**
* @brief can rfc register
* @brief can rfc register
*/
union
{
__IO uint32_t rfc;
struct
{
__IO uint32_t rfdtl : 4; /* [3:0] */
__IO uint32_t reserved1 : 4; /* [7:4] */
__IO uint32_t rffmn : 8; /* [15:8] */
__IO uint32_t rfts : 16;/* [31:16] */
} rfc_bit;
};
{
__IO uint32_t rfdtl : 4; /* [3:0] */
__IO uint32_t reserved1 : 4; /* [7:4] */
__IO uint32_t rffmn : 8; /* [15:8] */
__IO uint32_t rfts : 16;/* [31:16] */
} rfc_bit;
};
/**
* @brief can rfdtl register
@@ -547,13 +547,13 @@ typedef struct
{
__IO uint32_t rfdtl;
struct
{
__IO uint32_t rfdt0 : 8; /* [7:0] */
__IO uint32_t rfdt1 : 8; /* [15:8] */
__IO uint32_t rfdt2 : 8; /* [23:16] */
__IO uint32_t rfdt3 : 8; /* [31:24] */
} rfdtl_bit;
};
{
__IO uint32_t rfdt0 : 8; /* [7:0] */
__IO uint32_t rfdt1 : 8; /* [15:8] */
__IO uint32_t rfdt2 : 8; /* [23:16] */
__IO uint32_t rfdt3 : 8; /* [31:24] */
} rfdtl_bit;
};
/**
* @brief can rfdth register
@@ -562,13 +562,13 @@ typedef struct
{
__IO uint32_t rfdth;
struct
{
__IO uint32_t rfdt4 : 8; /* [7:0] */
__IO uint32_t rfdt5 : 8; /* [15:8] */
__IO uint32_t rfdt6 : 8; /* [23:16] */
__IO uint32_t rfdt7 : 8; /* [31:24] */
} rfdth_bit;
};
{
__IO uint32_t rfdt4 : 8; /* [7:0] */
__IO uint32_t rfdt5 : 8; /* [15:8] */
__IO uint32_t rfdt6 : 8; /* [23:16] */
__IO uint32_t rfdt7 : 8; /* [31:24] */
} rfdth_bit;
};
} can_fifo_mailbox_type;
/**
@@ -585,9 +585,9 @@ typedef struct
*/
typedef struct
{
/**
* @brief can mctrl register, offset:0x00
* @brief can mctrl register, offset:0x00
*/
union
{
@@ -596,21 +596,21 @@ typedef struct
{
__IO uint32_t fzen : 1; /* [0] */
__IO uint32_t dzen : 1; /* [1] */
__IO uint32_t mmssr : 1; /* [2] */
__IO uint32_t mmssr : 1; /* [2] */
__IO uint32_t mdrsel : 1; /* [3] */
__IO uint32_t prsfen : 1; /* [4] */
__IO uint32_t aeden : 1; /* [5] */
__IO uint32_t aeden : 1; /* [5] */
__IO uint32_t aeboen : 1; /* [6] */
__IO uint32_t ttcen : 1; /* [7] */
__IO uint32_t reserved1 : 7; /* [14:8] */
__IO uint32_t reserved1 : 7; /* [14:8] */
__IO uint32_t sprst : 1; /* [15] */
__IO uint32_t ptd : 1; /* [16] */
__IO uint32_t ptd : 1; /* [16] */
__IO uint32_t reserved2 : 15;/*[31:17] */
} mctrl_bit;
};
/**
* @brief can msts register, offset:0x04
* @brief can msts register, offset:0x04
*/
union
{
@@ -619,20 +619,20 @@ typedef struct
{
__IO uint32_t fzc : 1; /* [0] */
__IO uint32_t dzc : 1; /* [1] */
__IO uint32_t eoif : 1; /* [2] */
__IO uint32_t eoif : 1; /* [2] */
__IO uint32_t qdzif : 1; /* [3] */
__IO uint32_t edzif : 1; /* [4] */
__IO uint32_t reserved1 : 3; /* [7:5] */
__IO uint32_t reserved1 : 3; /* [7:5] */
__IO uint32_t cuss : 1; /* [8] */
__IO uint32_t curs : 1; /* [9] */
__IO uint32_t lsamprx : 1; /* [10] */
__IO uint32_t realrx : 1; /* [11] */
__IO uint32_t realrx : 1; /* [11] */
__IO uint32_t reserved2 : 20;/*[31:12] */
} msts_bit;
};
/**
* @brief can tsts register, offset:0x08
* @brief can tsts register, offset:0x08
*/
union
{
@@ -641,34 +641,34 @@ typedef struct
{
__IO uint32_t tm0tcf : 1; /* [0] */
__IO uint32_t tm0tsf : 1; /* [1] */
__IO uint32_t tm0alf : 1; /* [2] */
__IO uint32_t tm0alf : 1; /* [2] */
__IO uint32_t tm0tef : 1; /* [3] */
__IO uint32_t reserved1 : 3; /* [6:4] */
__IO uint32_t tm0ct : 1; /* [7] */
__IO uint32_t tm0ct : 1; /* [7] */
__IO uint32_t tm1tcf : 1; /* [8] */
__IO uint32_t tm1tsf : 1; /* [9] */
__IO uint32_t tm1alf : 1; /* [10] */
__IO uint32_t tm1tef : 1; /* [11] */
__IO uint32_t tm1tef : 1; /* [11] */
__IO uint32_t reserved2 : 3; /* [14:12] */
__IO uint32_t tm1ct : 1; /* [15] */
__IO uint32_t tm2tcf : 1; /* [16] */
__IO uint32_t tm2tcf : 1; /* [16] */
__IO uint32_t tm2tsf : 1; /* [17] */
__IO uint32_t tm2alf : 1; /* [18] */
__IO uint32_t tm2tef : 1; /* [19] */
__IO uint32_t tm2tef : 1; /* [19] */
__IO uint32_t reserved3 : 3; /* [22:20] */
__IO uint32_t tm2ct : 1; /* [23] */
__IO uint32_t tmnr : 2; /* [25:24] */
__IO uint32_t tm0ef : 1; /* [26] */
__IO uint32_t tm1ef : 1; /* [27] */
__IO uint32_t tm2ef : 1; /* [28] */
__IO uint32_t tm0lpf : 1; /* [29] */
__IO uint32_t tm1lpf : 1; /* [30] */
__IO uint32_t tm2lpf : 1; /* [31] */
__IO uint32_t tm0ef : 1; /* [26] */
__IO uint32_t tm1ef : 1; /* [27] */
__IO uint32_t tm2ef : 1; /* [28] */
__IO uint32_t tm0lpf : 1; /* [29] */
__IO uint32_t tm1lpf : 1; /* [30] */
__IO uint32_t tm2lpf : 1; /* [31] */
} tsts_bit;
};
/**
* @brief can rf0 register, offset:0x0C
* @brief can rf0 register, offset:0x0C
*/
union
{
@@ -677,15 +677,15 @@ typedef struct
{
__IO uint32_t rf0mn : 2; /* [1:0] */
__IO uint32_t reserved1 : 1; /* [2] */
__IO uint32_t rf0ff : 1; /* [3] */
__IO uint32_t rf0ff : 1; /* [3] */
__IO uint32_t rf0of : 1; /* [4] */
__IO uint32_t rf0r : 1; /* [5] */
__IO uint32_t reserved2 : 26;/* [31:6] */
} rf0_bit;
};
/**
* @brief can rf1 register, offset:0x10
* @brief can rf1 register, offset:0x10
*/
union
{
@@ -694,231 +694,231 @@ typedef struct
{
__IO uint32_t rf1mn : 2; /* [1:0] */
__IO uint32_t reserved1 : 1; /* [2] */
__IO uint32_t rf1ff : 1; /* [3] */
__IO uint32_t rf1ff : 1; /* [3] */
__IO uint32_t rf1of : 1; /* [4] */
__IO uint32_t rf1r : 1; /* [5] */
__IO uint32_t reserved2 : 26;/* [31:6] */
} rf1_bit;
};
};
/**
* @brief can inten register, offset:0x14
* @brief can inten register, offset:0x14
*/
union
{
__IO uint32_t inten;
struct
{
__IO uint32_t tcien : 1; /* [0] */
__IO uint32_t tcien : 1; /* [0] */
__IO uint32_t rf0mien : 1; /* [1] */
__IO uint32_t rf0fien : 1; /* [2] */
__IO uint32_t rf0oien : 1; /* [3] */
__IO uint32_t rf0oien : 1; /* [3] */
__IO uint32_t rf1mien : 1; /* [4] */
__IO uint32_t rf1fien : 1; /* [5] */
__IO uint32_t rf1oien : 1; /* [6] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t eaien : 1; /* [8] */
__IO uint32_t eaien : 1; /* [8] */
__IO uint32_t epien : 1; /* [9] */
__IO uint32_t boien : 1; /* [10] */
__IO uint32_t etrien : 1; /* [11] */
__IO uint32_t reserved2 : 3; /* [14:12] */
__IO uint32_t eoien : 1; /* [15] */
__IO uint32_t eoien : 1; /* [15] */
__IO uint32_t qdzien : 1; /* [16] */
__IO uint32_t edzien : 1; /* [17] */
__IO uint32_t edzien : 1; /* [17] */
__IO uint32_t reserved3 : 14;/* [31:18] */
} inten_bit;
};
/**
* @brief can ests register, offset:0x18
* @brief can ests register, offset:0x18
*/
union
{
__IO uint32_t ests;
struct
{
__IO uint32_t eaf : 1; /* [0] */
__IO uint32_t eaf : 1; /* [0] */
__IO uint32_t epf : 1; /* [1] */
__IO uint32_t bof : 1; /* [2] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t etr : 3; /* [6:4] */
__IO uint32_t reserved2 : 9; /* [15:7] */
__IO uint32_t tec : 8; /* [23:16] */
__IO uint32_t tec : 8; /* [23:16] */
__IO uint32_t rec : 8; /* [31:24] */
} ests_bit;
} ests_bit;
};
/**
* @brief can btmg register, offset:0x1C
* @brief can btmg register, offset:0x1C
*/
union
{
__IO uint32_t btmg;
struct
{
__IO uint32_t brdiv : 12;/* [11:0] */
__IO uint32_t brdiv : 12;/* [11:0] */
__IO uint32_t reserved1 : 4; /* [15:12] */
__IO uint32_t bts1 : 4; /* [19:16] */
__IO uint32_t bts2 : 3; /* [22:20] */
__IO uint32_t bts2 : 3; /* [22:20] */
__IO uint32_t reserved2 : 1; /* [23] */
__IO uint32_t rsaw : 2; /* [25:24] */
__IO uint32_t reserved3 : 4; /* [29:26] */
__IO uint32_t reserved3 : 4; /* [29:26] */
__IO uint32_t lben : 1; /* [30] */
__IO uint32_t loen : 1; /* [31] */
} btmg_bit;
};
__IO uint32_t loen : 1; /* [31] */
} btmg_bit;
};
/**
* @brief can reserved register, offset:0x20~0x17C
*/
__IO uint32_t reserved1[88];
/**
* @brief can controller area network tx mailbox register, offset:0x180~0x1AC
*/
can_tx_mailbox_type tx_mailbox[3];
/**
* @brief can controller area network fifo mailbox register, offset:0x1B0~0x1CC
*/
can_fifo_mailbox_type fifo_mailbox[2];
/**
* @brief can reserved register, offset:0x1D0~0x1FC
*/
__IO uint32_t reserved2[12];
/**
* @brief can fctrl register, offset:0x200
* @brief can fctrl register, offset:0x200
*/
union
{
__IO uint32_t fctrl;
struct
{
__IO uint32_t fcs : 1; /* [0] */
__IO uint32_t reserved1 : 31;/* [31:1] */
} fctrl_bit;
};
{
__IO uint32_t fcs : 1; /* [0] */
__IO uint32_t reserved1 : 31;/* [31:1] */
} fctrl_bit;
};
/**
* @brief can fmcfg register, offset:0x204
* @brief can fmcfg register, offset:0x204
*/
union
{
__IO uint32_t fmcfg;
struct
{
__IO uint32_t fmsel0 : 1; /* [0] */
__IO uint32_t fmsel1 : 1; /* [1] */
__IO uint32_t fmsel2 : 1; /* [2] */
__IO uint32_t fmsel3 : 1; /* [3] */
__IO uint32_t fmsel4 : 1; /* [4] */
__IO uint32_t fmsel5 : 1; /* [5] */
__IO uint32_t fmsel6 : 1; /* [6] */
__IO uint32_t fmsel7 : 1; /* [7] */
__IO uint32_t fmsel8 : 1; /* [8] */
__IO uint32_t fmsel9 : 1; /* [9] */
__IO uint32_t fmsel10 : 1; /* [10] */
__IO uint32_t fmsel11 : 1; /* [11] */
__IO uint32_t fmsel12 : 1; /* [12] */
__IO uint32_t fmsel13 : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} fmcfg_bit;
};
{
__IO uint32_t fmsel0 : 1; /* [0] */
__IO uint32_t fmsel1 : 1; /* [1] */
__IO uint32_t fmsel2 : 1; /* [2] */
__IO uint32_t fmsel3 : 1; /* [3] */
__IO uint32_t fmsel4 : 1; /* [4] */
__IO uint32_t fmsel5 : 1; /* [5] */
__IO uint32_t fmsel6 : 1; /* [6] */
__IO uint32_t fmsel7 : 1; /* [7] */
__IO uint32_t fmsel8 : 1; /* [8] */
__IO uint32_t fmsel9 : 1; /* [9] */
__IO uint32_t fmsel10 : 1; /* [10] */
__IO uint32_t fmsel11 : 1; /* [11] */
__IO uint32_t fmsel12 : 1; /* [12] */
__IO uint32_t fmsel13 : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} fmcfg_bit;
};
/**
* @brief can reserved register, offset:0x208
* @brief can reserved register, offset:0x208
*/
__IO uint32_t reserved3;
/**
* @brief can fbwcfg register, offset:0x20C
* @brief can fbwcfg register, offset:0x20C
*/
union
{
__IO uint32_t fbwcfg;
struct
{
__IO uint32_t fbwsel0 : 1; /* [0] */
__IO uint32_t fbwsel1 : 1; /* [1] */
__IO uint32_t fbwsel2 : 1; /* [2] */
__IO uint32_t fbwsel3 : 1; /* [3] */
__IO uint32_t fbwsel4 : 1; /* [4] */
__IO uint32_t fbwsel5 : 1; /* [5] */
__IO uint32_t fbwsel6 : 1; /* [6] */
__IO uint32_t fbwsel7 : 1; /* [7] */
__IO uint32_t fbwsel8 : 1; /* [8] */
__IO uint32_t fbwsel9 : 1; /* [9] */
__IO uint32_t fbwsel10 : 1; /* [10] */
__IO uint32_t fbwsel11 : 1; /* [11] */
__IO uint32_t fbwsel12 : 1; /* [12] */
__IO uint32_t fbwsel13 : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} fbwcfg_bit;
};
{
__IO uint32_t fbwsel0 : 1; /* [0] */
__IO uint32_t fbwsel1 : 1; /* [1] */
__IO uint32_t fbwsel2 : 1; /* [2] */
__IO uint32_t fbwsel3 : 1; /* [3] */
__IO uint32_t fbwsel4 : 1; /* [4] */
__IO uint32_t fbwsel5 : 1; /* [5] */
__IO uint32_t fbwsel6 : 1; /* [6] */
__IO uint32_t fbwsel7 : 1; /* [7] */
__IO uint32_t fbwsel8 : 1; /* [8] */
__IO uint32_t fbwsel9 : 1; /* [9] */
__IO uint32_t fbwsel10 : 1; /* [10] */
__IO uint32_t fbwsel11 : 1; /* [11] */
__IO uint32_t fbwsel12 : 1; /* [12] */
__IO uint32_t fbwsel13 : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} fbwcfg_bit;
};
/**
* @brief can reserved register, offset:0x210
* @brief can reserved register, offset:0x210
*/
__IO uint32_t reserved4;
/**
* @brief can frf register, offset:0x214
*/
* @brief can frf register, offset:0x214
*/
union
{
__IO uint32_t frf;
struct
{
__IO uint32_t frfsel0 : 1; /* [0] */
__IO uint32_t frfsel1 : 1; /* [1] */
__IO uint32_t frfsel2 : 1; /* [2] */
__IO uint32_t frfsel3 : 1; /* [3] */
__IO uint32_t frfsel4 : 1; /* [4] */
__IO uint32_t frfsel5 : 1; /* [5] */
__IO uint32_t frfsel6 : 1; /* [6] */
__IO uint32_t frfsel7 : 1; /* [7] */
__IO uint32_t frfsel8 : 1; /* [8] */
__IO uint32_t frfsel9 : 1; /* [9] */
__IO uint32_t frfsel10 : 1; /* [10] */
__IO uint32_t frfsel11 : 1; /* [11] */
__IO uint32_t frfsel12 : 1; /* [12] */
__IO uint32_t frfsel13 : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} frf_bit;
};
{
__IO uint32_t frfsel0 : 1; /* [0] */
__IO uint32_t frfsel1 : 1; /* [1] */
__IO uint32_t frfsel2 : 1; /* [2] */
__IO uint32_t frfsel3 : 1; /* [3] */
__IO uint32_t frfsel4 : 1; /* [4] */
__IO uint32_t frfsel5 : 1; /* [5] */
__IO uint32_t frfsel6 : 1; /* [6] */
__IO uint32_t frfsel7 : 1; /* [7] */
__IO uint32_t frfsel8 : 1; /* [8] */
__IO uint32_t frfsel9 : 1; /* [9] */
__IO uint32_t frfsel10 : 1; /* [10] */
__IO uint32_t frfsel11 : 1; /* [11] */
__IO uint32_t frfsel12 : 1; /* [12] */
__IO uint32_t frfsel13 : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} frf_bit;
};
/**
* @brief can reserved register, offset:0x218
* @brief can reserved register, offset:0x218
*/
__IO uint32_t reserved5;
/**
* @brief can facfg register, offset:0x21C
*/
* @brief can facfg register, offset:0x21C
*/
union
{
__IO uint32_t facfg;
struct
{
__IO uint32_t faen0 : 1; /* [0] */
__IO uint32_t faen1 : 1; /* [1] */
__IO uint32_t faen2 : 1; /* [2] */
__IO uint32_t faen3 : 1; /* [3] */
__IO uint32_t faen4 : 1; /* [4] */
__IO uint32_t faen5 : 1; /* [5] */
__IO uint32_t faen6 : 1; /* [6] */
__IO uint32_t faen7 : 1; /* [7] */
__IO uint32_t faen8 : 1; /* [8] */
__IO uint32_t faen9 : 1; /* [9] */
__IO uint32_t faen10 : 1; /* [10] */
__IO uint32_t faen11 : 1; /* [11] */
__IO uint32_t faen12 : 1; /* [12] */
__IO uint32_t faen13 : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} facfg_bit;
};
{
__IO uint32_t faen0 : 1; /* [0] */
__IO uint32_t faen1 : 1; /* [1] */
__IO uint32_t faen2 : 1; /* [2] */
__IO uint32_t faen3 : 1; /* [3] */
__IO uint32_t faen4 : 1; /* [4] */
__IO uint32_t faen5 : 1; /* [5] */
__IO uint32_t faen6 : 1; /* [6] */
__IO uint32_t faen7 : 1; /* [7] */
__IO uint32_t faen8 : 1; /* [8] */
__IO uint32_t faen9 : 1; /* [9] */
__IO uint32_t faen10 : 1; /* [10] */
__IO uint32_t faen11 : 1; /* [11] */
__IO uint32_t faen12 : 1; /* [12] */
__IO uint32_t faen13 : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} facfg_bit;
};
/**
* @brief can reserved register, offset:0x220~0x23C
@@ -929,19 +929,19 @@ typedef struct
* @brief can ffb register, offset:0x240~0x2AC
*/
can_filter_register_type ffb[14];
} can_type;
} can_type;
/**
* @}
*/
#define CAN1 ((can_type *) CAN1_BASE)
#define CAN2 ((can_type *) CAN2_BASE)
/** @defgroup CAN_exported_functions
* @{
*/
void can_reset(can_type* can_x);
void can_baudrate_default_para_init(can_baudrate_type* can_baudrate_struct);
error_status can_baudrate_set(can_type* can_x, can_baudrate_type* can_baudrate_struct);

22
libraries/drivers/inc/at32f413_crc.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_crc.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 crc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -74,7 +74,7 @@ typedef enum
typedef struct
{
/**
* @brief crc dt register, offset:0x00
* @brief crc dt register, offset:0x00
*/
union
{
@@ -86,7 +86,7 @@ typedef struct
};
/**
* @brief crc cdt register, offset:0x04
* @brief crc cdt register, offset:0x04
*/
union
{
@@ -99,7 +99,7 @@ typedef struct
};
/**
* @brief crc ctrl register, offset:0x08
* @brief crc ctrl register, offset:0x08
*/
union
{
@@ -120,7 +120,7 @@ typedef struct
__IO uint32_t reserved1;
/**
* @brief crc idt register, offset:0x10
* @brief crc idt register, offset:0x10
*/
union
{

38
libraries/drivers/inc/at32f413_crm.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_crm.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 crm header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -43,15 +43,15 @@ extern "C" {
/** @addtogroup CRM
* @{
*/
#define CRM_REG(value) PERIPH_REG(CRM_BASE, value)
#define CRM_REG_BIT(value) PERIPH_REG_BIT(value)
/** @defgroup CRM_flags_definition
* @brief crm flag
/** @defgroup CRM_flags_definition
* @brief crm flag
* @{
*/
#define CRM_HICK_STABLE_FLAG MAKE_VALUE(0x00, 1) /*!< high speed internal clock stable flag */
#define CRM_HEXT_STABLE_FLAG MAKE_VALUE(0x00, 17) /*!< high speed external crystal stable flag */
#define CRM_PLL_STABLE_FLAG MAKE_VALUE(0x00, 25) /*!< phase locking loop stable flag */
@@ -74,12 +74,12 @@ extern "C" {
/**
* @}
*/
/** @defgroup CRM_interrupts_definition
* @brief crm interrupt
* @brief crm interrupt
* @{
*/
#define CRM_LICK_STABLE_INT ((uint32_t)0x00000100) /*!< low speed internal clock stable interrupt */
#define CRM_LEXT_STABLE_INT ((uint32_t)0x00000200) /*!< low speed external crystal stable interrupt */
#define CRM_HICK_STABLE_INT ((uint32_t)0x00000400) /*!< high speed internal clock stable interrupt */
@@ -482,7 +482,7 @@ typedef struct
typedef struct
{
/**
* @brief crm ctrl register, offset:0x00
* @brief crm ctrl register, offset:0x00
*/
union
{
@@ -505,7 +505,7 @@ typedef struct
};
/**
* @brief crm cfg register, offset:0x04
* @brief crm cfg register, offset:0x04
*/
union
{
@@ -531,7 +531,7 @@ typedef struct
};
/**
* @brief crm clkint register, offset:0x08
* @brief crm clkint register, offset:0x08
*/
union
{
@@ -665,7 +665,7 @@ typedef struct
__IO uint32_t gpioden : 1; /* [5] */
__IO uint32_t reserved2 : 1; /* [6] */
__IO uint32_t gpiofen : 1; /* [7] */
__IO uint32_t reserved3 : 1; /* [8] */
__IO uint32_t reserved3 : 1; /* [8] */
__IO uint32_t adc1en : 1; /* [9] */
__IO uint32_t adc2en : 1; /* [10] */
__IO uint32_t tmr1en : 1; /* [11] */

58
libraries/drivers/inc/at32f413_debug.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_debug.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 debug header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,8 +31,8 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f413.h"
@@ -49,20 +49,20 @@ extern "C" {
*/
#define DEBUG_SLEEP 0x00000001 /*!< debug sleep mode */
#define DEBUG_DEEPSLEEP 0x00000002 /*!< debug deepsleep mode */
#define DEBUG_STANDBY 0x00000004 /*!< debug standby mode */
#define DEBUG_WDT_PAUSE 0x00000100 /*!< debug watchdog timer pause */
#define DEBUG_WWDT_PAUSE 0x00000200 /*!< debug window watchdog timer pause */
#define DEBUG_TMR1_PAUSE 0x00000400 /*!< debug timer1 pause */
#define DEBUG_TMR2_PAUSE 0x00000800 /*!< debug timer2 pause */
#define DEBUG_TMR3_PAUSE 0x00001000 /*!< debug timer3 pause */
#define DEBUG_TMR4_PAUSE 0x00002000 /*!< debug timer4 pause */
#define DEBUG_CAN1_PAUSE 0x00004000 /*!< debug can1 pause */
#define DEBUG_I2C1_SMBUS_TIMEOUT 0x00008000 /*!< debug i2c1 smbus timeout */
#define DEBUG_I2C2_SMBUS_TIMEOUT 0x00010000 /*!< debug i2c2 smbus timeout */
#define DEBUG_TMR8_PAUSE 0x00020000 /*!< debug timer8 pause */
#define DEBUG_TMR5_PAUSE 0x00040000 /*!< debug timer5 pause */
#define DEBUG_CAN2_PAUSE 0x00200000 /*!< debug can2 pause */
#define DEBUG_DEEPSLEEP 0x00000002 /*!< debug deepsleep mode */
#define DEBUG_STANDBY 0x00000004 /*!< debug standby mode */
#define DEBUG_WDT_PAUSE 0x00000100 /*!< debug watchdog timer pause */
#define DEBUG_WWDT_PAUSE 0x00000200 /*!< debug window watchdog timer pause */
#define DEBUG_TMR1_PAUSE 0x00000400 /*!< debug timer1 pause */
#define DEBUG_TMR2_PAUSE 0x00000800 /*!< debug timer2 pause */
#define DEBUG_TMR3_PAUSE 0x00001000 /*!< debug timer3 pause */
#define DEBUG_TMR4_PAUSE 0x00002000 /*!< debug timer4 pause */
#define DEBUG_CAN1_PAUSE 0x00004000 /*!< debug can1 pause */
#define DEBUG_I2C1_SMBUS_TIMEOUT 0x00008000 /*!< debug i2c1 smbus timeout */
#define DEBUG_I2C2_SMBUS_TIMEOUT 0x00010000 /*!< debug i2c2 smbus timeout */
#define DEBUG_TMR8_PAUSE 0x00020000 /*!< debug timer8 pause */
#define DEBUG_TMR5_PAUSE 0x00040000 /*!< debug timer5 pause */
#define DEBUG_CAN2_PAUSE 0x00200000 /*!< debug can2 pause */
#define DEBUG_TMR9_PAUSE 0x10000000 /*!< debug timer9 pause */
#define DEBUG_TMR10_PAUSE 0x20000000 /*!< debug timer10 pause */
#define DEBUG_TMR11_PAUSE 0x40000000 /*!< debug timer11 pause */
@@ -105,9 +105,9 @@ typedef struct
__IO uint32_t standby_debug : 1;/* [2] */
__IO uint32_t reserved1 : 2;/* [4:3] */
__IO uint32_t trace_ioen : 1;/* [5] */
__IO uint32_t trace_mode : 2;/* [7:6] */
__IO uint32_t wdt_pause : 1;/* [8] */
__IO uint32_t wwdt_pause : 1;/* [9] */
__IO uint32_t trace_mode : 2;/* [7:6] */
__IO uint32_t wdt_pause : 1;/* [8] */
__IO uint32_t wwdt_pause : 1;/* [9] */
__IO uint32_t tmr1_pause : 1;/* [10] */
__IO uint32_t tmr2_pause : 1;/* [11] */
__IO uint32_t tmr3_pause : 1;/* [12] */
@@ -117,13 +117,13 @@ typedef struct
__IO uint32_t i2c2_smbus_timeout : 1;/* [16] */
__IO uint32_t tmr8_pause : 1;/* [17] */
__IO uint32_t tmr5_pause : 1;/* [18] */
__IO uint32_t reserved2 : 2;/* [20:19] */
__IO uint32_t reserved2 : 2;/* [20:19] */
__IO uint32_t can2_pause : 1;/* [21] */
__IO uint32_t reserved3 : 6;/* [27:22] */
__IO uint32_t reserved3 : 6;/* [27:22] */
__IO uint32_t tmr9_pause : 1;/* [28] */
__IO uint32_t tmr10_pause : 1;/* [29] */
__IO uint32_t tmr11_pause : 1;/* [30] */
__IO uint32_t reserved4 : 1;/* [31] */
__IO uint32_t reserved4 : 1;/* [31] */
} ctrl_bit;
};

14
libraries/drivers/inc/at32f413_def.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_def.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 macros header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,

6
libraries/drivers/inc/at32f413_dma.h
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f413_dma.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 dma header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -206,7 +206,7 @@ typedef enum
DMA_FLEXIBLE_TMR8_CH1 = 0x70, /*!< tmr8_ch1 flexible request id */
DMA_FLEXIBLE_TMR8_CH2 = 0x71, /*!< tmr8_ch2 flexible request id */
DMA_FLEXIBLE_TMR8_CH3 = 0x72, /*!< tmr8_ch3 flexible request id */
DMA_FLEXIBLE_TMR8_CH4 = 0x73, /*!< tmr8_ch4 flexible request id */
DMA_FLEXIBLE_TMR8_CH4 = 0x73, /*!< tmr8_ch4 flexible request id */
} dma_flexible_request_type;
/**

98
libraries/drivers/inc/at32f413_exint.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_exint.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 exint header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,8 +31,8 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f413.h"
@@ -49,25 +49,25 @@ extern "C" {
*/
#define EXINT_LINE_NONE ((uint32_t)0x000000)
#define EXINT_LINE_0 ((uint32_t)0x000001) /*!< external interrupt line 0 */
#define EXINT_LINE_1 ((uint32_t)0x000002) /*!< external interrupt line 1 */
#define EXINT_LINE_2 ((uint32_t)0x000004) /*!< external interrupt line 2 */
#define EXINT_LINE_3 ((uint32_t)0x000008) /*!< external interrupt line 3 */
#define EXINT_LINE_4 ((uint32_t)0x000010) /*!< external interrupt line 4 */
#define EXINT_LINE_5 ((uint32_t)0x000020) /*!< external interrupt line 5 */
#define EXINT_LINE_6 ((uint32_t)0x000040) /*!< external interrupt line 6 */
#define EXINT_LINE_7 ((uint32_t)0x000080) /*!< external interrupt line 7 */
#define EXINT_LINE_8 ((uint32_t)0x000100) /*!< external interrupt line 8 */
#define EXINT_LINE_9 ((uint32_t)0x000200) /*!< external interrupt line 9 */
#define EXINT_LINE_10 ((uint32_t)0x000400) /*!< external interrupt line 10 */
#define EXINT_LINE_11 ((uint32_t)0x000800) /*!< external interrupt line 11 */
#define EXINT_LINE_12 ((uint32_t)0x001000) /*!< external interrupt line 12 */
#define EXINT_LINE_13 ((uint32_t)0x002000) /*!< external interrupt line 13 */
#define EXINT_LINE_14 ((uint32_t)0x004000) /*!< external interrupt line 14 */
#define EXINT_LINE_15 ((uint32_t)0x008000) /*!< external interrupt line 15 */
#define EXINT_LINE_16 ((uint32_t)0x010000) /*!< external interrupt line 16 connected to the pvm output */
#define EXINT_LINE_17 ((uint32_t)0x020000) /*!< external interrupt line 17 connected to the rtc alarm event */
#define EXINT_LINE_18 ((uint32_t)0x040000) /*!< external interrupt line 18 connected to the usb fs wakeup from suspend event */
#define EXINT_LINE_0 ((uint32_t)0x000001) /*!< external interrupt line 0 */
#define EXINT_LINE_1 ((uint32_t)0x000002) /*!< external interrupt line 1 */
#define EXINT_LINE_2 ((uint32_t)0x000004) /*!< external interrupt line 2 */
#define EXINT_LINE_3 ((uint32_t)0x000008) /*!< external interrupt line 3 */
#define EXINT_LINE_4 ((uint32_t)0x000010) /*!< external interrupt line 4 */
#define EXINT_LINE_5 ((uint32_t)0x000020) /*!< external interrupt line 5 */
#define EXINT_LINE_6 ((uint32_t)0x000040) /*!< external interrupt line 6 */
#define EXINT_LINE_7 ((uint32_t)0x000080) /*!< external interrupt line 7 */
#define EXINT_LINE_8 ((uint32_t)0x000100) /*!< external interrupt line 8 */
#define EXINT_LINE_9 ((uint32_t)0x000200) /*!< external interrupt line 9 */
#define EXINT_LINE_10 ((uint32_t)0x000400) /*!< external interrupt line 10 */
#define EXINT_LINE_11 ((uint32_t)0x000800) /*!< external interrupt line 11 */
#define EXINT_LINE_12 ((uint32_t)0x001000) /*!< external interrupt line 12 */
#define EXINT_LINE_13 ((uint32_t)0x002000) /*!< external interrupt line 13 */
#define EXINT_LINE_14 ((uint32_t)0x004000) /*!< external interrupt line 14 */
#define EXINT_LINE_15 ((uint32_t)0x008000) /*!< external interrupt line 15 */
#define EXINT_LINE_16 ((uint32_t)0x010000) /*!< external interrupt line 16 connected to the pvm output */
#define EXINT_LINE_17 ((uint32_t)0x020000) /*!< external interrupt line 17 connected to the rtc alarm event */
#define EXINT_LINE_18 ((uint32_t)0x040000) /*!< external interrupt line 18 connected to the usb fs wakeup from suspend event */
/**
* @}
*/
@@ -77,7 +77,7 @@ extern "C" {
*/
/**
* @brief exint line mode type
* @brief exint line mode type
*/
typedef enum
{
@@ -86,7 +86,7 @@ typedef enum
} exint_line_mode_type;
/**
* @brief exint polarity configuration type
* @brief exint polarity configuration type
*/
typedef enum
{
@@ -95,7 +95,7 @@ typedef enum
EXINT_TRIGGER_BOTH_EDGE = 0x02 /*!< external interrupt line both rising and falling trigger mode */
} exint_polarity_config_type;
/**
/**
* @brief exint init type
*/
typedef struct
@@ -110,10 +110,10 @@ typedef struct
* @brief type define exint register all
*/
typedef struct
{
{
/**
* @brief exint inten register, offset:0x00
* @brief exint inten register, offset:0x00
*/
union
{
@@ -124,9 +124,9 @@ typedef struct
__IO uint32_t reserved1 : 9;/* [31:23] */
} inten_bit;
};
/**
* @brief exint evten register, offset:0x04
* @brief exint evten register, offset:0x04
*/
union
{
@@ -137,9 +137,9 @@ typedef struct
__IO uint32_t reserved1 : 9;/* [31:23] */
} evten_bit;
};
/**
* @brief exint polcfg1 register, offset:0x08
* @brief exint polcfg1 register, offset:0x08
*/
union
{
@@ -150,9 +150,9 @@ typedef struct
__IO uint32_t reserved1 : 9;/* [31:23] */
} polcfg1_bit;
};
/**
* @brief exint polcfg2 register, offset:0x0C
* @brief exint polcfg2 register, offset:0x0C
*/
union
{
@@ -162,10 +162,10 @@ typedef struct
__IO uint32_t fpx : 23;/* [22:0] */
__IO uint32_t reserved1 : 9;/* [31:23] */
} polcfg2_bit;
};
};
/**
* @brief exint swtrg register, offset:0x10
* @brief exint swtrg register, offset:0x10
*/
union
{
@@ -176,9 +176,9 @@ typedef struct
__IO uint32_t reserved1 : 9;/* [31:23] */
} swtrg_bit;
};
/**
* @brief exint intsts register, offset:0x14
* @brief exint intsts register, offset:0x14
*/
union
{
@@ -188,14 +188,14 @@ typedef struct
__IO uint32_t linex : 23;/* [22:0] */
__IO uint32_t reserved1 : 9;/* [31:23] */
} intsts_bit;
};
} exint_type;
};
} exint_type;
/**
* @}
*/
#define EXINT ((exint_type *) EXINT_BASE)
#define EXINT ((exint_type *) EXINT_BASE)
/** @defgroup EXINT_exported_functions
* @{

238
libraries/drivers/inc/at32f413_flash.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_flash.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 flash header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,8 +31,8 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f413.h"
@@ -46,7 +46,7 @@ extern "C" {
*/
/** @defgroup FLASH_unlock_keys
* @brief flash unlock keys
* @brief flash unlock keys
* @{
*/
@@ -58,9 +58,9 @@ extern "C" {
/**
* @}
*/
/** @defgroup FLASH_spim_address
* @brief flash spim address
* @brief flash spim address
* @{
*/
#define FLASH_SPIM_START_ADDR ((uint32_t)0x08400000) /*!< flash start address of spim */
@@ -70,7 +70,7 @@ extern "C" {
*/
/** @defgroup FLASH_flags
* @brief flash flag
* @brief flash flag
* @{
*/
@@ -89,7 +89,7 @@ extern "C" {
*/
/** @defgroup FLASH_interrupts
* @brief flash interrupts
* @brief flash interrupts
* @{
*/
@@ -101,11 +101,11 @@ extern "C" {
/**
* @}
*/
/** @defgroup FLASH_slib_mask
* @brief flash slib mask
* @brief flash slib mask
* @{
*/
*/
#define FLASH_SLIB_START_SECTOR ((uint32_t)0x000007FF) /*!< flash slib start sector */
#define FLASH_SLIB_DATA_START_SECTOR ((uint32_t)0x003FF800) /*!< flash slib d-bus area start sector */
@@ -116,9 +116,9 @@ extern "C" {
*/
/** @defgroup FLASH_user_system_data
* @brief flash user system data
* @brief flash user system data
* @{
*/
*/
#define USD_WDT_ATO_DISABLE ((uint16_t)0x0001) /*!< wdt auto start disabled */
#define USD_WDT_ATO_ENABLE ((uint16_t)0x0000) /*!< wdt auto start enabled */
@@ -134,7 +134,7 @@ extern "C" {
*/
/** @defgroup FLASH_timeout_definition
* @brief flash timeout definition
* @brief flash timeout definition
* @{
*/
@@ -163,7 +163,7 @@ typedef enum
FLASH_OPERATE_DONE = 0x03, /*!< flash status is operate done */
FLASH_OPERATE_TIMEOUT = 0x04 /*!< flash status is operate timeout */
} flash_status_type;
/**
* @brief flash spim model type
*/
@@ -177,9 +177,9 @@ typedef enum
* @brief type define flash register all
*/
typedef struct
{
{
/**
* @brief flash psr register, offset:0x00
* @brief flash psr register, offset:0x00
*/
union
{
@@ -189,9 +189,9 @@ typedef struct
__IO uint32_t reserved1 : 32; /* [31:0] */
} psr_bit;
};
/**
* @brief flash unlock register, offset:0x04
* @brief flash unlock register, offset:0x04
*/
union
{
@@ -201,9 +201,9 @@ typedef struct
__IO uint32_t ukval : 32;/* [31:0] */
} unlock_bit;
};
/**
* @brief flash usd unlock register, offset:0x08
* @brief flash usd unlock register, offset:0x08
*/
union
{
@@ -215,7 +215,7 @@ typedef struct
};
/**
* @brief flash sts register, offset:0x0C
* @brief flash sts register, offset:0x0C
*/
union
{
@@ -223,17 +223,17 @@ typedef struct
struct
{
__IO uint32_t obf : 1; /* [0] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t prgmerr : 1; /* [2] */
__IO uint32_t reserved2 : 1; /* [3] */
__IO uint32_t epperr : 1; /* [4] */
__IO uint32_t odf : 1; /* [5] */
__IO uint32_t reserved3 : 26;/* [31:6] */
__IO uint32_t reserved3 : 26;/* [31:6] */
} sts_bit;
};
/**
* @brief flash ctrl register, offset:0x10
* @brief flash ctrl register, offset:0x10
*/
union
{
@@ -241,41 +241,41 @@ typedef struct
struct
{
__IO uint32_t fprgm : 1; /* [0] */
__IO uint32_t secers : 1; /* [1] */
__IO uint32_t secers : 1; /* [1] */
__IO uint32_t bankers : 1; /* [2] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t usdprgm : 1; /* [4] */
__IO uint32_t usders : 1; /* [5] */
__IO uint32_t erstr : 1; /* [6] */
__IO uint32_t oplk : 1; /* [7] */
__IO uint32_t reserved2 : 1; /* [8] */
__IO uint32_t usdulks : 1; /* [9] */
__IO uint32_t errie : 1; /* [10] */
__IO uint32_t reserved3 : 1; /* [11] */
__IO uint32_t odfie : 1; /* [12] */
__IO uint32_t reserved4 : 19;/* [31:13] */
__IO uint32_t erstr : 1; /* [6] */
__IO uint32_t oplk : 1; /* [7] */
__IO uint32_t reserved2 : 1; /* [8] */
__IO uint32_t usdulks : 1; /* [9] */
__IO uint32_t errie : 1; /* [10] */
__IO uint32_t reserved3 : 1; /* [11] */
__IO uint32_t odfie : 1; /* [12] */
__IO uint32_t reserved4 : 19;/* [31:13] */
} ctrl_bit;
};
/**
* @brief flash addr register, offset:0x14
* @brief flash addr register, offset:0x14
*/
union
{
__IO uint32_t addr;
struct
{
__IO uint32_t fa : 32;/* [31:0] */
__IO uint32_t fa : 32;/* [31:0] */
} addr_bit;
};
/**
* @brief flash reserved1 register, offset:0x18
*/
__IO uint32_t reserved1;
/**
* @brief flash usd register, offset:0x1C
* @brief flash usd register, offset:0x1C
*/
union
{
@@ -283,26 +283,26 @@ typedef struct
struct
{
__IO uint32_t usderr : 1; /* [0] */
__IO uint32_t fap : 1; /* [1] */
__IO uint32_t fap : 1; /* [1] */
__IO uint32_t wdt_ato_en : 1; /* [2] */
__IO uint32_t depslp_rst : 1; /* [3] */
__IO uint32_t stdby_rst : 1; /* [4] */
__IO uint32_t reserved1 : 5; /* [9:5] */
__IO uint32_t user_d0 : 8; /* [17:10] */
__IO uint32_t user_d1 : 8; /* [25:18] */
__IO uint32_t reserved2 : 6; /* [31:26] */
__IO uint32_t reserved1 : 5; /* [9:5] */
__IO uint32_t user_d0 : 8; /* [17:10] */
__IO uint32_t user_d1 : 8; /* [25:18] */
__IO uint32_t reserved2 : 6; /* [31:26] */
} usd_bit;
};
/**
* @brief flash epps register, offset:0x20
* @brief flash epps register, offset:0x20
*/
union
{
__IO uint32_t epps;
struct
{
__IO uint32_t epps : 32;/* [31:0] */
__IO uint32_t epps : 32;/* [31:0] */
} epps_bit;
};
@@ -312,7 +312,7 @@ typedef struct
__IO uint32_t reserved2[24];
/**
* @brief flash unlock3 register, offset:0x84
* @brief flash unlock3 register, offset:0x84
*/
union
{
@@ -322,9 +322,9 @@ typedef struct
__IO uint32_t ukval : 32;/* [31:0] */
} unlock3_bit;
};
/**
* @brief flash select register, offset:0x88
* @brief flash select register, offset:0x88
*/
union
{
@@ -334,9 +334,9 @@ typedef struct
__IO uint32_t select : 32;/* [31:0] */
} select_bit;
};
/**
* @brief flash sts3 register, offset:0x8C
* @brief flash sts3 register, offset:0x8C
*/
union
{
@@ -344,17 +344,17 @@ typedef struct
struct
{
__IO uint32_t obf : 1; /* [0] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t prgmerr : 1; /* [2] */
__IO uint32_t reserved2 : 1; /* [3] */
__IO uint32_t epperr : 1; /* [4] */
__IO uint32_t odf : 1; /* [5] */
__IO uint32_t reserved3 : 26;/* [31:6] */
__IO uint32_t reserved3 : 26;/* [31:6] */
} sts3_bit;
};
/**
* @brief flash ctrl3 register, offset:0x90
* @brief flash ctrl3 register, offset:0x90
*/
union
{
@@ -362,176 +362,176 @@ typedef struct
struct
{
__IO uint32_t fprgm : 1; /* [0] */
__IO uint32_t secers : 1; /* [1] */
__IO uint32_t secers : 1; /* [1] */
__IO uint32_t chpers : 1; /* [2] */
__IO uint32_t reserved1 : 3; /* [5:3] */
__IO uint32_t erstr : 1; /* [6] */
__IO uint32_t oplk : 1; /* [7] */
__IO uint32_t reserved2 : 2; /* [9:8] */
__IO uint32_t errie : 1; /* [10] */
__IO uint32_t reserved3 : 1; /* [11] */
__IO uint32_t odfie : 1; /* [12] */
__IO uint32_t reserved4 : 19;/* [31:13] */
__IO uint32_t erstr : 1; /* [6] */
__IO uint32_t oplk : 1; /* [7] */
__IO uint32_t reserved2 : 2; /* [9:8] */
__IO uint32_t errie : 1; /* [10] */
__IO uint32_t reserved3 : 1; /* [11] */
__IO uint32_t odfie : 1; /* [12] */
__IO uint32_t reserved4 : 19;/* [31:13] */
} ctrl3_bit;
};
};
/**
* @brief flash addr3 register, offset:0x94
* @brief flash addr3 register, offset:0x94
*/
union
{
__IO uint32_t addr3;
struct
{
__IO uint32_t fa : 32;/* [31:0] */
__IO uint32_t fa : 32;/* [31:0] */
} addr3_bit;
};
/**
* @brief flash da register, offset:0x98
* @brief flash da register, offset:0x98
*/
union
{
__IO uint32_t da;
struct
{
__IO uint32_t fda : 32;/* [31:0] */
__IO uint32_t fda : 32;/* [31:0] */
} da_bit;
};
/**
* @brief flash reserved5 register, offset:0xC8~0x9C
*/
__IO uint32_t reserved5[12];
/**
* @brief flash slib_sts0 register, offset:0xCC
* @brief flash slib_sts0 register, offset:0xCC
*/
union
{
__IO uint32_t slib_sts0;
struct
{
__IO uint32_t reserved1 : 3; /* [2:0] */
__IO uint32_t slib_enf : 1; /* [3] */
__IO uint32_t reserved2 : 28;/* [31:4] */
__IO uint32_t reserved1 : 3; /* [2:0] */
__IO uint32_t slib_enf : 1; /* [3] */
__IO uint32_t reserved2 : 28;/* [31:4] */
} slib_sts0_bit;
};
/**
* @brief flash slib_sts1 register, offset:0xD0
* @brief flash slib_sts1 register, offset:0xD0
*/
union
{
__IO uint32_t slib_sts1;
struct
{
__IO uint32_t slib_ss : 11;/* [10:0] */
__IO uint32_t slib_dat_ss : 11;/* [21:11] */
__IO uint32_t slib_es : 10;/* [31:22] */
__IO uint32_t slib_ss : 11;/* [10:0] */
__IO uint32_t slib_dat_ss : 11;/* [21:11] */
__IO uint32_t slib_es : 10;/* [31:22] */
} slib_sts1_bit;
};
/**
* @brief flash slib_pwd_clr register, offset:0xD4
* @brief flash slib_pwd_clr register, offset:0xD4
*/
union
{
__IO uint32_t slib_pwd_clr;
struct
{
__IO uint32_t slib_pclr_val : 32;/* [31:0] */
__IO uint32_t slib_pclr_val : 32;/* [31:0] */
} slib_pwd_clr_bit;
};
/**
* @brief flash slib_misc_sts register, offset:0xD8
* @brief flash slib_misc_sts register, offset:0xD8
*/
union
{
__IO uint32_t slib_misc_sts;
struct
{
__IO uint32_t slib_pwd_err : 1; /* [0] */
__IO uint32_t slib_pwd_ok : 1; /* [1] */
__IO uint32_t slib_ulkf : 1; /* [2] */
__IO uint32_t reserved1 : 13;/* [15:3] */
__IO uint32_t slib_rcnt : 9; /* [24:16] */
__IO uint32_t reserved2 : 7; /* [31:25] */
__IO uint32_t slib_pwd_err : 1; /* [0] */
__IO uint32_t slib_pwd_ok : 1; /* [1] */
__IO uint32_t slib_ulkf : 1; /* [2] */
__IO uint32_t reserved1 : 13;/* [15:3] */
__IO uint32_t slib_rcnt : 9; /* [24:16] */
__IO uint32_t reserved2 : 7; /* [31:25] */
} slib_misc_sts_bit;
};
/**
* @brief flash slib_set_pwd register, offset:0xDC
* @brief flash slib_set_pwd register, offset:0xDC
*/
union
{
__IO uint32_t slib_set_pwd;
struct
{
__IO uint32_t slib_pset_val : 32;/* [31:0] */
{
__IO uint32_t slib_pset_val : 32;/* [31:0] */
} slib_set_pwd_bit;
};
/**
* @brief flash slib_set_range register, offset:0xE0
* @brief flash slib_set_range register, offset:0xE0
*/
union
{
__IO uint32_t slib_set_range;
struct
{
__IO uint32_t slib_ss_set : 11;/* [10:0] */
__IO uint32_t slib_dss_set : 11;/* [21:11] */
__IO uint32_t slib_es_set : 10;/* [31:22] */
__IO uint32_t slib_ss_set : 11;/* [10:0] */
__IO uint32_t slib_dss_set : 11;/* [21:11] */
__IO uint32_t slib_es_set : 10;/* [31:22] */
} slib_set_range_bit;
};
/**
* @brief flash reserved6 register, offset:0xEC~0xE4
*/
__IO uint32_t reserved6[3];
/**
* @brief flash slib_unlock register, offset:0xF0
* @brief flash slib_unlock register, offset:0xF0
*/
union
{
__IO uint32_t slib_unlock;
struct
{
__IO uint32_t slib_ukval : 32;/* [31:0] */
{
__IO uint32_t slib_ukval : 32;/* [31:0] */
} slib_unlock_bit;
};
/**
* @brief flash crc_ctrl register, offset:0xF4
* @brief flash crc_ctrl register, offset:0xF4
*/
union
{
__IO uint32_t crc_ctrl;
struct
{
__IO uint32_t crc_ss : 12;/* [11:0] */
__IO uint32_t crc_sn : 12;/* [23:12] */
__IO uint32_t reserved1 : 7; /* [30:24] */
__IO uint32_t crc_strt : 1; /* [31] */
__IO uint32_t crc_ss : 12;/* [11:0] */
__IO uint32_t crc_sn : 12;/* [23:12] */
__IO uint32_t reserved1 : 7; /* [30:24] */
__IO uint32_t crc_strt : 1; /* [31] */
} crc_ctrl_bit;
};
/**
* @brief flash crc_chkr register, offset:0xF8
* @brief flash crc_chkr register, offset:0xF8
*/
union
{
__IO uint32_t crc_chkr;
struct
{
__IO uint32_t crc_chkr : 32;/* [31:0] */
__IO uint32_t crc_chkr : 32;/* [31:0] */
} crc_chkr_bit;
};
} flash_type;
} flash_type;
/**
* @brief user system data
@@ -549,11 +549,11 @@ typedef struct
__IO uint16_t eopb0;
__IO uint16_t reserved;
__IO uint16_t data2;
__IO uint16_t data3;
__IO uint16_t data3;
__IO uint16_t data4;
__IO uint16_t data5;
__IO uint16_t data5;
__IO uint16_t data6;
__IO uint16_t data7;
__IO uint16_t data7;
__IO uint16_t ext_flash_key[8];
} usd_type;

10
libraries/drivers/inc/at32f413_gpio.h
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f413_gpio.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 gpio header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -47,7 +47,7 @@ extern "C" {
/** @defgroup GPIO_pins_number_definition
* @{
*/
#define GPIO_PINS_0 0x0001 /*!< gpio pins number 0 */
#define GPIO_PINS_1 0x0002 /*!< gpio pins number 1 */
#define GPIO_PINS_2 0x0004 /*!< gpio pins number 2 */
@@ -224,7 +224,7 @@ typedef enum
{
GPIO_DRIVE_STRENGTH_STRONGER = 0x01, /*!< stronger sourcing/sinking strength */
GPIO_DRIVE_STRENGTH_MODERATE = 0x02, /*!< moderate sourcing/sinking strength */
GPIO_DRIVE_STRENGTH_MAXIMUM = 0x03 /*!< maximum sourcing/sinking strength */
GPIO_DRIVE_STRENGTH_MAXIMUM = 0x03 /*!< maximum sourcing/sinking strength */
} gpio_drive_type;
/**
@@ -654,7 +654,7 @@ typedef struct
{
__IO uint32_t tmr9_gmux : 4; /* [3:0] */
__IO uint32_t tmr10_gmux : 4; /* [7:4] */
__IO uint32_t tmr11_gmux : 4; /* [11:8] */
__IO uint32_t tmr11_gmux : 4; /* [11:8] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} remap3_bit;
};

42
libraries/drivers/inc/at32f413_i2c.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_i2c.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 i2c header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -44,11 +44,11 @@ extern "C" {
* @{
*/
/** @defgroup I2C_sts1_flags_definition
/** @defgroup I2C_sts1_flags_definition
* @brief i2c sts1 flag
* @{
*/
#define I2C_STARTF_FLAG ((uint32_t)0x00000001) /*!< i2c start condition generation complete flag */
#define I2C_ADDR7F_FLAG ((uint32_t)0x00000002) /*!< i2c 0~7 bit address match flag */
#define I2C_TDC_FLAG ((uint32_t)0x00000004) /*!< i2c transmit data complete flag */
@@ -68,11 +68,11 @@ extern "C" {
* @}
*/
/** @defgroup I2C_sts2_flags_definition
/** @defgroup I2C_sts2_flags_definition
* @brief i2c sts2 flag
* @{
*/
#define I2C_TRMODE_FLAG ((uint32_t)0x10010000) /*!< i2c transmission mode */
#define I2C_BUSYF_FLAG ((uint32_t)0x10020000) /*!< i2c bus busy flag transmission mode */
#define I2C_DIRF_FLAG ((uint32_t)0x10040000) /*!< i2c transmission direction flag */
@@ -85,12 +85,12 @@ extern "C" {
* @}
*/
/** @defgroup I2C_interrupts_definition
* @brief i2c interrupt
/** @defgroup I2C_interrupts_definition
* @brief i2c interrupt
* @{
*/
#define I2C_DATA_INT ((uint16_t)0x0400) /*!< i2c data transmission interrupt */
#define I2C_DATA_INT ((uint16_t)0x0400) /*!< i2c data transmission interrupt */
#define I2C_EVT_INT ((uint16_t)0x0200) /*!< i2c event interrupt */
#define I2C_ERR_INT ((uint16_t)0x0100) /*!< i2c error interrupt */
@@ -101,13 +101,13 @@ extern "C" {
/** @defgroup I2C_exported_types
* @{
*/
/**
* @brief i2c master receiving mode acknowledge control
*/
typedef enum
{
I2C_MASTER_ACK_CURRENT = 0x00, /*!< acken bit acts on the current byte */
I2C_MASTER_ACK_CURRENT = 0x00, /*!< acken bit acts on the current byte */
I2C_MASTER_ACK_NEXT = 0x01 /*!< acken bit acts on the next byte */
} i2c_master_ack_type;
@@ -116,7 +116,7 @@ typedef enum
*/
typedef enum
{
I2C_PEC_POSITION_CURRENT = 0x00, /*!< the current byte is pec */
I2C_PEC_POSITION_CURRENT = 0x00, /*!< the current byte is pec */
I2C_PEC_POSITION_NEXT = 0x01 /*!< the next byte is pec */
} i2c_pec_position_type;
@@ -126,7 +126,7 @@ typedef enum
*/
typedef enum
{
I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
I2C_SMBUS_ALERT_LOW = 0x01 /*!< smbus alert pin set low */
} i2c_smbus_alert_set_type;
@@ -173,7 +173,7 @@ typedef enum
typedef struct
{
/**
* @brief i2c ctrl1 register, offset:0x00
* @brief i2c ctrl1 register, offset:0x00
*/
union
{
@@ -201,7 +201,7 @@ typedef struct
};
/**
* @brief i2c ctrl2 register, offset:0x04
* @brief i2c ctrl2 register, offset:0x04
*/
union
{

14
libraries/drivers/inc/at32f413_misc.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_misc.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 misc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,

46
libraries/drivers/inc/at32f413_pwc.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_pwc.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 pwc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,8 +31,8 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f413.h"
@@ -44,8 +44,8 @@ extern "C" {
* @{
*/
/** @defgroup PWC_flags_definition
* @brief pwc flag
/** @defgroup PWC_flags_definition
* @brief pwc flag
* @{
*/
@@ -65,9 +65,9 @@ extern "C" {
/** @defgroup PWC_exported_types
* @{
*/
/**
* @brief pwc pvm voltage type
* @brief pwc pvm voltage type
*/
typedef enum
{
@@ -81,7 +81,7 @@ typedef enum
} pwc_pvm_voltage_type;
/**
* @brief pwc sleep enter type
* @brief pwc sleep enter type
*/
typedef enum
{
@@ -90,7 +90,7 @@ typedef enum
} pwc_sleep_enter_type;
/**
* @brief pwc deep sleep enter type
* @brief pwc deep sleep enter type
*/
typedef enum
{
@@ -99,7 +99,7 @@ typedef enum
} pwc_deep_sleep_enter_type;
/**
* @brief pwc regulator type
* @brief pwc regulator type
*/
typedef enum
{
@@ -128,11 +128,11 @@ typedef struct
__IO uint32_t pvmsel : 3; /* [7:5] */
__IO uint32_t bpwen : 1; /* [8] */
__IO uint32_t reserved1 : 23;/* [31:9] */
} ctrl_bit;
} ctrl_bit;
};
/**
* @brief pwc ctrlsts register, offset:0x04
* @brief pwc ctrlsts register, offset:0x04
*/
union
{
@@ -147,14 +147,14 @@ typedef struct
__IO uint32_t reserved2 : 23;/* [31:9] */
} ctrlsts_bit;
};
} pwc_type;
} pwc_type;
/**
* @}
*/
#define PWC ((pwc_type *) PWC_BASE)
#define PWC ((pwc_type *) PWC_BASE)
/** @defgroup PWC_exported_functions
* @{

104
libraries/drivers/inc/at32f413_rtc.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_rtc.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 rtc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,8 +31,8 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f413.h"
@@ -44,24 +44,24 @@ extern "C" {
* @{
*/
/** @defgroup RTC_interrupts_definition
* @brief rtc interrupt
/** @defgroup RTC_interrupts_definition
* @brief rtc interrupt
* @{
*/
#define RTC_TS_INT ((uint16_t)0x0001) /*!< rtc time second interrupt */
#define RTC_TA_INT ((uint16_t)0x0002) /*!< rtc time alarm interrupt */
#define RTC_OVF_INT ((uint16_t)0x0004) /*!< rtc overflow interrupt */
#define RTC_OVF_INT ((uint16_t)0x0004) /*!< rtc overflow interrupt */
/**
* @}
*/
/** @defgroup RTC_flags_definition
* @brief rtc flag
/** @defgroup RTC_flags_definition
* @brief rtc flag
* @{
*/
#define RTC_TS_FLAG ((uint16_t)0x0001) /*!< rtc time second flag */
#define RTC_TA_FLAG ((uint16_t)0x0002) /*!< rtc time alarm flag */
#define RTC_OVF_FLAG ((uint16_t)0x0004) /*!< rtc overflow flag */
@@ -71,19 +71,19 @@ extern "C" {
/**
* @}
*/
/** @defgroup RTC_exported_types
* @{
*/
/**
* @brief type define rtc register all
*/
typedef struct
{
{
/**
* @brief rtc ctrlh register, offset:0x00
* @brief rtc ctrlh register, offset:0x00
*/
union
{
@@ -96,9 +96,9 @@ typedef struct
__IO uint32_t reserved1 : 29;/* [31:3] */
} ctrlh_bit;
};
/**
* @brief rtc ctrll register, offset:0x04
* @brief rtc ctrll register, offset:0x04
*/
union
{
@@ -113,10 +113,10 @@ typedef struct
__IO uint32_t cfgf : 1; /* [5] */
__IO uint32_t reserved1 : 26;/* [31:6] */
} ctrll_bit;
};
};
/**
* @brief rtc divh register, offset:0x08
* @brief rtc divh register, offset:0x08
*/
union
{
@@ -126,10 +126,10 @@ typedef struct
__IO uint32_t div : 4; /* [3:0] */
__IO uint32_t reserved1 : 28;/* [31:4] */
} divh_bit;
};
};
/**
* @brief rtc divl register, offset:0x0C
* @brief rtc divl register, offset:0x0C
*/
union
{
@@ -139,10 +139,10 @@ typedef struct
__IO uint32_t div : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} divl_bit;
};
};
/**
* @brief rtc divcnth register, offset:0x10
* @brief rtc divcnth register, offset:0x10
*/
union
{
@@ -152,10 +152,10 @@ typedef struct
__IO uint32_t divcnt : 4; /* [3:0] */
__IO uint32_t reserved1 : 28;/* [31:15] */
} divcnth_bit;
};
};
/**
* @brief rtc divcntl register, offset:0x14
* @brief rtc divcntl register, offset:0x14
*/
union
{
@@ -165,10 +165,10 @@ typedef struct
__IO uint32_t divcnt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} divcntl_bit;
};
};
/**
* @brief rtc cnth register, offset:0x18
* @brief rtc cnth register, offset:0x18
*/
union
{
@@ -178,10 +178,10 @@ typedef struct
__IO uint32_t cnt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} cnth_bit;
};
};
/**
* @brief rtc cntl register, offset:0x1C
* @brief rtc cntl register, offset:0x1C
*/
union
{
@@ -191,10 +191,10 @@ typedef struct
__IO uint32_t cnt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} cntl_bit;
};
};
/**
* @brief rtc tah register, offset:0x20
* @brief rtc tah register, offset:0x20
*/
union
{
@@ -204,10 +204,10 @@ typedef struct
__IO uint32_t ta : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} tah_bit;
};
};
/**
* @brief rtc tal register, offset:0x24
* @brief rtc tal register, offset:0x24
*/
union
{
@@ -217,15 +217,15 @@ typedef struct
__IO uint32_t ta : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} tal_bit;
};
} rtc_type;
};
} rtc_type;
/**
* @}
*/
#define RTC ((rtc_type *) RTC_BASE)
#define RTC ((rtc_type *) RTC_BASE)
/** @defgroup RTC_exported_functions
* @{

42
libraries/drivers/inc/at32f413_sdio.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_sdio.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 sdio header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -45,10 +45,10 @@ extern "C" {
*/
/** @defgroup SDIO_interrupts_definition
* @brief sdio interrupt
* @brief sdio interrupt
* @{
*/
#define SDIO_CMDFAIL_INT ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
#define SDIO_DTFAIL_INT ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
#define SDIO_CMDTIMEOUT_INT ((uint32_t)0x00000004) /*!< command response timerout interrupt */
@@ -76,9 +76,9 @@ extern "C" {
/**
* @}
*/
/** @defgroup SDIO_flags_definition
* @brief sdio flag
/** @defgroup SDIO_flags_definition
* @brief sdio flag
* @{
*/
@@ -109,11 +109,11 @@ extern "C" {
/**
* @}
*/
/** @defgroup SDIO_exported_types
* @{
*/
/**
* @brief sdio power state
*/
@@ -133,7 +133,7 @@ typedef enum
} sdio_edge_phase_type;
/**
* @brief sdio bus width
* @brief sdio bus width
*/
typedef enum
{
@@ -143,7 +143,7 @@ typedef enum
} sdio_bus_width_type;
/**
* @brief sdio response type
* @brief sdio response type
*/
typedef enum
{
@@ -153,7 +153,7 @@ typedef enum
} sdio_reponse_type;
/**
* @brief sdio wait type
* @brief sdio wait type
*/
typedef enum
{
@@ -223,7 +223,7 @@ typedef enum
} sdio_read_wait_mode_type;
/**
* @brief sdio command structure
* @brief sdio command structure
*/
typedef struct
{
@@ -234,7 +234,7 @@ typedef struct
} sdio_command_struct_type;
/**
* @brief sdio data structure
* @brief sdio data structure
*/
typedef struct
{
@@ -251,7 +251,7 @@ typedef struct
typedef struct
{
/**
* @brief sdio pwrctrl register, offset:0x00
* @brief sdio pwrctrl register, offset:0x00
*/
union
{
@@ -264,7 +264,7 @@ typedef struct
};
/**
* @brief sdio clkctrl register, offset:0x04
* @brief sdio clkctrl register, offset:0x04
*/
union
{

118
libraries/drivers/inc/at32f413_spi.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_spi.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 spi header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,8 +31,8 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f413.h"
@@ -43,13 +43,13 @@ extern "C" {
/** @addtogroup SPI
* @{
*/
/**
* @defgroup SPI_I2S_flags_definition
* @brief spi i2s flag
* @{
* @brief spi i2s flag
* @{
*/
#define SPI_I2S_RDBF_FLAG 0x0001 /*!< spi or i2s receive data buffer full flag */
#define SPI_I2S_TDBE_FLAG 0x0002 /*!< spi or i2s transmit data buffer empty flag */
#define I2S_ACS_FLAG 0x0004 /*!< i2s audio channel state flag */
@@ -64,9 +64,9 @@ extern "C" {
*/
/**
* @defgroup SPI_I2S_interrupts_definition
* @brief spi i2s interrupt
* @{
* @defgroup SPI_I2S_interrupts_definition
* @brief spi i2s interrupt
* @{
*/
#define SPI_I2S_ERROR_INT 0x0020 /*!< error interrupt */
@@ -80,9 +80,9 @@ extern "C" {
/** @defgroup SPI_exported_types
* @{
*/
/**
* @brief spi frame bit num type
* @brief spi frame bit num type
*/
typedef enum
{
@@ -91,7 +91,7 @@ typedef enum
} spi_frame_bit_num_type;
/**
* @brief spi master/slave mode type
* @brief spi master/slave mode type
*/
typedef enum
{
@@ -100,7 +100,7 @@ typedef enum
} spi_master_slave_mode_type;
/**
* @brief spi clock polarity (clkpol) type
* @brief spi clock polarity (clkpol) type
*/
typedef enum
{
@@ -109,7 +109,7 @@ typedef enum
} spi_clock_polarity_type;
/**
* @brief spi clock phase (clkpha) type
* @brief spi clock phase (clkpha) type
*/
typedef enum
{
@@ -118,7 +118,7 @@ typedef enum
} spi_clock_phase_type;
/**
* @brief spi cs mode type
* @brief spi cs mode type
*/
typedef enum
{
@@ -127,7 +127,7 @@ typedef enum
} spi_cs_mode_type;
/**
* @brief spi master clock frequency division type
* @brief spi master clock frequency division type
*/
typedef enum
{
@@ -144,7 +144,7 @@ typedef enum
} spi_mclk_freq_div_type;
/**
* @brief spi transmit first bit (lsb/msb) type
* @brief spi transmit first bit (lsb/msb) type
*/
typedef enum
{
@@ -153,7 +153,7 @@ typedef enum
} spi_first_bit_type;
/**
* @brief spi transmission mode type
* @brief spi transmission mode type
*/
typedef enum
{
@@ -164,7 +164,7 @@ typedef enum
} spi_transmission_mode_type;
/**
* @brief spi crc direction type
* @brief spi crc direction type
*/
typedef enum
{
@@ -173,7 +173,7 @@ typedef enum
} spi_crc_direction_type;
/**
* @brief spi single line bidirectional direction type
* @brief spi single line bidirectional direction type
*/
typedef enum
{
@@ -182,7 +182,7 @@ typedef enum
} spi_half_duplex_direction_type;
/**
* @brief spi software cs internal level type
* @brief spi software cs internal level type
*/
typedef enum
{
@@ -191,7 +191,7 @@ typedef enum
} spi_software_cs_level_type;
/**
* @brief i2s audio protocol type
* @brief i2s audio protocol type
*/
typedef enum
{
@@ -220,7 +220,7 @@ typedef enum
} i2s_audio_sampling_freq_type;
/**
* @brief i2s data bit num and channel bit num type
* @brief i2s data bit num and channel bit num type
*/
typedef enum
{
@@ -231,7 +231,7 @@ typedef enum
} i2s_data_channel_format_type;
/**
* @brief i2s operation mode type
* @brief i2s operation mode type
*/
typedef enum
{
@@ -242,7 +242,7 @@ typedef enum
} i2s_operation_mode_type;
/**
* @brief i2s clock polarity type
* @brief i2s clock polarity type
*/
typedef enum
{
@@ -260,7 +260,7 @@ typedef struct
spi_mclk_freq_div_type mclk_freq_division; /*!< master clock frequency division selection */
spi_first_bit_type first_bit_transmission;/*!< transmit lsb or msb selection */
spi_frame_bit_num_type frame_bit_num; /*!< frame bit num 8 or 16 bit selection */
spi_clock_polarity_type clock_polarity; /*!< clock polarity selection */
spi_clock_polarity_type clock_polarity; /*!< clock polarity selection */
spi_clock_phase_type clock_phase; /*!< clock phase selection */
spi_cs_mode_type cs_mode_selection; /*!< hardware or software cs mode selection */
} spi_init_type;
@@ -282,10 +282,10 @@ typedef struct
* @brief type define spi register all
*/
typedef struct
{
{
/**
* @brief spi ctrl1 register, offset:0x00
* @brief spi ctrl1 register, offset:0x00
*/
union
{
@@ -297,11 +297,11 @@ typedef struct
__IO uint32_t msten : 1; /* [2] */
__IO uint32_t mdiv_l : 3; /* [5:3] */
__IO uint32_t spien : 1; /* [6] */
__IO uint32_t ltf : 1; /* [7] */
__IO uint32_t ltf : 1; /* [7] */
__IO uint32_t swcsil : 1; /* [8] */
__IO uint32_t swcsen : 1; /* [9] */
__IO uint32_t ora : 1; /* [10] */
__IO uint32_t fbn : 1; /* [11] */
__IO uint32_t fbn : 1; /* [11] */
__IO uint32_t ntc : 1; /* [12] */
__IO uint32_t ccen : 1; /* [13] */
__IO uint32_t slbtd : 1; /* [14] */
@@ -309,9 +309,9 @@ typedef struct
__IO uint32_t reserved1 : 16;/* [31:16] */
} ctrl1_bit;
};
/**
* @brief spi ctrl2 register, offset:0x04
* @brief spi ctrl2 register, offset:0x04
*/
union
{
@@ -323,15 +323,15 @@ typedef struct
__IO uint32_t hwcsoe : 1; /* [2] */
__IO uint32_t reserved1 : 2; /* [4:3] */
__IO uint32_t errie : 1; /* [5] */
__IO uint32_t rdbfie : 1; /* [6] */
__IO uint32_t rdbfie : 1; /* [6] */
__IO uint32_t tdbeie : 1; /* [7] */
__IO uint32_t mdiv_h : 1; /* [8] */
__IO uint32_t reserved2 : 23;/* [31:9] */
} ctrl2_bit;
};
/**
* @brief spi sts register, offset:0x08
* @brief spi sts register, offset:0x08
*/
union
{
@@ -348,10 +348,10 @@ typedef struct
__IO uint32_t bf : 1; /* [7] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} sts_bit;
};
};
/**
* @brief spi dt register, offset:0x0C
* @brief spi dt register, offset:0x0C
*/
union
{
@@ -361,10 +361,10 @@ typedef struct
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} dt_bit;
};
};
/**
* @brief spi cpoly register, offset:0x10
* @brief spi cpoly register, offset:0x10
*/
union
{
@@ -374,10 +374,10 @@ typedef struct
__IO uint32_t cpoly : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cpoly_bit;
};
};
/**
* @brief spi rcrc register, offset:0x14
* @brief spi rcrc register, offset:0x14
*/
union
{
@@ -388,9 +388,9 @@ typedef struct
__IO uint32_t reserved1 : 16;/* [31:16] */
} rcrc_bit;
};
/**
* @brief spi tcrc register, offset:0x18
* @brief spi tcrc register, offset:0x18
*/
union
{
@@ -403,7 +403,7 @@ typedef struct
};
/**
* @brief spi i2sctrl register, offset:0x1C
* @brief spi i2sctrl register, offset:0x1C
*/
union
{
@@ -421,10 +421,10 @@ typedef struct
__IO uint32_t i2smsel : 1; /* [11] */
__IO uint32_t reserved2 : 20;/* [31:12] */
} i2sctrl_bit;
};
};
/**
* @brief spi i2sclk register, offset:0x20
* @brief spi i2sclk register, offset:0x20
*/
union
{
@@ -437,9 +437,9 @@ typedef struct
__IO uint32_t i2sdiv_h : 2; /* [11:10] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} i2sclk_bit;
};
};
} spi_type;
} spi_type;
/**
* @}

148
libraries/drivers/inc/at32f413_tmr.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_tmr.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 tmr header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,8 +31,8 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f413.h"
@@ -44,11 +44,11 @@ extern "C" {
* @{
*/
/** @defgroup TMR_flags_definition
* @brief tmr flag
/** @defgroup TMR_flags_definition
* @brief tmr flag
* @{
*/
#define TMR_OVF_FLAG ((uint32_t)0x000001) /*!< tmr flag overflow */
#define TMR_C1_FLAG ((uint32_t)0x000002) /*!< tmr flag channel 1 */
#define TMR_C2_FLAG ((uint32_t)0x000004) /*!< tmr flag channel 2 */
@@ -66,7 +66,7 @@ extern "C" {
* @}
*/
/** @defgroup TMR_interrupt_select_type_definition
/** @defgroup TMR_interrupt_select_type_definition
* @brief tmr interrupt select type
* @{
*/
@@ -89,7 +89,7 @@ extern "C" {
*/
/**
* @brief tmr clock division type
* @brief tmr clock division type
*/
typedef enum
{
@@ -99,7 +99,7 @@ typedef enum
} tmr_clock_division_type;
/**
* @brief tmr counter mode type
* @brief tmr counter mode type
*/
typedef enum
{
@@ -111,7 +111,7 @@ typedef enum
} tmr_count_mode_type;
/**
* @brief tmr primary mode select type
* @brief tmr primary mode select type
*/
typedef enum
{
@@ -126,7 +126,7 @@ typedef enum
} tmr_primary_select_type;
/**
* @brief tmr subordinate mode input select type
* @brief tmr subordinate mode input select type
*/
typedef enum
{
@@ -141,7 +141,7 @@ typedef enum
} sub_tmr_input_sel_type;
/**
* @brief tmr subordinate mode select type
* @brief tmr subordinate mode select type
*/
typedef enum
{
@@ -156,7 +156,7 @@ typedef enum
} tmr_sub_mode_select_type;
/**
* @brief tmr encoder mode type
* @brief tmr encoder mode type
*/
typedef enum
{
@@ -166,7 +166,7 @@ typedef enum
} tmr_encoder_mode_type;
/**
* @brief tmr output control mode type
* @brief tmr output control mode type
*/
typedef enum
{
@@ -219,7 +219,7 @@ typedef enum
TMR_SELECT_CHANNEL_2C = 0x03, /*!< tmr channel select channel 2 complementary */
TMR_SELECT_CHANNEL_3 = 0x04, /*!< tmr channel select channel 3 */
TMR_SELECT_CHANNEL_3C = 0x05, /*!< tmr channel select channel 3 complementary */
TMR_SELECT_CHANNEL_4 = 0x06 /*!< tmr channel select channel 4 */
TMR_SELECT_CHANNEL_4 = 0x06 /*!< tmr channel select channel 4 */
} tmr_channel_select_type;
/**
@@ -242,7 +242,7 @@ typedef enum
} tmr_input_direction_mapped_type;
/**
* @brief tmr input divider type
* @brief tmr input divider type
*/
typedef enum
{
@@ -253,7 +253,7 @@ typedef enum
} tmr_channel_input_divider_type;
/**
* @brief tmr dma request source select type
* @brief tmr dma request source select type
*/
typedef enum
{
@@ -262,7 +262,7 @@ typedef enum
} tmr_dma_request_source_type;
/**
* @brief tmr dma request type
* @brief tmr dma request type
*/
typedef enum
{
@@ -276,7 +276,7 @@ typedef enum
} tmr_dma_request_type;
/**
* @brief tmr event triggered by software type
* @brief tmr event triggered by software type
*/
typedef enum
{
@@ -291,7 +291,7 @@ typedef enum
}tmr_event_trigger_type;
/**
* @brief tmr polarity active type
* @brief tmr polarity active type
*/
typedef enum
{
@@ -301,7 +301,7 @@ typedef enum
}tmr_polarity_active_type;
/**
* @brief tmr external signal divider type
* @brief tmr external signal divider type
*/
typedef enum
{
@@ -312,7 +312,7 @@ typedef enum
}tmr_external_signal_divider_type;
/**
* @brief tmr external signal polarity type
* @brief tmr external signal polarity type
*/
typedef enum
{
@@ -321,7 +321,7 @@ typedef enum
}tmr_external_signal_polarity_type;
/**
* @brief tmr dma transfer length type
* @brief tmr dma transfer length type
*/
typedef enum
{
@@ -346,7 +346,7 @@ typedef enum
}tmr_dma_transfer_length_type;
/**
* @brief tmr dma base address type
* @brief tmr dma base address type
*/
typedef enum
{
@@ -372,7 +372,7 @@ typedef enum
}tmr_dma_address_type;
/**
* @brief tmr brk polarity type
* @brief tmr brk polarity type
*/
typedef enum
{
@@ -381,32 +381,32 @@ typedef enum
}tmr_brk_polarity_type;
/**
* @brief tmr write protect level type
* @brief tmr write protect level type
*/
typedef enum
{
TMR_WP_OFF = 0x00, /*!< tmr write protect off */
TMR_WP_OFF = 0x00, /*!< tmr write protect off */
TMR_WP_LEVEL_3 = 0x01, /*!< tmr write protect level 3 */
TMR_WP_LEVEL_2 = 0x02, /*!< tmr write protect level 2 */
TMR_WP_LEVEL_1 = 0x03 /*!< tmr write protect level 1 */
}tmr_wp_level_type;
/**
* @brief tmr output config type
/**
* @brief tmr output config type
*/
typedef struct
{
tmr_output_control_mode_type oc_mode; /*!< output channel mode */
confirm_state oc_idle_state; /*!< output channel idle state */
confirm_state occ_idle_state; /*!< output channel complementary idle state */
tmr_output_polarity_type oc_polarity; /*!< output channel polarity */
tmr_output_polarity_type occ_polarity; /*!< output channel complementary polarity */
confirm_state oc_output_state; /*!< output channel enable */
confirm_state occ_output_state; /*!< output channel complementary enable */
confirm_state occ_idle_state; /*!< output channel complementary idle state */
tmr_output_polarity_type oc_polarity; /*!< output channel polarity */
tmr_output_polarity_type occ_polarity; /*!< output channel complementary polarity */
confirm_state oc_output_state; /*!< output channel enable */
confirm_state occ_output_state; /*!< output channel complementary enable */
} tmr_output_config_type;
/**
* @brief tmr input capture config type
/**
* @brief tmr input capture config type
*/
typedef struct
{
@@ -416,7 +416,7 @@ typedef struct
uint8_t input_filter_value; /*!< tmr channel filter value */
} tmr_input_config_type;
/**
/**
* @brief tmr brkdt config type
*/
typedef struct
@@ -424,7 +424,7 @@ typedef struct
uint8_t deadtime; /*!< dead-time generator setup */
tmr_brk_polarity_type brk_polarity; /*!< tmr brake polarity */
tmr_wp_level_type wp_level; /*!< write protect configuration */
confirm_state auto_output_enable; /*!< automatic output enable */
confirm_state auto_output_enable; /*!< automatic output enable */
confirm_state fcsoen_state; /*!< frozen channel status when output enable */
confirm_state fcsodis_state; /*!< frozen channel status when output disable */
confirm_state brk_enable; /*!< tmr brk enale */
@@ -436,13 +436,13 @@ typedef struct
typedef struct
{
/**
* @brief tmr ctrl1 register, offset:0x00
* @brief tmr ctrl1 register, offset:0x00
*/
union
{
__IO uint32_t ctrl1;
struct
{
{
__IO uint32_t tmren : 1; /* [0] */
__IO uint32_t ovfen : 1; /* [1] */
__IO uint32_t ovfs : 1; /* [2] */
@@ -456,7 +456,7 @@ typedef struct
};
/**
* @brief tmr ctrl2 register, offset:0x04
* @brief tmr ctrl2 register, offset:0x04
*/
union
{
@@ -481,7 +481,7 @@ typedef struct
};
/**
* @brief tmr smc register, offset:0x08
* @brief tmr smc register, offset:0x08
*/
union
{
@@ -501,11 +501,11 @@ typedef struct
};
/**
* @brief tmr die register, offset:0x0C
* @brief tmr die register, offset:0x0C
*/
union
{
__IO uint32_t iden;
__IO uint32_t iden;
struct
{
__IO uint32_t ovfien : 1; /* [0] */
@@ -528,7 +528,7 @@ typedef struct
};
/**
* @brief tmr ists register, offset:0x10
* @brief tmr ists register, offset:0x10
*/
union
{
@@ -553,7 +553,7 @@ typedef struct
};
/**
* @brief tmr eveg register, offset:0x14
* @brief tmr eveg register, offset:0x14
*/
union
{
@@ -573,12 +573,12 @@ typedef struct
};
/**
* @brief tmr ccm1 register, offset:0x18
* @brief tmr ccm1 register, offset:0x18
*/
union
{
__IO uint32_t cm1;
/**
* @brief channel mode
*/
@@ -591,12 +591,12 @@ typedef struct
__IO uint32_t c1osen : 1; /* [7] */
__IO uint32_t c2c : 2; /* [9:8] */
__IO uint32_t c2oien : 1; /* [10] */
__IO uint32_t c2oben : 1; /* [11] */
__IO uint32_t c2octrl : 3; /* [14:12] */
__IO uint32_t c2oben : 1; /* [11] */
__IO uint32_t c2octrl : 3; /* [14:12] */
__IO uint32_t c2osen : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cm1_output_bit;
/**
* @brief input capture mode
*/
@@ -613,12 +613,12 @@ typedef struct
};
/**
* @brief tmr ccm2 register, offset:0x1C
* @brief tmr ccm2 register, offset:0x1C
*/
union
{
__IO uint32_t cm2;
/**
* @brief channel mode
*/
@@ -631,8 +631,8 @@ typedef struct
__IO uint32_t c3osen : 1; /* [7] */
__IO uint32_t c4c : 2; /* [9:8] */
__IO uint32_t c4oien : 1; /* [10] */
__IO uint32_t c4oben : 1; /* [11] */
__IO uint32_t c4octrl : 3; /* [14:12] */
__IO uint32_t c4oben : 1; /* [11] */
__IO uint32_t c4octrl : 3; /* [14:12] */
__IO uint32_t c4osen : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cm2_output_bit;
@@ -653,7 +653,7 @@ typedef struct
};
/**
* @brief tmr cce register, offset:0x20
* @brief tmr cce register, offset:0x20
*/
union
{
@@ -679,7 +679,7 @@ typedef struct
};
/**
* @brief tmr cnt register, offset:0x24
* @brief tmr cnt register, offset:0x24
*/
union
{
@@ -691,7 +691,7 @@ typedef struct
};
/**
* @brief tmr div, offset:0x28
* @brief tmr div, offset:0x28
*/
union
{
@@ -704,7 +704,7 @@ typedef struct
};
/**
* @brief tmr pr register, offset:0x2C
* @brief tmr pr register, offset:0x2C
*/
union
{
@@ -716,7 +716,7 @@ typedef struct
};
/**
* @brief tmr rpr register, offset:0x30
* @brief tmr rpr register, offset:0x30
*/
union
{
@@ -729,7 +729,7 @@ typedef struct
};
/**
* @brief tmr c1dt register, offset:0x34
* @brief tmr c1dt register, offset:0x34
*/
union
{
@@ -741,7 +741,7 @@ typedef struct
};
/**
* @brief tmr c2dt register, offset:0x38
* @brief tmr c2dt register, offset:0x38
*/
union
{
@@ -753,7 +753,7 @@ typedef struct
};
/**
* @brief tmr c3dt register, offset:0x3C
* @brief tmr c3dt register, offset:0x3C
*/
union
{
@@ -765,7 +765,7 @@ typedef struct
};
/**
* @brief tmr c4dt register, offset:0x40
* @brief tmr c4dt register, offset:0x40
*/
union
{
@@ -777,7 +777,7 @@ typedef struct
};
/**
* @brief tmr brk register, offset:0x44
* @brief tmr brk register, offset:0x44
*/
union
{
@@ -796,7 +796,7 @@ typedef struct
} brk_bit;
};
/**
* @brief tmr dmactrl register, offset:0x48
* @brief tmr dmactrl register, offset:0x48
*/
union
{
@@ -811,7 +811,7 @@ typedef struct
};
/**
* @brief tmr dmadt register, offset:0x4C
* @brief tmr dmadt register, offset:0x4C
*/
union
{
@@ -821,7 +821,7 @@ typedef struct
__IO uint32_t dmadt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} dmadt_bit;
};
};
} tmr_type;

44
libraries/drivers/inc/at32f413_usart.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_usart.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 usart header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,10 +31,10 @@
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f413.h"
#include "at32f413.h"
/** @addtogroup AT32F413_periph_driver
* @{
@@ -45,10 +45,10 @@ extern "C" {
*/
/** @defgroup USART_flags_definition
* @brief usart flag
* @brief usart flag
* @{
*/
#define USART_PERR_FLAG ((uint32_t)0x00000001) /*!< usart parity error flag */
#define USART_FERR_FLAG ((uint32_t)0x00000002) /*!< usart framing error flag */
#define USART_NERR_FLAG ((uint32_t)0x00000004) /*!< usart noise error flag */
@@ -64,7 +64,7 @@ extern "C" {
* @}
*/
/** @defgroup USART_interrupts_definition
/** @defgroup USART_interrupts_definition
* @brief usart interrupt
* @{
*/
@@ -81,11 +81,11 @@ extern "C" {
/**
* @}
*/
/** @defgroup USART_exported_types
* @{
*/
/**
* @brief usart parity selection type
*/
@@ -179,7 +179,7 @@ typedef struct
{
/**
* @brief usart sts register, offset:0x00
*/
*/
union
{
__IO uint32_t sts;
@@ -198,10 +198,10 @@ typedef struct
__IO uint32_t reserved1 : 22;/* [31:10] */
} sts_bit;
};
/**
* @brief usart dt register, offset:0x04
*/
*/
union
{
__IO uint32_t dt;
@@ -211,7 +211,7 @@ typedef struct
__IO uint32_t reserved1 : 23;/* [31:9] */
} dt_bit;
};
/**
* @brief usart baudr register, offset:0x08
*/
@@ -224,7 +224,7 @@ typedef struct
__IO uint32_t reserved1 : 16;/* [31:16] */
} baudr_bit;
};
/**
* @brief usart ctrl1 register, offset:0x0C
*/
@@ -273,7 +273,7 @@ typedef struct
__IO uint32_t reserved3 : 17;/* [31:15] */
} ctrl2_bit;
};
/**
* @brief usart ctrl3 register, offset:0x14
*/
@@ -285,7 +285,7 @@ typedef struct
__IO uint32_t errien : 1; /* [0] */
__IO uint32_t irdaen : 1; /* [1] */
__IO uint32_t irdalp : 1; /* [2] */
__IO uint32_t slben : 1; /* [3] */
__IO uint32_t slben : 1; /* [3] */
__IO uint32_t scnacken : 1; /* [4] */
__IO uint32_t scmen : 1; /* [5] */
__IO uint32_t dmaren : 1; /* [6] */
@@ -309,7 +309,7 @@ typedef struct
__IO uint32_t scgt : 8; /* [15:8] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} gdiv_bit;
};
};
} usart_type;
/**

81
libraries/drivers/inc/at32f413_usb.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_usb.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 usb header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,7 +31,7 @@
/** @addtogroup USB
* @{
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F413_USB_H
#define __AT32F413_USB_H
@@ -45,12 +45,12 @@ extern "C" {
#include "at32f413.h"
/** @defgroup USB_interrupts_definition
/** @defgroup USB_interrupts_definition
* @brief usb interrupt mask
* @{
*/
#define USB_LSOF_INT ((uint32_t)0x00000100) /*!< usb lost sof interrupt */
#define USB_SOF_INT ((uint32_t)0x00000200) /*!< usb sof interrupt */
#define USB_RST_INT ((uint32_t)0x00000400) /*!< usb reset interrupt */
@@ -64,7 +64,7 @@ extern "C" {
* @}
*/
/** @defgroup USB_interrupt_flags_definition
/** @defgroup USB_interrupt_flags_definition
* @brief usb interrupt flag
* @{
*/
@@ -84,7 +84,7 @@ extern "C" {
* @}
*/
/** @defgroup USB_endpoint_register_bit_definition
/** @defgroup USB_endpoint_register_bit_definition
* @brief usb endpoint register bit define
* @{
*/
@@ -107,12 +107,12 @@ extern "C" {
/**
* @}
*/
/** @defgroup USB_endpoint_tx_and_rx_status_definition
/** @defgroup USB_endpoint_tx_and_rx_status_definition
* @brief usb endpoint tx and rx status
* @{
*/
#define USB_TX_DISABLE ((uint32_t)0x00000000) /*!< usb tx status disable */
#define USB_TX_STALL ((uint32_t)0x00000010) /*!< usb tx status stall */
#define USB_TX_NAK ((uint32_t)0x00000020) /*!< usb tx status nak */
@@ -132,9 +132,9 @@ extern "C" {
/**
* @}
*/
/** @defgroup USB_device_endpoint_register_type_definition
* @brief usb device endpoint register type define
* @brief usb device endpoint register type define
* @{
*/
@@ -146,12 +146,12 @@ extern "C" {
/**
* @}
*/
/** @defgroup USB_buffer_table_default_offset_address_definition
/** @defgroup USB_buffer_table_default_offset_address_definition
* @brief usb buffer table default offset address
* @{
*/
#define USB_BUFFER_TABLE_ADDRESS 0x0000 /*!< usb buffer table address */
/**
@@ -159,7 +159,7 @@ extern "C" {
*/
/** @defgroup USB_packet_buffer_start_address_definition
* @brief usb packet buffer start address
* @brief usb packet buffer start address
* @{
*/
@@ -173,7 +173,7 @@ extern "C" {
/** @defgroup USB_exported_enum_types
* @{
*/
/**
* @brief usb endpoint number define
*/
@@ -295,7 +295,7 @@ typedef enum
#define USB_DBUF1_GET_LEN(eptn) USB_GET_RX_LEN(eptn)
/**
* @brief set usb length of rx buffer
* @brief set usb length of rx buffer
* @param reg: usb rx length register
* @param len: rx max length
* @param blks: number of blocks
@@ -493,16 +493,16 @@ typedef enum
/** @defgroup USB_exported_types
* @{
*/
/**
* @brief usb endpoint infomation structure definition
/**
* @brief usb endpoint infomation structure definition
*/
typedef struct
{
uint8_t eptn; /*!< endpoint register number (0~7) */
uint8_t ept_address; /*!< endpoint address */
uint8_t inout; /*!< endpoint dir DATA_TRANS_IN or DATA_TRANS_OUT */
uint8_t trans_type; /*!< endpoint type:
uint8_t trans_type; /*!< endpoint type:
EPT_CONTROL_TYPE, EPT_BULK_TYPE, EPT_INT_TYPE, EPT_ISO_TYPE*/
uint16_t tx_addr; /*!< endpoint tx buffer offset address */
uint16_t rx_addr; /*!< endpoint rx buffer offset address */
@@ -510,23 +510,24 @@ typedef struct
uint8_t is_double_buffer; /*!< endpoint double buffer flag */
uint8_t stall; /*!< endpoint is stall state */
uint16_t status; /*!< endpoint status */
/* transmission buffer and count */
uint16_t total_len; /*!< endpoint transmission total length */
uint16_t trans_len; /*!< endpoint transmission length*/
uint8_t *trans_buf; /*!< endpoint transmission buffer */
uint16_t last_len; /*!< last transfer length */
uint16_t rem0_len; /*!< rem transfer length */
uint16_t ept0_slen; /*!< endpoint 0 transfer sum length */
}usb_ept_info;
/**
* @brief type define usb register all
*/
typedef struct
{
/**
* @brief usb endpoint register, offset:0x00
* @brief usb endpoint register, offset:0x00
*/
union
{
@@ -546,11 +547,11 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} ept_bit[8];
};
__IO uint32_t reserved1[8];
/**
* @brief usb control register, offset:0x40
* @brief usb control register, offset:0x40
*/
union
{
@@ -574,7 +575,7 @@ typedef struct
__IO uint32_t reserved2 : 16; /* [31:16] */
} ctrl_bit;
};
/**
* @brief usb interrupt status register, offset:0x44
*/
@@ -597,7 +598,7 @@ typedef struct
__IO uint32_t reserved2 : 16; /* [31:16] */
} intsts_bit;
};
/**
* @brief usb frame number register, offset:0x48
*/
@@ -614,7 +615,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} sofrnum_bit;
};
/**
* @brief usb device address register, offset:0x4c
*/
@@ -628,7 +629,7 @@ typedef struct
__IO uint32_t reserved1 : 24; /* [31:8] */
} devaddr_bit;
};
/**
* @brief usb buffer address register, offset:0x50
*/
@@ -655,7 +656,7 @@ typedef struct
__IO uint32_t reserved1 : 31; /* [31:1] */
} cfg_bit;
};
} usbd_type;
/**

80
libraries/drivers/inc/at32f413_wdt.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_wdt.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 wdt header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,8 +31,8 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f413.h"
@@ -45,14 +45,14 @@ extern "C" {
*/
/** @defgroup WDT_flags_definition
/** @defgroup WDT_flags_definition
* @brief wdt flag
* @{
*/
#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
/**
* @}
*/
@@ -60,12 +60,12 @@ extern "C" {
/** @defgroup WDT_exported_types
* @{
*/
/**
* @brief wdt division value type
*/
typedef enum
{
/**
* @brief wdt division value type
*/
typedef enum
{
WDT_CLK_DIV_4 = 0x00, /*!< wdt clock divider value is 4 */
WDT_CLK_DIV_8 = 0x01, /*!< wdt clock divider value is 8 */
WDT_CLK_DIV_16 = 0x02, /*!< wdt clock divider value is 16 */
@@ -73,15 +73,15 @@ typedef enum
WDT_CLK_DIV_64 = 0x04, /*!< wdt clock divider value is 64 */
WDT_CLK_DIV_128 = 0x05, /*!< wdt clock divider value is 128 */
WDT_CLK_DIV_256 = 0x06 /*!< wdt clock divider value is 256 */
} wdt_division_type;
/**
* @brief wdt cmd value type
*/
typedef enum
{
WDT_CMD_LOCK = 0x0000, /*!< disable write protection command */
WDT_CMD_UNLOCK = 0x5555, /*!< enable write protection command */
} wdt_division_type;
/**
* @brief wdt cmd value type
*/
typedef enum
{
WDT_CMD_LOCK = 0x0000, /*!< disable write protection command */
WDT_CMD_UNLOCK = 0x5555, /*!< enable write protection command */
WDT_CMD_ENABLE = 0xCCCC, /*!< enable wdt command */
WDT_CMD_RELOAD = 0xAAAA /*!< reload command */
} wdt_cmd_value_type;
@@ -90,10 +90,10 @@ typedef enum
* @brief type define wdt register all
*/
typedef struct
{
{
/**
* @brief wdt cmd register, offset:0x00
* @brief wdt cmd register, offset:0x00
*/
union
{
@@ -104,9 +104,9 @@ typedef struct
__IO uint32_t reserved1 : 16;/* [31:16] */
} cmd_bit;
};
/**
* @brief wdt div register, offset:0x04
* @brief wdt div register, offset:0x04
*/
union
{
@@ -117,9 +117,9 @@ typedef struct
__IO uint32_t reserved1 : 29;/* [31:3] */
} div_bit;
};
/**
* @brief wdt rld register, offset:0x08
* @brief wdt rld register, offset:0x08
*/
union
{
@@ -130,9 +130,9 @@ typedef struct
__IO uint32_t reserved1 : 20;/* [31:12] */
} rld_bit;
};
/**
* @brief wdt sts register, offset:0x0C
* @brief wdt sts register, offset:0x0C
*/
union
{
@@ -144,9 +144,9 @@ typedef struct
__IO uint32_t reserved1 : 30;/* [31:2] */
} sts_bit;
};
} wdt_type;
} wdt_type;
/**
* @}
*/

26
libraries/drivers/inc/at32f413_wwdt.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f413_wwdt.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f413 wwdt header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,8 +31,8 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f413.h"
@@ -43,12 +43,12 @@ extern "C" {
/** @addtogroup WWDT
* @{
*/
/** @defgroup WWDT_enable_bit_definition
/** @defgroup WWDT_enable_bit_definition
* @brief wwdt enable bit
* @{
*/
#define WWDT_EN_BIT ((uint32_t)0x00000080) /*!< wwdt enable bit */
/**
@@ -124,7 +124,7 @@ typedef struct
* @}
*/
#define WWDT ((wwdt_type *) WWDT_BASE)
#define WWDT ((wwdt_type *) WWDT_BASE)
/** @defgroup WWDT_exported_functions
* @{