mirror of
https://github.com/ArteryTek/AT32F403A_407_Firmware_Library.git
synced 2026-05-21 01:12:11 +00:00
509 lines
18 KiB
C
509 lines
18 KiB
C
/**
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**************************************************************************
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* @file at32f403a_407_xmc.c
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* @version v2.1.1
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* @date 2022-07-22
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* @brief contains all the functions for the xmc firmware library
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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#include "at32f403a_407_conf.h"
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/** @addtogroup AT32F403A_407_periph_driver
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* @{
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*/
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/** @defgroup XMC
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* @brief XMC driver modules
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* @{
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*/
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#ifdef XMC_MODULE_ENABLED
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/** @defgroup XMC_private_functions
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* @{
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*/
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/**
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* @brief xmc nor or sram registers reset
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* @param xmc_subbank
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* this parameter can be one of the following values:
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* - XMC_BANK1_NOR_SRAM1
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* - XMC_BANK1_NOR_SRAM4
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* @retval none
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*/
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void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank)
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{
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/* XMC_BANK1_NORSRAM1 */
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if(xmc_subbank == XMC_BANK1_NOR_SRAM1)
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{
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XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030DB;
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}
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/* XMC_BANK1_NORSRAM2, XMC_BANK1_NORSRAM3 or XMC_BANK1_NORSRAM4 */
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else
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{
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XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030D2;
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}
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XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1tmg = 0x0FFFFFFF;
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XMC_BANK1->tmgwr_group[xmc_subbank].bk1tmgwr = 0x0FFFFFFF;
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}
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/**
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* @brief initialize the xmc nor/sram banks according to the specified
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* parameters in the xmc_norsraminitstruct.
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* @param xmc_norsram_init_struct : pointer to a xmc_norsram_init_type
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* structure that contains the configuration information for
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* the xmc nor/sram specified banks.
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* @retval none
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*/
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void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct)
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{
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/* bank1 nor/sram control register configuration */
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XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl =
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(uint32_t)xmc_norsram_init_struct->data_addr_multiplex |
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xmc_norsram_init_struct->device |
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xmc_norsram_init_struct->bus_type |
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xmc_norsram_init_struct->burst_mode_enable |
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xmc_norsram_init_struct->asynwait_enable |
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xmc_norsram_init_struct->wait_signal_lv |
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xmc_norsram_init_struct->wrapped_mode_enable |
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xmc_norsram_init_struct->wait_signal_config |
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xmc_norsram_init_struct->write_enable |
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xmc_norsram_init_struct->wait_signal_enable |
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xmc_norsram_init_struct->write_timing_enable |
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xmc_norsram_init_struct->write_burst_syn;
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/* if nor flash device */
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if(xmc_norsram_init_struct->device == XMC_DEVICE_NOR)
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{
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XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl_bit.noren = 0x1;
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}
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}
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/**
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* @brief initialize the xmc nor/sram banks according to the specified
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* parameters in the xmc_rw_timing_struct and xmc_w_timing_struct.
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* @param xmc_rw_timing_struct : pointer to a xmc_norsram_timing_init_type
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* structure that contains the configuration information for
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* the xmc nor/sram specified banks.
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* @param xmc_w_timing_struct : pointer to a xmc_norsram_timing_init_type
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* structure that contains the configuration information for
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* the xmc nor/sram specified banks.
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* @retval none
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*/
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void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
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xmc_norsram_timing_init_type* xmc_w_timing_struct)
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{
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/* bank1 nor/sram timing register configuration */
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XMC_BANK1->ctrl_tmg_group[xmc_rw_timing_struct->subbank].bk1tmg =
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(uint32_t)xmc_rw_timing_struct->addr_setup_time |
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(xmc_rw_timing_struct->addr_hold_time << 4) |
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(xmc_rw_timing_struct->data_setup_time << 8) |
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(xmc_rw_timing_struct->bus_latency_time <<16) |
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(xmc_rw_timing_struct->clk_psc << 20) |
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(xmc_rw_timing_struct->data_latency_time << 24) |
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xmc_rw_timing_struct->mode;
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/* bank1 nor/sram timing register for write configuration, if extended mode is used */
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if(xmc_rw_timing_struct->write_timing_enable == XMC_WRITE_TIMING_ENABLE)
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{
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XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr =
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(uint32_t)xmc_w_timing_struct->addr_setup_time |
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(xmc_w_timing_struct->addr_hold_time << 4) |
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(xmc_w_timing_struct->data_setup_time << 8) |
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(xmc_w_timing_struct->bus_latency_time << 16) |
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(xmc_w_timing_struct->clk_psc << 20) |
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(xmc_w_timing_struct->data_latency_time << 24) |
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xmc_w_timing_struct->mode;
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}
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else
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{
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XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr = 0x0FFFFFFF;
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}
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}
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/**
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* @brief fill each xmc_nor_sram_init_struct member with its default value.
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* @param xmc_nor_sram_init_struct: pointer to a xmc_norsram_init_type
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* structure which will be initialized.
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* @retval none
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*/
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void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct)
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{
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/* reset nor/sram init structure parameters values */
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xmc_nor_sram_init_struct->subbank = XMC_BANK1_NOR_SRAM1;
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xmc_nor_sram_init_struct->data_addr_multiplex = XMC_DATA_ADDR_MUX_ENABLE;
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xmc_nor_sram_init_struct->device = XMC_DEVICE_SRAM;
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xmc_nor_sram_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
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xmc_nor_sram_init_struct->burst_mode_enable = XMC_BURST_MODE_DISABLE;
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xmc_nor_sram_init_struct->asynwait_enable = XMC_ASYN_WAIT_DISABLE;
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xmc_nor_sram_init_struct->wait_signal_lv = XMC_WAIT_SIGNAL_LEVEL_LOW;
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xmc_nor_sram_init_struct->wrapped_mode_enable = XMC_WRAPPED_MODE_DISABLE;
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xmc_nor_sram_init_struct->wait_signal_config = XMC_WAIT_SIGNAL_SYN_BEFORE;
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xmc_nor_sram_init_struct->write_enable = XMC_WRITE_OPERATION_ENABLE;
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xmc_nor_sram_init_struct->wait_signal_enable = XMC_WAIT_SIGNAL_ENABLE;
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xmc_nor_sram_init_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
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xmc_nor_sram_init_struct->write_burst_syn = XMC_WRITE_BURST_SYN_DISABLE;
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}
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/**
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* @brief fill each xmc_rw_timing_struct and xmc_w_timing_struct member with its default value.
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* @param xmc_rw_timing_struct: pointer to a xmc_norsram_timing_init_type
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* structure which will be initialized.
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* @param xmc_w_timing_struct: pointer to a xmc_norsram_timing_init_type
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* structure which will be initialized.
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* @retval none
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*/
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void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
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xmc_norsram_timing_init_type* xmc_w_timing_struct)
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{
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xmc_rw_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
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xmc_rw_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
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xmc_rw_timing_struct->addr_setup_time = 0xF;
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xmc_rw_timing_struct->addr_hold_time = 0xF;
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xmc_rw_timing_struct->data_setup_time = 0xFF;
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xmc_rw_timing_struct->bus_latency_time = 0xF;
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xmc_rw_timing_struct->clk_psc = 0xF;
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xmc_rw_timing_struct->data_latency_time = 0xF;
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xmc_rw_timing_struct->mode = XMC_ACCESS_MODE_A;
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xmc_w_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
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xmc_w_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
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xmc_w_timing_struct->addr_setup_time = 0xF;
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xmc_w_timing_struct->addr_hold_time = 0xF;
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xmc_w_timing_struct->data_setup_time = 0xFF;
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xmc_w_timing_struct->bus_latency_time = 0xF;
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xmc_w_timing_struct->clk_psc = 0xF;
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xmc_w_timing_struct->data_latency_time = 0xF;
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xmc_w_timing_struct->mode = XMC_ACCESS_MODE_A;
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}
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/**
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* @brief enable or disable the specified nor/sram memory bank.
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* @param xmc_subbank
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* this parameter can be one of the following values:
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* - XMC_BANK1_NOR_SRAM1
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* - XMC_BANK1_NOR_SRAM4
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* @param new_state (TRUE or FALSE)
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* @retval none
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*/
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void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state)
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{
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XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl_bit.en = new_state;
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}
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/**
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* @brief config the bus turnaround phase.
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* @param xmc_sub_bank
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* this parameter can be one of the following values:
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* - XMC_BANK1_NOR_SRAM1
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* - XMC_BANK1_NOR_SRAM4
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* @param w2w_timing :write timing
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* @param r2r_timing :read timing
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* @retval none
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*/
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void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
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{
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XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8;
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XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;
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}
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/**
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* @brief xmc nand flash registers reset
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* @param xmc_bank
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* this parameter can be one of the following values:
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* - XMC_BANK2_NAND
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* @retval none
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*/
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void xmc_nand_reset(xmc_class_bank_type xmc_bank)
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{
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/* set the XMC_BANK2_NAND registers to their reset values */
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if(xmc_bank == XMC_BANK2_NAND)
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{
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XMC_BANK2->bk2ctrl = 0x00000018;
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XMC_BANK2->bk2is = 0x00000040;
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XMC_BANK2->bk2tmgatt = 0xFCFCFCFC;
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XMC_BANK2->bk2tmgmem = 0xFCFCFCFC;
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}
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}
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/**
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* @brief initialize the xmc nand banks according to the specified
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* parameters in the xmc_nandinitstruct.
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* @param xmc_nand_init_struct : pointer to a xmc_nand_init_type
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* structure that contains the configuration information for the xmc
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* nand specified banks.
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* @retval none
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*/
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void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct)
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{
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uint32_t tempctrl = 0x0;
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/* Set the tempctrl value according to xmc_nand_init_struct parameters */
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tempctrl = (uint32_t)xmc_nand_init_struct->wait_enable |
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xmc_nand_init_struct->bus_type |
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xmc_nand_init_struct->ecc_enable |
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xmc_nand_init_struct->ecc_pagesize |
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(xmc_nand_init_struct->delay_time_cycle << 9) |
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(xmc_nand_init_struct->delay_time_ar << 13) |
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0x00000008;
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/* xmc_bank2_nand registers configuration */
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if(xmc_nand_init_struct->nand_bank == XMC_BANK2_NAND)
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{
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XMC_BANK2->bk2ctrl = tempctrl;
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}
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}
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/**
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* @brief initialize the xmc nand banks according to the specified
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* parameters in the xmc_nandinitstruct.
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* @param xmc_regular_spacetiming_struct : pointer to a xmc_nand_timinginit_type
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* structure that contains the configuration information for the xmc
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* nand specified banks.
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* @param xmc_special_spacetiming_struct : pointer to a xmc_nand_timinginit_type
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* structure that contains the configuration information for the xmc
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* nand specified banks.
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* @retval none
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*/
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void xmc_nand_timing_config(xmc_nand_timinginit_type* xmc_regular_spacetiming_struct,
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xmc_nand_timinginit_type* xmc_special_spacetiming_struct)
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{
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uint32_t tempmem = 0x0, tempatt = 0x0;
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/* set the tempmem value according to xmc_nand_init_struct parameters */
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tempmem = (uint32_t)xmc_regular_spacetiming_struct->mem_setup_time |
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(xmc_regular_spacetiming_struct->mem_waite_time << 8) |
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(xmc_regular_spacetiming_struct->mem_hold_time << 16) |
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(xmc_regular_spacetiming_struct->mem_hiz_time << 24);
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/* set the tempatt value according to xmc_nand_init_struct parameters */
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tempatt = (uint32_t)xmc_special_spacetiming_struct->mem_setup_time |
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(xmc_special_spacetiming_struct->mem_waite_time << 8) |
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(xmc_special_spacetiming_struct->mem_hold_time << 16) |
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(xmc_special_spacetiming_struct->mem_hiz_time << 24);
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/* xmc_bank2_nand registers configuration */
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if(xmc_regular_spacetiming_struct->class_bank == XMC_BANK2_NAND)
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{
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XMC_BANK2->bk2tmgatt = tempatt;
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XMC_BANK2->bk2tmgmem = tempmem;
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}
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}
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/**
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* @brief fill each xmc_nand_init_struct member with its default value.
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* @param xmc_nand_init_struct: pointer to a xmc_nand_init_type
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* structure which will be initialized.
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* @retval none
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*/
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void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct)
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{
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/* reset nand init structure parameters values */
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xmc_nand_init_struct->nand_bank = XMC_BANK2_NAND;
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xmc_nand_init_struct->wait_enable = XMC_WAIT_OPERATION_DISABLE;
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xmc_nand_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
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xmc_nand_init_struct->ecc_enable = XMC_ECC_OPERATION_DISABLE;
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xmc_nand_init_struct->ecc_pagesize = XMC_ECC_PAGESIZE_256_BYTES;
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xmc_nand_init_struct->delay_time_cycle = 0x0;
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xmc_nand_init_struct->delay_time_ar = 0x0;
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}
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/**
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* @brief fill each xmc_common_spacetiming_struct and xmc_attribute_spacetiming_struct member with its default value.
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* @param xmc_common_spacetiming_struct: pointer to a xmc_nand_timinginit_type
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* structure which will be initialized.
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* @param xmc_special_spacetiming_struct: pointer to a xmc_nand_timinginit_type
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* structure which will be initialized.
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* @retval none
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*/
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void xmc_nand_timing_default_para_init(xmc_nand_timinginit_type* xmc_regular_spacetiming_struct,
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xmc_nand_timinginit_type* xmc_special_spacetiming_struct)
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{
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xmc_regular_spacetiming_struct->class_bank = XMC_BANK2_NAND;
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xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
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xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
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xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
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xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
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xmc_special_spacetiming_struct->class_bank = XMC_BANK2_NAND;
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xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
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xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
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xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
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xmc_special_spacetiming_struct->mem_hiz_time = 0xFC;
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}
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/**
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* @brief enable or disable the specified nand memory bank.
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* @param xmc_bank: specifies the xmc bank to be used
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* this parameter can be one of the following values:
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* - XMC_BANK2_NAND
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* @param new_state (TRUE or FALSE)
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* @retval none
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*/
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void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
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{
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/* enable or disable the nand bank2 by setting the en bit in the bk2ctrl register */
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if(xmc_bank == XMC_BANK2_NAND)
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{
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XMC_BANK2->bk2ctrl_bit.en = new_state;
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}
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}
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/**
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* @brief enable or disable the xmc nand ecc feature.
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* @param xmc_bank: specifies the xmc bank to be used
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* this parameter can be one of the following values:
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* - XMC_BANK2_NAND
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* @param new_state (TRUE or FALSE)
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* @retval none
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*/
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void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
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{
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/* enable the selected nand bank2 ecc function by setting the eccen bit in the bk2ctrl register */
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if(xmc_bank == XMC_BANK2_NAND)
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{
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XMC_BANK2->bk2ctrl_bit.eccen = new_state;
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}
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}
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/**
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* @brief return the error correction code register value.
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* @param xmc_bank: specifies the xmc bank to be used
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* this parameter can be one of the following values:
|
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* - XMC_BANK2_NAND
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* @retval the error correction code (ecc) value.
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*/
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uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank)
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{
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uint32_t eccvaule = 0x0;
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|
|
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/* get the bk2ecc register value */
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if(xmc_bank == XMC_BANK2_NAND)
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{
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eccvaule = XMC_BANK2->bk2ecc;
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}
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|
|
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/* return the error correction code value */
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return eccvaule;
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|
}
|
|
|
|
/**
|
|
* @brief enable or disable the specified xmc interrupts.
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|
* @param xmc_bank: specifies the xmc bank to be used
|
|
* this parameter can be one of the following values:
|
|
* - XMC_BANK2_NAND
|
|
* @param xmc_int: specifies the xmc interrupt sources to be enabled or disabled.
|
|
* this parameter can be any combination of the following values:
|
|
* - XMC_INT_RISING_EDGE
|
|
* - XMC_INT_LEVEL
|
|
* - XMC_INT_FALLING_EDGE
|
|
* @param new_state (TRUE or FALSE)
|
|
* @retval none
|
|
*/
|
|
void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state)
|
|
{
|
|
if(new_state != FALSE)
|
|
{
|
|
/* enable the selected xmc_bank2 interrupts */
|
|
if(xmc_bank == XMC_BANK2_NAND)
|
|
{
|
|
XMC_BANK2->bk2is |= xmc_int;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* disable the selected xmc_bank2 interrupts */
|
|
if(xmc_bank == XMC_BANK2_NAND)
|
|
{
|
|
XMC_BANK2->bk2is &= ~xmc_int;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief check whether the specified xmc flag is set or not.
|
|
* @param xmc_bank: specifies the xmc bank to be used
|
|
* this parameter can be one of the following values:
|
|
* - XMC_BANK2_NAND
|
|
* @param xmc_flag: specifies the flag to check.
|
|
* this parameter can be any combination of the following values:
|
|
* - XMC_RISINGEDGE_FLAG
|
|
* - XMC_LEVEL_FLAG
|
|
* - XMC_FALLINGEDGE_FLAG
|
|
* - XMC_FEMPT_FLAG
|
|
* @retval none
|
|
*/
|
|
flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
|
|
{
|
|
flag_status status = RESET;
|
|
uint32_t temp = 0;
|
|
|
|
if(xmc_bank == XMC_BANK2_NAND)
|
|
{
|
|
temp = XMC_BANK2->bk2is;
|
|
}
|
|
/* get the flag status */
|
|
if((temp & xmc_flag) == RESET)
|
|
{
|
|
status = RESET;
|
|
}
|
|
else
|
|
{
|
|
status = SET;
|
|
}
|
|
/* return the flag status */
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief clear the xmc's pending flags.
|
|
* @param xmc_bank: specifies the xmc bank to be used
|
|
* this parameter can be one of the following values:
|
|
* - XMC_BANK2_NAND
|
|
* @param xmc_flag: specifies the flag to check.
|
|
* this parameter can be any combination of the following values:
|
|
* - XMC_RISINGEDGE_FLAG
|
|
* - XMC_LEVEL_FLAG
|
|
* - XMC_FALLINGEDGE_FLAG
|
|
* - XMC_FEMPT_FLAG
|
|
* @retval none
|
|
*/
|
|
void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
|
|
{
|
|
__IO uint32_t int_state;
|
|
if(xmc_bank == XMC_BANK2_NAND)
|
|
{
|
|
int_state = XMC_BANK2->bk2is & 0x38; /* keep interrupt state */
|
|
XMC_BANK2->bk2is = (~(xmc_flag | 0x38) | int_state);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|