update version to v2.1.9

This commit is contained in:
Artery-MCU
2024-08-27 09:37:50 +08:00
parent ba2f6ccee8
commit f2cb360c3d
633 changed files with 1567 additions and 3934 deletions

View File

@@ -161,7 +161,7 @@ extern "C" {
*/
#define __AT32F403A_407_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F403A_407_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */
#define __AT32F403A_407_LIBRARY_VERSION_MINOR (0x08) /*!< [15:8] minor version */
#define __AT32F403A_407_LIBRARY_VERSION_MINOR (0x09) /*!< [15:8] minor version */
#define __AT32F403A_407_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F403A_407_LIBRARY_VERSION ((__AT32F403A_407_LIBRARY_VERSION_MAJOR << 24) | \
(__AT32F403A_407_LIBRARY_VERSION_MIDDLE << 16) | \

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@@ -82,6 +82,7 @@ extern "C" {
typedef enum
{
EXINT_LINE_INTERRUPUT = 0x00, /*!< external interrupt line interrupt mode */
EXINT_LINE_INTERRUPT = 0x00, /*!< same as EXINT_LINE_INTERRUPUT, fixed spelling error */
EXINT_LINE_EVENT = 0x01 /*!< external interrupt line event mode */
} exint_line_mode_type;

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@@ -398,7 +398,7 @@ typedef struct
xmc_bank1_tmgwr_reg_type tmgwr_group[4];
/**
* @brief xmc bank1 reserved register, offset:0x120~0x21C
* @brief xmc bank1 reserved register, offset:0x120~0x220
*/
__IO uint32_t reserved2[63];

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@@ -83,7 +83,7 @@ void exint_init(exint_init_type *exint_struct)
if(exint_struct->line_enable != FALSE)
{
if(exint_struct->line_mode == EXINT_LINE_INTERRUPUT)
if(exint_struct->line_mode == EXINT_LINE_INTERRUPT)
{
EXINT->inten |= line_index;
}

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@@ -819,7 +819,7 @@ flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data)
/**
* @brief config erase/program protection for the desired sectors.
* @param sector_bits:
* @param sector_bits(1:ENABLE, 0:DISABLE)
* the pointer of the address of the sectors to be erase/program protected.
* general every bit is used to protect the 4KB bytes, and the last one bit
* is used to protect the rest.

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@@ -173,7 +173,14 @@ void i2c_init(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty, uint32_t speed)
i2c_x->clkctrl_bit.speedmode = TRUE;
/* set the maximum rise time */
i2c_x->tmrise_bit.risetime = (uint16_t)(((freq_mhz * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
if(speed <= 400000)
{
i2c_x->tmrise_bit.risetime = (uint16_t)(((freq_mhz * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
}
else
{
i2c_x->tmrise_bit.risetime = (uint16_t)(((freq_mhz * (uint16_t)120) / (uint16_t)1000) + (uint16_t)1);
}
}
}
@@ -704,13 +711,15 @@ void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag)
{
i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x0000DF00);
if(i2c_x->sts1 & I2C_ADDR7F_FLAG)
if(flag & I2C_ADDR7F_FLAG)
{
UNUSED(i2c_x->sts1);
UNUSED(i2c_x->sts2);
}
if(i2c_x->sts1 & I2C_STOPF_FLAG)
if(flag & I2C_STOPF_FLAG)
{
UNUSED(i2c_x->sts1);
i2c_x->ctrl1_bit.i2cen = TRUE;
}
}

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@@ -483,26 +483,28 @@ flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag
flag_status xmc_interrupt_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
{
flag_status status = RESET;
switch(xmc_flag)
if(xmc_bank == XMC_BANK2_NAND)
{
case XMC_RISINGEDGE_FLAG:
if(XMC_BANK2->bk2is_bit.reien && XMC_BANK2->bk2is_bit.res)
status = SET;
break;
case XMC_LEVEL_FLAG:
if(XMC_BANK2->bk2is_bit.feien && XMC_BANK2->bk2is_bit.fes)
status = SET;
break;
case XMC_FALLINGEDGE_FLAG:
if(XMC_BANK2->bk2is_bit.hlien && XMC_BANK2->bk2is_bit.hls)
status = SET;
break;
default:
break;
switch(xmc_flag)
{
case XMC_RISINGEDGE_FLAG:
if(XMC_BANK2->bk2is_bit.reien && XMC_BANK2->bk2is_bit.res)
status = SET;
break;
case XMC_LEVEL_FLAG:
if(XMC_BANK2->bk2is_bit.feien && XMC_BANK2->bk2is_bit.fes)
status = SET;
break;
case XMC_FALLINGEDGE_FLAG:
if(XMC_BANK2->bk2is_bit.hlien && XMC_BANK2->bk2is_bit.hls)
status = SET;
break;
default:
break;
}
}
/* return the flag status */