update version to v2.0.7

This commit is contained in:
Artery-MCU
2022-03-03 19:28:16 +08:00
parent e1d3f6e2c9
commit eb00682e95
2098 changed files with 11432 additions and 6380 deletions

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_acc.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 acc header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_adc.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 adc header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_bpr.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 bpr header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_can.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 can header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_crc.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 crc header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_crm.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 crm header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -57,6 +57,7 @@ extern "C" {
#define CRM_PLL_STABLE_FLAG MAKE_VALUE(0x00, 25) /*!< phase locking loop stable flag */
#define CRM_LEXT_STABLE_FLAG MAKE_VALUE(0x20, 1) /*!< low speed external crystal stable flag */
#define CRM_LICK_STABLE_FLAG MAKE_VALUE(0x24, 1) /*!< low speed internal clock stable flag */
#define CRM_ALL_RESET_FLAG MAKE_VALUE(0x24, 24) /*!< all reset flag */
#define CRM_NRST_RESET_FLAG MAKE_VALUE(0x24, 26) /*!< nrst pin reset flag */
#define CRM_POR_RESET_FLAG MAKE_VALUE(0x24, 27) /*!< power on reset flag */
#define CRM_SW_RESET_FLAG MAKE_VALUE(0x24, 28) /*!< software reset flag */

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_dac.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 dac header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -344,7 +344,7 @@ void dac_reset(void);
void dac_enable(dac_select_type dac_select, confirm_state new_state);
void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state);
void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state);
void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_select);
void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_source);
void dac_software_trigger_generate(dac_select_type dac_select);
void dac_dual_software_trigger_generate(void);
void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave);

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_debug.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 debug header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -121,18 +121,18 @@ typedef struct
__IO uint32_t can1_pause : 1;/* [14] */
__IO uint32_t i2c1_smbus_timeout : 1;/* [15] */
__IO uint32_t i2c2_smbus_timeout : 1;/* [16] */
__IO uint32_t tim8_pause : 1;/* [17] */
__IO uint32_t tim5_pause : 1;/* [18] */
__IO uint32_t tim6_pause : 1;/* [19] */
__IO uint32_t tim7_pause : 1;/* [20] */
__IO uint32_t tmr8_pause : 1;/* [17] */
__IO uint32_t tmr5_pause : 1;/* [18] */
__IO uint32_t tmr6_pause : 1;/* [19] */
__IO uint32_t tmr7_pause : 1;/* [20] */
__IO uint32_t can2_pause : 1;/* [21] */
__IO uint32_t reserved2 : 3;/* [24:22] */
__IO uint32_t tim12_pause : 1;/* [25] */
__IO uint32_t tim13_pause : 1;/* [26] */
__IO uint32_t tim14_pause : 1;/* [27] */
__IO uint32_t tim9_pause : 1;/* [28] */
__IO uint32_t tim10_pause : 1;/* [29] */
__IO uint32_t tim11_pause : 1;/* [30] */
__IO uint32_t tmr12_pause : 1;/* [25] */
__IO uint32_t tmr13_pause : 1;/* [26] */
__IO uint32_t tmr14_pause : 1;/* [27] */
__IO uint32_t tmr9_pause : 1;/* [28] */
__IO uint32_t tmr10_pause : 1;/* [29] */
__IO uint32_t tmr11_pause : 1;/* [30] */
__IO uint32_t i2c3_smbus_timeout : 1;/* [31] */
} ctrl_bit;
};

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_def.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 macros header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_dma.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 dma header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_emac.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 emac header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_exint.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 exint header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_flash.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 flash header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_gpio.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 gpio header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -259,7 +259,7 @@ extern "C" {
#define SWJTAG_GMUX_100 IOMUX_MAKE_VALUE(0x30, 16, 3, 0x04) /*!< full swj disabled (jtag-dp + sw-dp) */
#define PD01_GMUX IOMUX_MAKE_VALUE(0x30, 20, 1, 0x01) /*!< pd0/pd1 mapping on osc_in/osc_out */
#define XMC_GMUX_001 IOMUX_MAKE_VALUE(0x30, 24, 3, 0x01) /*!< xmc_nwe(pd2), xmc_d0(pb14), xmc_d1(pc6), xmc_d2(pc11), xmc_d3(pc12), xmc_d4(pa2), xmc_d5(pa3), xmc_d6(pa4), xmc_d7(pa5), xmc_d13(pb12), xmc_noe(pc5) */
#define XMC_GMUX_010 IOMUX_MAKE_VALUE(0x30, 24, 3, 0x02) /*!< xmc_nwe(pd2), xmc_d0(pb14), xmc_d1(pc6), xmc_d2(pc11), xmc_d3(pc12), xmc_d4(pa2), xmc_d5(pa3), xmc_d6(pa4), xmc_d7(pa5), xmc_d13(pb12), xmc_noe(pc5) */
#define XMC_GMUX_010 IOMUX_MAKE_VALUE(0x30, 24, 3, 0x02) /*!< xmc_nwe(pc2), xmc_d0(pb14), xmc_d1(pc6), xmc_d2(pc11), xmc_d3(pc12), xmc_d4(pa2), xmc_d5(pa3), xmc_d6(pa4), xmc_d7(pa5), xmc_d13(pb12), xmc_noe(pc5) */
#define XMC_NADV_GMUX IOMUX_MAKE_VALUE(0x30, 27, 1, 0x01) /*!< xmc_nadv not used */
/**

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_i2c.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 i2c header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_misc.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 misc header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -99,8 +99,8 @@ typedef enum
*/
void nvic_system_reset(void);
void nvic_irq_enable(uint32_t irqn, uint32_t preempt_priority, uint32_t sub_priority);
void nvic_irq_disable(uint32_t irqn);
void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority);
void nvic_irq_disable(IRQn_Type irqn);
void nvic_priority_group_config(nvic_priority_group_type priority_group);
void nvic_vector_table_set(uint32_t base, uint32_t offset);
void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_pwc.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 pwc header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_rtc.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 rtc header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_sdio.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 sdio header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_spi.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 spi header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_tmr.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 tmr header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -174,8 +174,8 @@ typedef enum
TMR_OUTPUT_CONTROL_HIGH = 0x01, /*!< tmr output control mode high */
TMR_OUTPUT_CONTROL_LOW = 0x02, /*!< tmr output control mode low */
TMR_OUTPUT_CONTROL_SWITCH = 0x03, /*!< tmr output control mode switch */
TMR_OUTPUT_CONTROL_FORCE_HIGH = 0x04, /*!< tmr output control mode force high */
TMR_OUTPUT_CONTROL_FORCE_LOW = 0x05, /*!< tmr output control mode force low */
TMR_OUTPUT_CONTROL_FORCE_LOW = 0x04, /*!< tmr output control mode force low */
TMR_OUTPUT_CONTROL_FORCE_HIGH = 0x05, /*!< tmr output control mode force high */
TMR_OUTPUT_CONTROL_PWM_MODE_A = 0x06, /*!< tmr output control mode pwm a */
TMR_OUTPUT_CONTROL_PWM_MODE_B = 0x07 /*!< tmr output control mode pwm b */
} tmr_output_control_mode_type;

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_usart.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 usart header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_usb.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 usb header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_wdt.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 wdt header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_wwdt.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 wwdt header file
**************************************************************************
* Copyright notice & Disclaimer

View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_xmc.h
* @version v2.0.6
* @date 2021-12-31
* @version v2.0.7
* @date 2022-02-11
* @brief at32f403a_407 xmc header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -402,7 +402,7 @@ typedef struct
/**
* @brief xmc bank1 reserved register, offset:0x120~0x21C
*/
__IO uint32_t reserved2[64];
__IO uint32_t reserved2[63];
/**
* @brief xmc bank1 ext register, offset:0x220~0x22C