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update version to v2.0.6

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Artery-MCU
2022-01-21 15:43:43 +08:00
parent 4fd69ebc78
commit e1d3f6e2c9
2457 changed files with 68919 additions and 60424 deletions
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320
libraries/drivers/src/at32f403a_407_xmc.c
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_xmc.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the xmc firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -43,28 +43,26 @@
/**
* @brief xmc nor or sram registers reset
* @param xmc_bank
* @param xmc_subbank
* this parameter can be one of the following values:
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM2
* - XMC_BANK1_NOR_SRAM3
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM4
* @retval none
*/
void xmc_nor_sram_reset(xmc_nor_sram_bank_type xmc_bank)
void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank)
{
/* XMC_BANK1_NORSRAM1 */
if(xmc_bank == XMC_BANK1_NOR_SRAM1)
if(xmc_subbank == XMC_BANK1_NOR_SRAM1)
{
XMC_BANK1->bk1ctrl[xmc_bank] = 0x000030DB;
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030DB;
}
/* XMC_BANK1_NORSRAM2, XMC_BANK1_NORSRAM3 or XMC_BANK1_NORSRAM4 */
else
{
XMC_BANK1->bk1ctrl[xmc_bank] = 0x000030D2;
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030D2;
}
XMC_BANK1->bk1ctrl[xmc_bank + 1] = 0x0FFFFFFF;
XMC_BANK1E->bk1tmgwr[xmc_bank] = 0x0FFFFFFF;
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1tmg = 0x0FFFFFFF;
XMC_BANK1->tmgwr_group[xmc_subbank].bk1tmgwr = 0x0FFFFFFF;
}
/**
@@ -78,7 +76,7 @@ void xmc_nor_sram_reset(xmc_nor_sram_bank_type xmc_bank)
void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct)
{
/* bank1 nor/sram control register configuration */
XMC_BANK1->bk1ctrl[xmc_norsram_init_struct->bank] =
XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl =
(uint32_t)xmc_norsram_init_struct->data_addr_multiplex |
xmc_norsram_init_struct->device |
xmc_norsram_init_struct->bus_type |
@@ -95,7 +93,7 @@ void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct)
/* if nor flash device */
if(xmc_norsram_init_struct->device == XMC_DEVICE_NOR)
{
XMC_BANK1->bk1ctrl_bit[xmc_norsram_init_struct->bank].noren = 0x1;
XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl_bit.noren = 0x1;
}
}
@@ -114,7 +112,7 @@ void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_stru
xmc_norsram_timing_init_type* xmc_w_timing_struct)
{
/* bank1 nor/sram timing register configuration */
XMC_BANK1->bk1ctrl[xmc_rw_timing_struct->bank + 1] =
XMC_BANK1->ctrl_tmg_group[xmc_rw_timing_struct->subbank].bk1tmg =
(uint32_t)xmc_rw_timing_struct->addr_setup_time |
(xmc_rw_timing_struct->addr_hold_time << 4) |
(xmc_rw_timing_struct->data_setup_time << 8) |
@@ -126,7 +124,7 @@ void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_stru
/* bank1 nor/sram timing register for write configuration, if extended mode is used */
if(xmc_rw_timing_struct->write_timing_enable == XMC_WRITE_TIMING_ENABLE)
{
XMC_BANK1E->bk1tmgwr[xmc_w_timing_struct->bank] =
XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr =
(uint32_t)xmc_w_timing_struct->addr_setup_time |
(xmc_w_timing_struct->addr_hold_time << 4) |
(xmc_w_timing_struct->data_setup_time << 8) |
@@ -137,7 +135,7 @@ void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_stru
}
else
{
XMC_BANK1E->bk1tmgwr[xmc_w_timing_struct->bank] = 0x0FFFFFFF;
XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr = 0x0FFFFFFF;
}
}
@@ -150,7 +148,7 @@ void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_stru
void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct)
{
/* reset nor/sram init structure parameters values */
xmc_nor_sram_init_struct->bank = XMC_BANK1_NOR_SRAM1;
xmc_nor_sram_init_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_nor_sram_init_struct->data_addr_multiplex = XMC_DATA_ADDR_MUX_ENABLE;
xmc_nor_sram_init_struct->device = XMC_DEVICE_SRAM;
xmc_nor_sram_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
@@ -176,7 +174,7 @@ void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_stru
void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct)
{
xmc_rw_timing_struct->bank = XMC_BANK1_NOR_SRAM1;
xmc_rw_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_rw_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
xmc_rw_timing_struct->addr_setup_time = 0xF;
xmc_rw_timing_struct->addr_hold_time = 0xF;
@@ -185,7 +183,7 @@ void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_t
xmc_rw_timing_struct->clk_psc = 0xF;
xmc_rw_timing_struct->data_latency_time = 0xF;
xmc_rw_timing_struct->mode = XMC_ACCESS_MODE_A;
xmc_w_timing_struct->bank = XMC_BANK1_NOR_SRAM1;
xmc_w_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_w_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
xmc_w_timing_struct->addr_setup_time = 0xF;
xmc_w_timing_struct->addr_hold_time = 0xF;
@@ -198,64 +196,51 @@ void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_t
/**
* @brief enable or disable the specified nor/sram memory bank.
* @param xmc_bank
* @param xmc_subbank
* this parameter can be one of the following values:
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM2
* - XMC_BANK1_NOR_SRAM3
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM4
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nor_sram_enable(xmc_nor_sram_bank_type xmc_bank, confirm_state new_state)
void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state)
{
XMC_BANK1->bk1ctrl_bit[xmc_bank].en = new_state;
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl_bit.en = new_state;
}
/**
* @brief config the bus turnaround phase.
* @param xmc_sub_bank
* this parameter can be one of the following values:
* - XMC_SUBBANK1_NOR_SRAM1
* - XMC_SUBBANK1_NOR_SRAM2
* - XMC_SUBBANK1_NOR_SRAM3
* - XMC_SUBBANK1_NOR_SRAM4
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM4
* @param w2w_timing :write timing
* @param r2r_timing :read timing
* @retval none
*/
void xmc_ext_timing_config(xmc_subbank1_nor_sram_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
{
XMC_BANK1H->bk1ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8;
XMC_BANK1H->bk1ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;
XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8;
XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;
}
/**
* @brief xmc nand flash registers reset
* @param xmc_bank
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* - XMC_BANK2_NAND
* @retval none
*/
void xmc_nand_reset(xmc_nand_bank_type xmc_bank)
void xmc_nand_reset(xmc_class_bank_type xmc_bank)
{
/* set the XMC_BANK2_NAND registers to their reset values */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl = 0x00000018;
XMC_BANK2->bk2sts = 0x00000040;
XMC_BANK2->bk2is = 0x00000040;
XMC_BANK2->bk2tmgatt = 0xFCFCFCFC;
XMC_BANK2->bk2tmgmem = 0xFCFCFCFC;
}
/* set the XMC_BANK3_NAND registers to their reset values */
else
{
XMC_BANK3->bk3ctrl = 0x00000018;
XMC_BANK3->bk3sts = 0x00000040;
XMC_BANK3->bk3tmgatt = 0xFCFCFCFC;
XMC_BANK3->bk3tmgmem = 0xFCFCFCFC;
}
}
/**
@@ -284,26 +269,21 @@ void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct)
{
XMC_BANK2->bk2ctrl = tempctrl;
}
/* xmc_bank3_nand registers configuration */
else
{
XMC_BANK3->bk3ctrl = tempctrl;
}
}
/**
* @brief initialize the xmc nand banks according to the specified
* parameters in the xmc_nandinitstruct.
* @param xmc_regular_spacetiming_struct : pointer to a xmc_nand_pccard_timinginit_type
* @param xmc_regular_spacetiming_struct : pointer to a xmc_nand_timinginit_type
* structure that contains the configuration information for the xmc
* nand specified banks.
* @param xmc_special_spacetiming_struct : pointer to a xmc_nand_pccard_timinginit_type
* @param xmc_special_spacetiming_struct : pointer to a xmc_nand_timinginit_type
* structure that contains the configuration information for the xmc
* nand specified banks.
* @retval none
*/
void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct)
void xmc_nand_timing_config(xmc_nand_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_timinginit_type* xmc_special_spacetiming_struct)
{
uint32_t tempmem = 0x0, tempatt = 0x0;
@@ -319,16 +299,11 @@ void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spaceti
(xmc_special_spacetiming_struct->mem_hold_time << 16) |
(xmc_special_spacetiming_struct->mem_hiz_time << 24);
/* xmc_bank2_nand registers configuration */
if(xmc_regular_spacetiming_struct->nand_bank == XMC_BANK2_NAND)
if(xmc_regular_spacetiming_struct->class_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2tmgatt = tempatt;
XMC_BANK2->bk2tmgmem = tempmem;
}
else
{
XMC_BANK3->bk3tmgatt = tempatt;
XMC_BANK3->bk3tmgmem = tempmem;
}
}
/**
@@ -351,21 +326,21 @@ void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct)
/**
* @brief fill each xmc_common_spacetiming_struct and xmc_attribute_spacetiming_struct member with its default value.
* @param xmc_common_spacetiming_struct: pointer to a xmc_nand_pccard_timinginit_type
* @param xmc_common_spacetiming_struct: pointer to a xmc_nand_timinginit_type
* structure which will be initialized.
* @param xmc_special_spacetiming_struct: pointer to a xmc_nand_pccard_timinginit_type
* @param xmc_special_spacetiming_struct: pointer to a xmc_nand_timinginit_type
* structure which will be initialized.
* @retval none
*/
void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct)
void xmc_nand_timing_default_para_init(xmc_nand_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_timinginit_type* xmc_special_spacetiming_struct)
{
xmc_regular_spacetiming_struct->nand_bank = XMC_BANK2_NAND;
xmc_regular_spacetiming_struct->class_bank = XMC_BANK2_NAND;
xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
xmc_special_spacetiming_struct->nand_bank = XMC_BANK2_NAND;
xmc_special_spacetiming_struct->class_bank = XMC_BANK2_NAND;
xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
@@ -377,22 +352,16 @@ void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regu
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nand_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state)
void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
{
/* enable or disable the nand bank2 by setting the en bit in the bk2ctrl register */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl_bit.en = new_state;
}
/* enable or disable the nand bank3 by setting the en bit in the bk3ctrl register */
else
{
XMC_BANK3->bk3ctrl_bit.en = new_state;
}
}
/**
@@ -400,22 +369,16 @@ void xmc_nand_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state)
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nand_ecc_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state)
void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
{
/* enable the selected nand bank2 ecc function by setting the eccen bit in the bk2ctrl register */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl_bit.eccen = new_state;
}
/* enable the selected nand bank3 ecc function by setting the eccen bit in the bk3ctrl register */
else
{
XMC_BANK3->bk3ctrl_bit.eccen = new_state;
}
}
/**
@@ -423,10 +386,9 @@ void xmc_nand_ecc_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state)
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* @retval the error correction code (ecc) value.
*/
uint32_t xmc_ecc_get(xmc_nand_bank_type xmc_bank)
uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank)
{
uint32_t eccvaule = 0x0;
@@ -435,11 +397,7 @@ uint32_t xmc_ecc_get(xmc_nand_bank_type xmc_bank)
{
eccvaule = XMC_BANK2->bk2ecc;
}
/* get the bk3ecc register value */
else
{
eccvaule = XMC_BANK3->bk3ecc;
}
/* return the error correction code value */
return eccvaule;
}
@@ -449,8 +407,6 @@ uint32_t xmc_ecc_get(xmc_nand_bank_type xmc_bank)
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* - XMC_BANK4_PCCARD
* @param xmc_int: specifies the xmc interrupt sources to be enabled or disabled.
* this parameter can be any combination of the following values:
* - XMC_INT_RISING_EDGE
@@ -459,24 +415,14 @@ uint32_t xmc_ecc_get(xmc_nand_bank_type xmc_bank)
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_interrupt_enable(xmc_nand_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state)
void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state)
{
if(new_state != FALSE)
{
/* enable the selected xmc_bank2 interrupts */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2sts |= xmc_int;
}
/* enable the selected xmc_bank3 interrupts */
else if(xmc_bank == XMC_BANK3_NAND)
{
XMC_BANK3->bk3sts |= xmc_int;
}
/* enable the selected xmc_bank4 interrupts */
else
{
XMC_BANK4->bk4sts |= xmc_int;
XMC_BANK2->bk2is |= xmc_int;
}
}
else
@@ -484,18 +430,8 @@ void xmc_interrupt_enable(xmc_nand_bank_type xmc_bank, xmc_interrupt_sources_typ
/* disable the selected xmc_bank2 interrupts */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2sts &= ~xmc_int;
}
/* disable the selected xmc_bank3 interrupts */
else if(xmc_bank == XMC_BANK3_NAND)
{
XMC_BANK3->bk3sts &= ~xmc_int;
}
/* disable the selected xmc_bank4 interrupts */
else
{
XMC_BANK4->bk4sts &= ~xmc_int;
}
XMC_BANK2->bk2is &= ~xmc_int;
}
}
}
@@ -504,8 +440,6 @@ void xmc_interrupt_enable(xmc_nand_bank_type xmc_bank, xmc_interrupt_sources_typ
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* - XMC_BANK4_PCCARD
* @param xmc_flag: specifies the flag to check.
* this parameter can be any combination of the following values:
* - XMC_RISINGEDGE_FLAG
@@ -514,22 +448,14 @@ void xmc_interrupt_enable(xmc_nand_bank_type xmc_bank, xmc_interrupt_sources_typ
* - XMC_FEMPT_FLAG
* @retval none
*/
flag_status xmc_flag_status_get(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
{
flag_status status = RESET;
uint32_t temp = 0;
if(xmc_bank == XMC_BANK2_NAND)
{
temp = XMC_BANK2->bk2sts;
}
else if(xmc_bank == XMC_BANK3_NAND)
{
temp = XMC_BANK3->bk3sts;
}
else
{
temp = XMC_BANK4->bk4sts;
temp = XMC_BANK2->bk2is;
}
/* get the flag status */
if((temp & xmc_flag) == RESET)
@@ -549,8 +475,6 @@ flag_status xmc_flag_status_get(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* - XMC_BANK4_PCCARD
* @param xmc_flag: specifies the flag to check.
* this parameter can be any combination of the following values:
* - XMC_RISINGEDGE_FLAG
@@ -559,148 +483,14 @@ flag_status xmc_flag_status_get(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_
* - XMC_FEMPT_FLAG
* @retval none
*/
void xmc_flag_clear(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
{
__IO uint32_t int_state;
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2sts &= ~xmc_flag;
int_state = XMC_BANK2->bk2is & 0x38; /* keep interrupt state */
XMC_BANK2->bk2is = (~(xmc_flag | 0x38) | int_state);
}
else if(xmc_bank == XMC_BANK3_NAND)
{
XMC_BANK3->bk3sts &= ~xmc_flag;
}
else
{
XMC_BANK4->bk4sts &= ~xmc_flag;
}
}
/**
* @brief xmc pc card registers reset
* @param none
* @retval none
*/
void xmc_pccard_reset(void)
{
/* Set the XMC_Bank4 registers to their reset values */
XMC_BANK4->bk4ctrl = 0x00000018;
XMC_BANK4->bk4sts = 0x00000000;
XMC_BANK4->bk4tmgatt = 0xFCFCFCFC;
XMC_BANK4->bk4tmgio = 0xFCFCFCFC;
XMC_BANK4->bk4tmgmem = 0xFCFCFCFC;
}
/**
* @brief initialize the xmc pccard bank according to the specified
* parameters in the xmc_pccard_init_struct.
* @param xmc_pccard_init_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @retval none
*/
void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct)
{
/* set the bk4ctrl register value according to xmc_pccard_init_struct parameters */
XMC_BANK4->bk4ctrl = (uint32_t)xmc_pccard_init_struct->enable_wait |
XMC_BUSTYPE_16_BITS |
(xmc_pccard_init_struct->delay_time_cr << 9) |
(xmc_pccard_init_struct->delay_time_ar << 13);
}
/**
* @brief initialize the xmc pccard bank according to the specified
* parameters in the xmc_common_spacetiming_struct/xmc_attribute_spacetiming_struct
* and xmc_iospace_timing_struct.
* @param xmc_regular_spacetiming_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @param xmc_special_spacetiming_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @param xmc_iospace_timing_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @retval none
*/
void xmc_pccard_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct)
{
/* set bk4tmgmem register value according to xmc_regular_spacetiming_struct parameters */
XMC_BANK4->bk4tmgmem = (uint32_t)xmc_regular_spacetiming_struct->mem_setup_time |
(xmc_regular_spacetiming_struct->mem_waite_time << 8) |
(xmc_regular_spacetiming_struct->mem_hold_time << 16) |
(xmc_regular_spacetiming_struct->mem_hiz_time << 24);
/* Set bk4tmgatt register value according to xmc_special_spacetiming_struct parameters */
XMC_BANK4->bk4tmgatt = (uint32_t)xmc_special_spacetiming_struct->mem_setup_time |
(xmc_special_spacetiming_struct->mem_waite_time << 8) |
(xmc_special_spacetiming_struct->mem_hold_time << 16) |
(xmc_special_spacetiming_struct->mem_hiz_time << 24);
/* Set bk4tmgio register value according to xmc_iospace_timing_struct parameters */
XMC_BANK4->bk4tmgio = (uint32_t)xmc_iospace_timing_struct->mem_setup_time |
(xmc_iospace_timing_struct->mem_waite_time << 8) |
(xmc_iospace_timing_struct->mem_hold_time << 16) |
(xmc_iospace_timing_struct->mem_hiz_time << 24);
}
/**
* @brief fill each xmc_pccard_init_struct member with its default value.
* @param xmc_pccard_init_struct: pointer to a xmc_pccardinittype
* structure which will be initialized.
* @retval none
*/
void xmc_pccard_default_para_init(xmc_pccard_init_type* xmc_pccard_init_struct)
{
/* reset pccard init structure parameters values */
xmc_pccard_init_struct->enable_wait = XMC_WAIT_OPERATION_DISABLE;
xmc_pccard_init_struct->delay_time_ar = 0x0;
xmc_pccard_init_struct->delay_time_cr = 0x0;
}
/**
* @brief fill each xmc_common_spacetiming_struct/xmc_attribute_spacetiming_struct
* and xmc_iospace_timing_struct member with its default value.
* @param xmc_regular_spacetiming_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @param xmc_special_spacetiming_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @param xmc_iospace_timing_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @retval none
*/
void xmc_pccard_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct)
{
xmc_regular_spacetiming_struct->nand_bank = XMC_BANK4_PCCARD;
xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
xmc_special_spacetiming_struct->nand_bank = XMC_BANK4_PCCARD;
xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
xmc_special_spacetiming_struct->mem_hiz_time = 0xFC;
xmc_iospace_timing_struct->nand_bank = XMC_BANK4_PCCARD;
xmc_iospace_timing_struct->mem_hold_time = 0xFC;
xmc_iospace_timing_struct->mem_waite_time = 0xFC;
xmc_iospace_timing_struct->mem_setup_time = 0xFC;
xmc_iospace_timing_struct->mem_hiz_time = 0xFC;
}
/**
* @brief enable or disable the pccard memory bank.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_pccard_enable(confirm_state new_state)
{
/* enable the pccard bank4 by setting the en bit in the bk4ctrl register */
XMC_BANK4->bk4ctrl_bit.en = new_state;
}
/**