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update version to v2.0.6

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Artery-MCU
2022-01-21 15:43:43 +08:00
parent 4fd69ebc78
commit e1d3f6e2c9
2457 changed files with 68919 additions and 60424 deletions
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4
libraries/drivers/inc/at32f403a_407_acc.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_acc.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 acc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f403a_407_adc.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_adc.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 adc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f403a_407_bpr.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_bpr.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 bpr header file
**************************************************************************
* Copyright notice & Disclaimer

29
libraries/drivers/inc/at32f403a_407_can.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_can.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 can header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -110,16 +110,21 @@ extern "C" {
/**
* @brief can flag clear operation macro definition val
*/
#define CAN_MSTS_EOIF_VAL ((uint32_t)0x00000004) /*!< eoif bit w1 */
#define CAN_MSTS_QDZIF_VAL ((uint32_t)0x00000008) /*!< qdzif bit w1 */
#define CAN_MSTS_EDZIF_VAL ((uint32_t)0x00000010) /*!< edzif bit w1 */
#define CAN_TSTS_TM0TCF_VAL ((uint32_t)0x00000001) /*!< tm0tcf bit w1 */
#define CAN_TSTS_TM1TCF_VAL ((uint32_t)0x00000100) /*!< tm1tcf bit w1 */
#define CAN_TSTS_TM2TCF_VAL ((uint32_t)0x00010000) /*!< tm2tcf bit w1 */
#define CAN_RF0_RF0FF_VAL ((uint32_t)0x00000008) /*!< rf0ff bit w1 */
#define CAN_RF0_RF0OF_VAL ((uint32_t)0x00000010) /*!< rf0of bit w1 */
#define CAN_RF1_RF1FF_VAL ((uint32_t)0x00000008) /*!< rf1ff bit w1 */
#define CAN_RF1_RF1OF_VAL ((uint32_t)0x00000010) /*!< rf1of bit w1 */
#define CAN_MSTS_EOIF_VAL ((uint32_t)0x00000004) /*!< eoif bit value, it clear by writing 1 */
#define CAN_MSTS_QDZIF_VAL ((uint32_t)0x00000008) /*!< qdzif bit value, it clear by writing 1 */
#define CAN_MSTS_EDZIF_VAL ((uint32_t)0x00000010) /*!< edzif bit value, it clear by writing 1 */
#define CAN_TSTS_TM0TCF_VAL ((uint32_t)0x00000001) /*!< tm0tcf bit value, it clear by writing 1 */
#define CAN_TSTS_TM1TCF_VAL ((uint32_t)0x00000100) /*!< tm1tcf bit value, it clear by writing 1 */
#define CAN_TSTS_TM2TCF_VAL ((uint32_t)0x00010000) /*!< tm2tcf bit value, it clear by writing 1 */
#define CAN_TSTS_TM0CT_VAL ((uint32_t)0x00000080) /*!< tm0ct bit value, it clear by writing 1 */
#define CAN_TSTS_TM1CT_VAL ((uint32_t)0x00008000) /*!< tm1ct bit value, it clear by writing 1 */
#define CAN_TSTS_TM2CT_VAL ((uint32_t)0x00800000) /*!< tm2ct bit value, it clear by writing 1 */
#define CAN_RF0_RF0FF_VAL ((uint32_t)0x00000008) /*!< rf0ff bit value, it clear by writing 1 */
#define CAN_RF0_RF0OF_VAL ((uint32_t)0x00000010) /*!< rf0of bit value, it clear by writing 1 */
#define CAN_RF0_RF0R_VAL ((uint32_t)0x00000020) /*!< rf0r bit value, it clear by writing 1 */
#define CAN_RF1_RF1FF_VAL ((uint32_t)0x00000008) /*!< rf1ff bit value, it clear by writing 1 */
#define CAN_RF1_RF1OF_VAL ((uint32_t)0x00000010) /*!< rf1of bit value, it clear by writing 1 */
#define CAN_RF1_RF1R_VAL ((uint32_t)0x00000020) /*!< rf1r bit value, it clear by writing 1 */
/** @defgroup CAN_exported_types
* @{

4
libraries/drivers/inc/at32f403a_407_crc.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_crc.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 crc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f403a_407_crm.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_crm.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 crm header file
**************************************************************************
* Copyright notice & Disclaimer

7
libraries/drivers/inc/at32f403a_407_dac.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_dac.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 dac header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -44,6 +44,9 @@ extern "C" {
* @{
*/
#define DAC1_D1DMAUDRF ((uint32_t)(0x00002000))
#define DAC2_D2DMAUDRF ((uint32_t)(0x20000000))
/** @defgroup DAC_exported_types
* @{
*/

6
libraries/drivers/inc/at32f403a_407_debug.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_debug.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 debug header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -143,7 +143,7 @@ typedef struct
* @}
*/
#define DEBUG ((debug_type *) DEBUG_BASE)
#define DEBUGMCU ((debug_type *) DEBUG_BASE)
/** @defgroup DEBUG_exported_functions
* @{

69
libraries/drivers/inc/at32f403a_407_def.h Normal file
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@@ -0,0 +1,69 @@
/**
**************************************************************************
* @file at32f403a_407_def.h
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 macros header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F403A_407_DEF_H
#define __AT32F403A_407_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/* gnu compiler */
#if defined (__GNUC__)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL __attribute__ ((aligned (4)))
#endif
#endif
/* arm compiler */
#if defined (__CC_ARM)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD __align(4)
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL
#endif
#endif
/* iar compiler */
#if defined (__ICCARM__)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

4
libraries/drivers/inc/at32f403a_407_dma.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_dma.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 dma header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f403a_407_emac.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_emac.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 emac header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f403a_407_exint.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_exint.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 exint header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f403a_407_flash.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_flash.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 flash header file
**************************************************************************
* Copyright notice & Disclaimer

6
libraries/drivers/inc/at32f403a_407_gpio.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_gpio.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 gpio header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -490,7 +490,7 @@ typedef struct
};
/**
* @brief gpio wcr register, offset:0x10
* @brief gpio scr register, offset:0x10
*/
union
{

4
libraries/drivers/inc/at32f403a_407_i2c.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_i2c.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 i2c header file
**************************************************************************
* Copyright notice & Disclaimer

14
libraries/drivers/inc/at32f403a_407_misc.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_misc.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 misc header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -64,11 +64,11 @@ extern "C" {
*/
typedef enum
{
NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x700), /*!< 0 bits for preemption priority, 4 bits for subpriority */
NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x600), /*!< 1 bits for preemption priority, 3 bits for subpriority */
NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x500), /*!< 2 bits for preemption priority, 2 bits for subpriority */
NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x400), /*!< 3 bits for preemption priority, 1 bits for subpriority */
NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x300) /*!< 4 bits for preemption priority, 0 bits for subpriority */
NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
} nvic_priority_group_type;
/**

11
libraries/drivers/inc/at32f403a_407_pwc.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_pwc.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 pwc header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -57,6 +57,11 @@ extern "C" {
* @}
*/
/**
* @brief pwc wakeup pin num definition
*/
#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */
/** @defgroup PWC_exported_types
* @{
*/
@@ -159,7 +164,7 @@ void pwc_reset(void);
void pwc_battery_powered_domain_access(confirm_state new_state);
void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
void pwc_power_voltage_monitor_enable(confirm_state new_state);
void pwc_wakeup_pin_enable(confirm_state new_state);
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
void pwc_flag_clear(uint32_t pwc_flag);
flag_status pwc_flag_get(uint32_t pwc_flag);
void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);

4
libraries/drivers/inc/at32f403a_407_rtc.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_rtc.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 rtc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f403a_407_sdio.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_sdio.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 sdio header file
**************************************************************************
* Copyright notice & Disclaimer

8
libraries/drivers/inc/at32f403a_407_spi.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_spi.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 spi header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -122,8 +122,8 @@ typedef enum
*/
typedef enum
{
SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is software mode */
SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is hardware mode */
SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is hardware mode */
SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is software mode */
} spi_cs_mode_type;
/**

4
libraries/drivers/inc/at32f403a_407_tmr.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_tmr.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 tmr header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f403a_407_usart.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_usart.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 usart header file
**************************************************************************
* Copyright notice & Disclaimer

5
libraries/drivers/inc/at32f403a_407_usb.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_usb.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 usb header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -690,6 +690,7 @@ void usb_remote_wkup_clear(usbd_type *usbx);
uint16_t usb_buffer_malloc(uint16_t maxpacket);
void usb_buffer_free(void);
flag_status usb_flag_get(usbd_type *usbx, uint16_t flag);
void usb_flag_clear(usbd_type *usbx, uint16_t flag);
#ifdef __cplusplus

4
libraries/drivers/inc/at32f403a_407_wdt.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_wdt.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 wdt header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f403a_407_wwdt.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_wwdt.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 wwdt header file
**************************************************************************
* Copyright notice & Disclaimer

493
libraries/drivers/inc/at32f403a_407_xmc.h
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@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_xmc.h
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief at32f403a_407 xmc header file
**************************************************************************
* Copyright notice & Disclaimer
@@ -121,13 +121,13 @@ typedef enum
} xmc_extended_mode_type;
/**
* @brief xmc pccard wait type
* @brief xmc nand wait type
*/
typedef enum
{
XMC_WAIT_OPERATION_DISABLE = 0x00000000, /*!< xmc wait operation for the pc card/nand flash memory bank disable */
XMC_WAIT_OPERATION_ENABLE = 0x00000002 /*!< xmc wait operation for the pc card/nand flash memory bank enable */
} xmc_nand_pccard_wait_type;
XMC_WAIT_OPERATION_DISABLE = 0x00000000, /*!< xmc wait operation for the nand flash memory bank disable */
XMC_WAIT_OPERATION_ENABLE = 0x00000002 /*!< xmc wait operation for the nand flash memory bank enable */
} xmc_nand_wait_type;
/**
* @brief xmc ecc enable type
@@ -143,32 +143,17 @@ typedef enum
*/
typedef enum
{
XMC_BANK1_NOR_SRAM1 = 0x00000000, /*!< xmc nor/sram bank1 */
XMC_BANK1_NOR_SRAM2 = 0x00000002, /*!< xmc nor/sram bank2 */
XMC_BANK1_NOR_SRAM3 = 0x00000004, /*!< xmc nor/sram bank3 */
XMC_BANK1_NOR_SRAM4 = 0x00000006 /*!< xmc nor/sram bank4 */
} xmc_nor_sram_bank_type;
XMC_BANK1_NOR_SRAM1 = 0x00000000, /*!< xmc nor/sram subbank1 */
XMC_BANK1_NOR_SRAM4 = 0x00000003 /*!< xmc nor/sram subbank4 */
} xmc_nor_sram_subbank_type;
/**
* @brief xmc subbank1 nor/sram type
*/
typedef enum
{
XMC_SUBBANK1_NOR_SRAM1 = 0x00000000, /*!< xmc nor/sram subbank1 */
XMC_SUBBANK1_NOR_SRAM2 = 0x00000001, /*!< xmc nor/sram subbank2 */
XMC_SUBBANK1_NOR_SRAM3 = 0x00000002, /*!< xmc nor/sram subbank3 */
XMC_SUBBANK1_NOR_SRAM4 = 0x00000003 /*!< xmc nor/sram subbank4 */
} xmc_subbank1_nor_sram_type;
/**
* @brief xmc nand bank type
* @brief xmc class bank type
*/
typedef enum
{
XMC_BANK2_NAND = 0x00000010, /*!< xmc nand flash bank2 */
XMC_BANK3_NAND = 0x00000100, /*!< xmc nand flash bank3 */
XMC_BANK4_PCCARD = 0x00001000 /*!< xmc pc card bank4 */
} xmc_nand_bank_type;
} xmc_class_bank_type;
/**
* @brief xmc memory type
@@ -257,7 +242,7 @@ typedef enum
*/
typedef struct
{
xmc_nor_sram_bank_type bank; /*!< xmc nor/sram bank */
xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram write timing enable */
uint32_t addr_setup_time; /*!< xmc nor/sram address setup time */
uint32_t addr_hold_time; /*!< xmc nor/sram address hold time */
@@ -273,7 +258,7 @@ typedef struct
*/
typedef struct
{
xmc_nor_sram_bank_type bank; /*!< xmc nor/sram bank */
xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
xmc_data_addr_mux_type data_addr_multiplex; /*!< xmc nor/sram address/data multiplexing enable */
xmc_memory_type device; /*!< xmc nor/sram memory device */
xmc_data_width_type bus_type; /*!< xmc nor/sram data bus width */
@@ -289,17 +274,17 @@ typedef struct
} xmc_norsram_init_type;
/**
* @brief nand and pccard timing parameters xmc
* @brief nand timing parameters xmc
*/
typedef struct
{
xmc_nand_bank_type nand_bank; /*!< xmc nand/pccard bank */
uint32_t mem_setup_time; /*!< xmc nand/pccard memory setup time */
uint32_t mem_waite_time; /*!< xmc nand/pccard memory wait time */
uint32_t mem_hold_time; /*!< xmc nand/pccard memory hold time */
uint32_t mem_hiz_time; /*!< xmc nand/pccard memory databus high resistance time */
} xmc_nand_pccard_timinginit_type;
xmc_class_bank_type class_bank; /*!< xmc nand bank */
uint32_t mem_setup_time; /*!< xmc nand memory setup time */
uint32_t mem_waite_time; /*!< xmc nand memory wait time */
uint32_t mem_hold_time; /*!< xmc nand memory hold time */
uint32_t mem_hiz_time; /*!< xmc nand memory databus high resistance time */
} xmc_nand_timinginit_type;
/**
* @brief xmc nand init structure definition
@@ -307,8 +292,8 @@ typedef struct
typedef struct
{
xmc_nand_bank_type nand_bank; /*!< xmc nand bank */
xmc_nand_pccard_wait_type wait_enable; /*!< xmc wait feature enable */
xmc_class_bank_type nand_bank; /*!< xmc nand bank */
xmc_nand_wait_type wait_enable; /*!< xmc wait feature enable */
xmc_data_width_type bus_type; /*!< xmc nand bus width */
xmc_ecc_enable_type ecc_enable; /*!< xmc nand ecc enable */
xmc_ecc_pagesize_type ecc_pagesize; /*!< xmc nand ecc page size */
@@ -316,425 +301,253 @@ typedef struct
uint32_t delay_time_ar; /*!< xmc nand ale to re delay */
} xmc_nand_init_type;
/**
* @brief xmc pccard init structure definition
*/
typedef struct
{
xmc_nand_pccard_wait_type enable_wait; /*!< xmc pccard wait feature enable */
uint32_t delay_time_cr; /*!< xmc pccard cle to re delay */
uint32_t delay_time_ar; /*!< xmc pccard ale to re delay */
} xmc_pccard_init_type;
/**
* @brief xmc controller
*/
typedef struct
{
/**
* @brief xmc bk1ctrl register, offset:0x00+0x08*(x-1) x= 1...4
* @brief xmc bank1 bk1ctrl register, offset:0x00+0x08*(x-1) x= 1 or 4
*/
union
{
__IO uint32_t bk1ctrl[8];
__IO uint32_t bk1ctrl;
struct
{
{
__IO uint32_t en : 1; /* [0] */
__IO uint32_t admuxen : 1; /* [1] */
__IO uint32_t dev : 2; /* [3:2] */
__IO uint32_t dev : 2; /* [3:2] */
__IO uint32_t extmdbw : 2; /* [5:4] */
__IO uint32_t noren : 1; /* [6] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t syncben : 1; /* [8] */
__IO uint32_t nwpol : 1; /* [9] */
__IO uint32_t nwpol : 1; /* [9] */
__IO uint32_t wrapen : 1; /* [10] */
__IO uint32_t nwtcfg : 1; /* [11] */
__IO uint32_t wen : 1; /* [12] */
__IO uint32_t nwsen : 1; /* [13] */
__IO uint32_t rwtd : 1; /* [14] */
__IO uint32_t nwasen : 1; /* [15] */
__IO uint32_t rwtd : 1; /* [14] */
__IO uint32_t nwasen : 1; /* [15] */
__IO uint32_t crpgs : 3; /* [18:16] */
__IO uint32_t mwmc : 1; /* [19] */
__IO uint32_t mwmc : 1; /* [19] */
__IO uint32_t reserved2 : 12;/* [31:20] */
} bk1ctrl_bit[8];
};
} xmc_bank1_type;
} bk1ctrl_bit;
};
/**
* @brief xmc bank1e
*/
typedef struct
{
/**
* @brief xmc bk1tmgwr register, offset:0x104+0x08*(x-1) x= 1...4
* @brief xmc bank1 bk1tmg register, offset:0x04+0x08*(x-1) x= 1 or 4
*/
union
{
__IO uint32_t bk1tmgwr[7];
__IO uint32_t bk1tmg;
struct
{
{
__IO uint32_t addrst : 4; /* [3:0] */
__IO uint32_t addrht : 4; /* [7:4] */
__IO uint32_t dtst : 8; /* [15:8] */
__IO uint32_t dtst : 8; /* [15:8] */
__IO uint32_t buslat : 4; /* [19:16] */
__IO uint32_t clkpsc : 4; /* [23:20] */
__IO uint32_t dtlat : 4; /* [27:24] */
__IO uint32_t asyncm : 2; /* [29:28] */
__IO uint32_t asyncm : 2; /* [29:28] */
__IO uint32_t reserved1 : 2; /* [31:30] */
} bk1tmgwr_bit[7];
};
} xmc_bank1_ext_type;
} bk1tmg_bit;
};
} xmc_bank1_ctrl_tmg_reg_type;
/**
* @brief xmc bank1h
*/
typedef struct
{
/**
* @brief xmc bk1ext register, offset:0x220+0x08*(x-1) x= 1...4
/**
* @brief xmc bank1 bk1tmgwr register, offset:0x104+0x08*(x-1) x= 1 or 4
*/
union
{
__IO uint32_t bk1ext[4];
__IO uint32_t bk1tmgwr;
struct
{
__IO uint32_t buslatw2w : 8; /* [7:0] */
__IO uint32_t buslatr2r : 8; /* [15:8] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} bk1ext_bit[4];
};
} xmc_bank1_hide_type;
{
__IO uint32_t addrst : 4; /* [3:0] */
__IO uint32_t addrht : 4; /* [7:4] */
__IO uint32_t dtst : 8; /* [15:8] */
__IO uint32_t buslat : 4; /* [19:16] */
__IO uint32_t reserved1 : 8; /* [27:20] */
__IO uint32_t asyncm : 2; /* [29:28] */
__IO uint32_t reserved2 : 2; /* [31:30] */
} bk1tmgwr_bit;
};
/**
* @brief xmc bank1 reserved register
*/
__IO uint32_t reserved1;
} xmc_bank1_tmgwr_reg_type;
/**
* @brief xmc bank2
* @brief xmc bank1 registers
*/
typedef struct
{
/**
* @brief xmc bk2ctrl register, offset:0x40+0x20*(x-1) x=2
* @brief xmc bank1 ctrl and tmg register, offset:0x00~0x1C
*/
xmc_bank1_ctrl_tmg_reg_type ctrl_tmg_group[4];
/**
* @brief xmc bank1 reserved register, offset:0x20~0x100
*/
__IO uint32_t reserved1[57];
/**
* @brief xmc bank1 tmgwr register, offset:0x104~0x11C
*/
xmc_bank1_tmgwr_reg_type tmgwr_group[4];
/**
* @brief xmc bank1 reserved register, offset:0x120~0x21C
*/
__IO uint32_t reserved2[64];
/**
* @brief xmc bank1 ext register, offset:0x220~0x22C
*/
union
{
__IO uint32_t ext[4];
struct
{
__IO uint32_t buslatw2w : 8; /* [7:0] */
__IO uint32_t buslatr2r : 8; /* [15:8] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} ext_bit[4];
};
} xmc_bank1_type;
/**
* @brief xmc bank2 registers
*/
typedef struct
{
/**
* @brief xmc bk2ctrl register, offset:0x60
*/
union
{
__IO uint32_t bk2ctrl;
struct
{
{
__IO uint32_t reserved1 : 1; /* [0] */
__IO uint32_t nwen : 1; /* [1] */
__IO uint32_t nwen : 1; /* [1] */
__IO uint32_t en : 1; /* [2] */
__IO uint32_t dev : 1; /* [3] */
__IO uint32_t extmdbw : 2; /* [5:4] */
__IO uint32_t dev : 1; /* [3] */
__IO uint32_t extmdbw : 2; /* [5:4] */
__IO uint32_t eccen : 1; /* [6] */
__IO uint32_t reserved2 : 2; /* [8:7] */
__IO uint32_t tcr : 4; /* [12:9] */
__IO uint32_t reserved2 : 2; /* [8:7] */
__IO uint32_t tcr : 4; /* [12:9] */
__IO uint32_t tar : 4; /* [16:13] */
__IO uint32_t eccpgs : 3; /* [19:17] */
__IO uint32_t eccpgs : 3; /* [19:17] */
__IO uint32_t reserved3 : 12;/* [31:20] */
} bk2ctrl_bit;
};
};
/**
* @brief xmc bk2sts register, offset:0x44+0x20*(x-1) x=2
*/
* @brief xmc bk2is register, offset:0x64
*/
union
{
__IO uint32_t bk2sts;
__IO uint32_t bk2is;
struct
{
{
__IO uint32_t res : 1; /* [0] */
__IO uint32_t hls : 1; /* [1] */
__IO uint32_t fes : 1; /* [2] */
__IO uint32_t reien : 1; /* [3] */
__IO uint32_t hlien : 1; /* [4] */
__IO uint32_t feien : 1; /* [5] */
__IO uint32_t fifoe : 1; /* [6] */
__IO uint32_t fifoe : 1; /* [6] */
__IO uint32_t reserved1 : 25;/* [31:7] */
} bk2sts_bit;
};
} bk2is_bit;
};
/**
* @brief xmc bk2tmgmem register, offset:0x48+0x20*(x-1) x=2
*/
* @brief xmc bk2tmgmem register, offset:0x68
*/
union
{
__IO uint32_t bk2tmgmem;
struct
{
{
__IO uint32_t cmst : 8; /* [7:0] */
__IO uint32_t cmwt : 8; /* [15:8] */
__IO uint32_t cmht : 8; /* [23:16] */
__IO uint32_t cmwt : 8; /* [15:8] */
__IO uint32_t cmht : 8; /* [23:16] */
__IO uint32_t cmdhizt : 8; /* [31:24] */
} bk2tmgmem_bit;
};
};
/**
* @brief xmc bk2tmgatt register, offset:0x4C+0x20*(x-1) x=2
*/
* @brief xmc bk2tmgatt register, offset:0x6C
*/
union
{
__IO uint32_t bk2tmgatt;
struct
{
{
__IO uint32_t amst : 8; /* [7:0] */
__IO uint32_t amwt : 8; /* [15:8] */
__IO uint32_t amht : 8; /* [23:16] */
__IO uint32_t amwt : 8; /* [15:8] */
__IO uint32_t amht : 8; /* [23:16] */
__IO uint32_t amdhizt : 8; /* [31:24] */
} bk2tmgatt_bit;
};
};
/**
* @brief xmc reserved register
*/
uint32_t reserved;
* @brief xmc reserved register, offset:0x70
*/
__IO uint32_t reserved1;
/**
* @brief xmc bk2ecc register, offset:0x54+0x20*(x-1) x=2
*/
* @brief xmc bk2ecc register, offset:0x74
*/
union
{
__IO uint32_t bk2ecc;
struct
{
{
__IO uint32_t ecc : 32; /* [31:0] */
} bk2ecc_bit;
};
};
} xmc_bank2_type;
/**
* @brief xmc bank3
*/
typedef struct
{
/**
* @brief xmc bk3ctrl register, offset:0x40+0x20*(x-1) x=3
*/
union
{
__IO uint32_t bk3ctrl;
struct
{
__IO uint32_t reserved1 : 1; /* [0] */
__IO uint32_t nwen : 1; /* [1] */
__IO uint32_t en : 1; /* [2] */
__IO uint32_t dev : 1; /* [3] */
__IO uint32_t extmdbw : 2; /* [5:4] */
__IO uint32_t eccen : 1; /* [6] */
__IO uint32_t reserved2 : 2; /* [8:7] */
__IO uint32_t tcr : 4; /* [12:9] */
__IO uint32_t tar : 4; /* [16:13] */
__IO uint32_t eccpgs : 3; /* [19:17] */
__IO uint32_t reserved3 : 12;/* [31:20] */
} bk3ctrl_bit;
};
/**
* @brief xmc bk3sts register, offset:0x44+0x20*(x-1) x=3
*/
union
{
__IO uint32_t bk3sts;
struct
{
__IO uint32_t res : 1; /* [0] */
__IO uint32_t hls : 1; /* [1] */
__IO uint32_t fes : 1; /* [2] */
__IO uint32_t reien : 1; /* [3] */
__IO uint32_t hlien : 1; /* [4] */
__IO uint32_t feien : 1; /* [5] */
__IO uint32_t fifoe : 1; /* [6] */
__IO uint32_t reserved1 : 25;/* [31:7] */
} bk3sts_bit;
};
/**
* @brief xmc bk3tmgmem register, offset:0x48+0x20*(x-1) x=3
*/
union
{
__IO uint32_t bk3tmgmem;
struct
{
__IO uint32_t cmst : 8; /* [7:0] */
__IO uint32_t cmwt : 8; /* [15:8] */
__IO uint32_t cmht : 8; /* [23:16] */
__IO uint32_t cmdhizt : 8; /* [31:24] */
} bk3tmgmem_bit;
};
/**
* @brief xmc bk3tmgatt register, offset:0x4C+0x20*(x-1) x=3
*/
union
{
__IO uint32_t bk3tmgatt;
struct
{
__IO uint32_t amst : 8; /* [7:0] */
__IO uint32_t amwt : 8; /* [15:8] */
__IO uint32_t amht : 8; /* [23:16] */
__IO uint32_t amdhizt : 8; /* [31:24] */
} bk3tmgatt_bit;
};
/**
* @brief xmc reserved register
*/
uint32_t reserved;
/**
* @brief xmc bk3ecc register, offset:0x54+0x20*(x-1) x=3
*/
union
{
__IO uint32_t bk3ecc;
struct
{
__IO uint32_t ecc : 32; /* [31:0] */
} bk3ecc_bit;
};
} xmc_bank3_type;
/**
* @brief xmc bank4
*/
typedef struct
{
/**
* @brief xmc bk4ctrl register, offset:0x40+0x20*(x-1) x=4
*/
union
{
__IO uint32_t bk4ctrl;
struct
{
__IO uint32_t reserved1 : 1; /* [0] */
__IO uint32_t nwen : 1; /* [1] */
__IO uint32_t en : 1; /* [2] */
__IO uint32_t dev : 1; /* [3] */
__IO uint32_t extmdbw : 2; /* [5:4] */
__IO uint32_t eccen : 1; /* [6] */
__IO uint32_t reserved2 : 2; /* [8:7] */
__IO uint32_t tcr : 4; /* [12:9] */
__IO uint32_t tar : 4; /* [16:13] */
__IO uint32_t eccpgs : 3; /* [19:17] */
__IO uint32_t reserved3 : 12;/* [31:20] */
} bk4ctrl_bit;
};
/**
* @brief xmc bk4sts register, offset:0x44+0x20*(x-1) x=4
*/
union
{
__IO uint32_t bk4sts;
struct
{
__IO uint32_t res : 1; /* [0] */
__IO uint32_t hls : 1; /* [1] */
__IO uint32_t fes : 1; /* [2] */
__IO uint32_t reien : 1; /* [3] */
__IO uint32_t hlien : 1; /* [4] */
__IO uint32_t feien : 1; /* [5] */
__IO uint32_t fifoe : 1; /* [6] */
__IO uint32_t reserved1 : 25;/* [31:7] */
} bk4sts_bit;
};
/**
* @brief xmc bk4tmgmem register, offset:0x48+0x20*(x-1) x=4
*/
union
{
__IO uint32_t bk4tmgmem;
struct
{
__IO uint32_t cmst : 8; /* [7:0] */
__IO uint32_t cmwt : 8; /* [15:8] */
__IO uint32_t cmht : 8; /* [23:16] */
__IO uint32_t cmdhizt : 8; /* [31:24] */
} bk4tmgmem_bit;
};
/**
* @brief xmc bk4tmgatt register, offset:0x4C+0x20*(x-1) x=4
*/
union
{
__IO uint32_t bk4tmgatt;
struct
{
__IO uint32_t amst : 8; /* [7:0] */
__IO uint32_t amwt : 8; /* [15:8] */
__IO uint32_t amht : 8; /* [23:16] */
__IO uint32_t amdhizt : 8; /* [31:24] */
} bk4tmgatt_bit;
};
/**
* @brief xmc bk4tmgio register, offset:0xB0
*/
union
{
__IO uint32_t bk4tmgio;
struct
{
__IO uint32_t iost : 8; /* [7:0] */
__IO uint32_t iowt : 8; /* [15:8] */
__IO uint32_t ioht : 8; /* [23:16] */
__IO uint32_t iohizt : 8; /* [31:24] */
} bk4tmgio_bit;
};
} xmc_bank4_type;
/**
* @}
*/
#define XMC_BANK1 ((xmc_bank1_type *) XMC_BANK1_REG_BASE)
#define XMC_BANK1E ((xmc_bank1_ext_type *) XMC_BANK1E_REG_BASE)
#define XMC_BANK1H ((xmc_bank1_hide_type *) XMC_BANK1E_H_BASE)
#define XMC_BANK2 ((xmc_bank2_type *) XMC_BANK2_REG_BASE)
#define XMC_BANK3 ((xmc_bank3_type *) XMC_BANK3_REG_BASE)
#define XMC_BANK4 ((xmc_bank4_type *) XMC_BANK4_REG_BASE)
/** @defgroup XMC_exported_functions
* @{
*/
void xmc_nor_sram_reset(xmc_nor_sram_bank_type xmc_bank);
void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank);
void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct);
void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct);
void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct);
void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct);
void xmc_nor_sram_enable(xmc_nor_sram_bank_type xmc_bank, confirm_state new_state);
void xmc_ext_timing_config(xmc_subbank1_nor_sram_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
void xmc_nand_reset(xmc_nand_bank_type xmc_bank);
void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state);
void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
void xmc_nand_reset(xmc_class_bank_type xmc_bank);
void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct);
void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct);
void xmc_nand_timing_config(xmc_nand_timinginit_type* xmc_common_spacetiming_struct,
xmc_nand_timinginit_type* xmc_attribute_spacetiming_struct);
void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct);
void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct);
void xmc_nand_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state);
void xmc_nand_ecc_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state);
uint32_t xmc_ecc_get(xmc_nand_bank_type xmc_bank);
void xmc_interrupt_enable(xmc_nand_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state);
flag_status xmc_flag_status_get(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
void xmc_flag_clear(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
void xmc_pccard_reset(void);
void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct);
void xmc_pccard_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct);
void xmc_pccard_default_para_init(xmc_pccard_init_type* xmc_pccard_init_struct);
void xmc_pccard_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct);
void xmc_pccard_enable(confirm_state new_state);
void xmc_nand_timing_default_para_init(xmc_nand_timinginit_type* xmc_common_spacetiming_struct,
xmc_nand_timinginit_type* xmc_attribute_spacetiming_struct);
void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank);
void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state);
flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
/**
* @}

4
libraries/drivers/src/at32f403a_407_acc.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_acc.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the acc firmware library
**************************************************************************
* Copyright notice & Disclaimer

6
libraries/drivers/src/at32f403a_407_adc.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_adc.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the adc firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -931,7 +931,7 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag)
*/
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag)
{
adc_x->sts &= ~adc_flag;
adc_x->sts = ~adc_flag;
}
/**

4
libraries/drivers/src/at32f403a_407_bpr.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_bpr.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the bpr firmware library
**************************************************************************
* Copyright notice & Disclaimer

15
libraries/drivers/src/at32f403a_407_can.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_can.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the can firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -591,13 +591,14 @@ void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailb
switch (transmit_mailbox)
{
case CAN_TX_MAILBOX0:
can_x->tsts_bit.tm0ct = TRUE;
can_x->tsts = CAN_TSTS_TM0CT_VAL;
break;
case CAN_TX_MAILBOX1:
can_x->tsts_bit.tm1ct = TRUE;
can_x->tsts = CAN_TSTS_TM1CT_VAL;
break;
case CAN_TX_MAILBOX2:
can_x->tsts_bit.tm2ct = TRUE;
can_x->tsts = CAN_TSTS_TM2CT_VAL;
break;
default:
break;
@@ -668,10 +669,10 @@ void can_receive_fifo_release(can_type* can_x, can_rx_fifo_num_type fifo_number)
switch (fifo_number)
{
case CAN_RX_FIFO0:
can_x->rf0_bit.rf0r = TRUE;
can_x->rf0 = CAN_RF0_RF0R_VAL;
break;
case CAN_RX_FIFO1:
can_x->rf1_bit.rf1r = TRUE;
can_x->rf1 = CAN_RF1_RF1R_VAL;
break;
default:
break;

4
libraries/drivers/src/at32f403a_407_crc.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_crc.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the crc firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f403a_407_crm.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_crm.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the crm firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f403a_407_dac.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_dac.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the dac firmware library
**************************************************************************
* Copyright notice & Disclaimer

11
libraries/drivers/src/at32f403a_407_debug.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_debug.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the debug firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -48,7 +48,7 @@
*/
uint32_t debug_device_id_get(void)
{
return DEBUG->pid;
return DEBUGMCU->pid;
}
/**
@@ -72,14 +72,13 @@ uint32_t debug_device_id_get(void)
*/
void debug_periph_mode_set(uint32_t periph_debug_mode, confirm_state new_state)
{
if(new_state != FALSE)
{
DEBUG->ctrl |= periph_debug_mode;
DEBUGMCU->ctrl |= periph_debug_mode;
}
else
{
DEBUG->ctrl &= ~periph_debug_mode;
DEBUGMCU->ctrl &= ~periph_debug_mode;
}
}

9
libraries/drivers/src/at32f403a_407_dma.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_dma.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the dma firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -214,8 +214,7 @@ void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state
* - FLEX_CHANNEL4
* - FLEX_CHANNEL5
* - FLEX_CHANNEL6
* - FLEX_CHANNEL7
* - DMA2_CHANNEL8
* - FLEX_CHANNEL7
* @param flexible_request: every peripheral have specified hardware_id.
* this parameter can be one of the following values:
* - DMA_FLEXIBLE_ADC1 - DMA_FLEXIBLE_ADC3 - DMA_FLEXIBLE_DAC1 - DMA_FLEXIBLE_DAC2
@@ -351,7 +350,7 @@ void dma_flag_clear(uint32_t dmax_flag)
{
if(dmax_flag > 0x10000000)
{
DMA2->clr = dmax_flag;
DMA2->clr = (uint32_t)(dmax_flag & 0x0FFFFFFF);
}
else
{

4
libraries/drivers/src/at32f403a_407_emac.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_emac.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the emac firmware library
**************************************************************************
* Copyright notice & Disclaimer

6
libraries/drivers/src/at32f403a_407_exint.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_exint.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the exint firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -52,7 +52,7 @@ void exint_reset(void)
EXINT->polcfg1 = 0x00000000;
EXINT->polcfg2 = 0x00000000;
EXINT->evten = 0x00000000;
EXINT->intsts = 0x007FFFFF;
EXINT->intsts = 0x000FFFFF;
}
/**

4
libraries/drivers/src/at32f403a_407_flash.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_flash.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the flash firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f403a_407_gpio.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_gpio.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the gpio firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f403a_407_i2c.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_i2c.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the i2c firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f403a_407_misc.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_misc.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the misc firmware library
**************************************************************************
* Copyright notice & Disclaimer

18
libraries/drivers/src/at32f403a_407_pwc.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_pwc.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the pwc firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -94,15 +94,25 @@ void pwc_power_voltage_monitor_enable(confirm_state new_state)
/**
* @brief enable or disable pwc standby wakeup pin
* @param pin_num: choose the wakeup pin.
* this parameter can be be any combination of the following values:
* - PWC_WAKEUP_PIN_1
* @param new_state: new state of the standby wakeup pin.
* this parameter can be one of the following values:
* - TRUE <wakeup pin is used for wake up cpu from standby mode>
* - FALSE <wakeup pin is used for general purpose I/O>
* @retval none
*/
void pwc_wakeup_pin_enable(confirm_state new_state)
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state)
{
PWC->ctrlsts_bit.swpen = new_state;
if(new_state == TRUE)
{
PWC->ctrlsts |= pin_num;
}
else
{
PWC->ctrlsts &= ~pin_num;
}
}
/**

18
libraries/drivers/src/at32f403a_407_rtc.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_rtc.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the rtc firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -49,14 +49,14 @@
void rtc_counter_set(uint32_t counter_value)
{
/* enter rtc config mode */
RTC->ctrll_bit.cfgen = TRUE;
RTC->ctrll = 0x003F;
/* set rtc counter */
RTC->cnth_bit.cnt = (uint16_t)(counter_value >> 16);
RTC->cntl_bit.cnt = (uint16_t)(counter_value & 0x0000FFFF);
/* exit rtc config mode */
RTC->ctrll_bit.cfgen = FALSE;
RTC->ctrll = 0x000F;
}
/**
@@ -82,14 +82,14 @@ uint32_t rtc_counter_get(void)
void rtc_divider_set(uint32_t div_value)
{
/* enter rtc config mode */
RTC->ctrll_bit.cfgen = TRUE;
RTC->ctrll = 0x003F;
/* set rtc divider */
RTC->divh_bit.div = (uint16_t)(div_value >> 16);
RTC->divl_bit.div = (uint16_t)(div_value & 0x0000FFFF);
/* exit rtc config mode */
RTC->ctrll_bit.cfgen = FALSE;
RTC->ctrll = 0x000F;
}
/**
@@ -115,14 +115,14 @@ uint32_t rtc_divider_get(void)
void rtc_alarm_set(uint32_t alarm_value)
{
/* enter rtc config mode */
RTC->ctrll_bit.cfgen = TRUE;
RTC->ctrll = 0x003F;
/* set rtc alarm value */
RTC->tah_bit.ta = (uint16_t)(alarm_value >> 16);
RTC->tal_bit.ta = (uint16_t)(alarm_value & 0x0000FFFF);
/* exit rtc config mode */
RTC->ctrll_bit.cfgen = FALSE;
RTC->ctrll = 0x000F;
}
/**
@@ -186,7 +186,7 @@ flag_status rtc_flag_get(uint16_t flag)
*/
void rtc_flag_clear(uint16_t flag)
{
RTC->ctrll &= ~flag;
RTC->ctrll = ~(flag | 0x10) | (RTC->ctrll_bit.cfgen << 4);
}
/**

6
libraries/drivers/src/at32f403a_407_sdio.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_sdio.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the sdio firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -325,7 +325,7 @@ flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag)
*/
void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag)
{
sdio_x->intclr |= flag;
sdio_x->intclr = flag;
}
/**

8
libraries/drivers/src/at32f403a_407_spi.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_spi.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the spi firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -584,9 +584,9 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag)
{
volatile uint32_t temp = 0;
temp = temp;
if(spi_i2s_flag == SPI_CCERR_FLAG)
spi_x->sts_bit.ccerr = FALSE;
spi_x->sts = ~SPI_CCERR_FLAG;
else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG)
temp = REG32(&spi_x->dt);
else if(spi_i2s_flag == I2S_TUERR_FLAG)

6
libraries/drivers/src/at32f403a_407_tmr.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_tmr.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the tmr firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -1406,7 +1406,7 @@ flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag)
*/
void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag)
{
tmr_x->ists &= ~tmr_flag;
tmr_x->ists = ~tmr_flag;
}
/**

4
libraries/drivers/src/at32f403a_407_usart.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_usart.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the usart firmware library
**************************************************************************
* Copyright notice & Disclaimer

33
libraries/drivers/src/at32f403a_407_usb.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_usb.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains the functions for the usb firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -329,7 +329,11 @@ void usb_write_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes)
uint16_t *pbuf = (uint16_t *)pusr_buf;
for(n_index = 0; n_index < nhbytes; n_index ++)
{
#if defined (__ICCARM__) && (__VER__ < 7000000)
*d_addr++ = *(__packed uint16_t *)pbuf;
#else
*d_addr++ = __UNALIGNED_UINT16_READ(pbuf);
#endif
d_addr ++;
pbuf ++;
}
@@ -350,7 +354,11 @@ void usb_read_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes)
uint16_t *pbuf = (uint16_t *)pusr_buf;
for(n_index = 0; n_index < nhbytes; n_index ++)
{
#if defined (__ICCARM__) && (__VER__ < 7000000)
*(__packed uint16_t *)pbuf = *(__IO uint16_t *)s_addr ++;
#else
__UNALIGNED_UINT16_WRITE(pbuf, *(__IO uint16_t *)s_addr ++);
#endif
s_addr ++;
pbuf ++;
}
@@ -517,6 +525,27 @@ flag_status usb_flag_get(usbd_type *usbx, uint16_t flag)
return status;
}
/**
* @brief clear flag of usb.
* @param usbx: select the usb peripheral
* @param flag: select the usb flag
* this parameter can be one of the following values:
* - USB_INOUT_FLAG
* - USB_LSOF_FLAG
* - USB_SOF_FLAG
* - USB_RST_FLAG
* - USB_SP_FLAG
* - USB_WK_FLAG
* - USB_BE_FLAG
* - USB_UCFOR_FLAG
* - USB_TC_FLAG
* @retval none
*/
void usb_flag_clear(usbd_type *usbx, uint16_t flag)
{
usbx->intsts = ~flag;
}
/**
* @}
*/

4
libraries/drivers/src/at32f403a_407_wdt.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_wdt.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the wdt firmware library
**************************************************************************
* Copyright notice & Disclaimer

6
libraries/drivers/src/at32f403a_407_wwdt.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_wwdt.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the wwdt firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -73,7 +73,7 @@ void wwdt_divider_set(wwdt_division_type division)
*/
void wwdt_flag_clear(void)
{
WWDT->sts_bit.rldf = FALSE;
WWDT->sts = 0;
}
/**

320
libraries/drivers/src/at32f403a_407_xmc.c
View File

@@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f403a_407_xmc.c
* @version v2.0.4
* @date 2021-11-26
* @version v2.0.6
* @date 2021-12-31
* @brief contains all the functions for the xmc firmware library
**************************************************************************
* Copyright notice & Disclaimer
@@ -43,28 +43,26 @@
/**
* @brief xmc nor or sram registers reset
* @param xmc_bank
* @param xmc_subbank
* this parameter can be one of the following values:
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM2
* - XMC_BANK1_NOR_SRAM3
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM4
* @retval none
*/
void xmc_nor_sram_reset(xmc_nor_sram_bank_type xmc_bank)
void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank)
{
/* XMC_BANK1_NORSRAM1 */
if(xmc_bank == XMC_BANK1_NOR_SRAM1)
if(xmc_subbank == XMC_BANK1_NOR_SRAM1)
{
XMC_BANK1->bk1ctrl[xmc_bank] = 0x000030DB;
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030DB;
}
/* XMC_BANK1_NORSRAM2, XMC_BANK1_NORSRAM3 or XMC_BANK1_NORSRAM4 */
else
{
XMC_BANK1->bk1ctrl[xmc_bank] = 0x000030D2;
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030D2;
}
XMC_BANK1->bk1ctrl[xmc_bank + 1] = 0x0FFFFFFF;
XMC_BANK1E->bk1tmgwr[xmc_bank] = 0x0FFFFFFF;
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1tmg = 0x0FFFFFFF;
XMC_BANK1->tmgwr_group[xmc_subbank].bk1tmgwr = 0x0FFFFFFF;
}
/**
@@ -78,7 +76,7 @@ void xmc_nor_sram_reset(xmc_nor_sram_bank_type xmc_bank)
void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct)
{
/* bank1 nor/sram control register configuration */
XMC_BANK1->bk1ctrl[xmc_norsram_init_struct->bank] =
XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl =
(uint32_t)xmc_norsram_init_struct->data_addr_multiplex |
xmc_norsram_init_struct->device |
xmc_norsram_init_struct->bus_type |
@@ -95,7 +93,7 @@ void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct)
/* if nor flash device */
if(xmc_norsram_init_struct->device == XMC_DEVICE_NOR)
{
XMC_BANK1->bk1ctrl_bit[xmc_norsram_init_struct->bank].noren = 0x1;
XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl_bit.noren = 0x1;
}
}
@@ -114,7 +112,7 @@ void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_stru
xmc_norsram_timing_init_type* xmc_w_timing_struct)
{
/* bank1 nor/sram timing register configuration */
XMC_BANK1->bk1ctrl[xmc_rw_timing_struct->bank + 1] =
XMC_BANK1->ctrl_tmg_group[xmc_rw_timing_struct->subbank].bk1tmg =
(uint32_t)xmc_rw_timing_struct->addr_setup_time |
(xmc_rw_timing_struct->addr_hold_time << 4) |
(xmc_rw_timing_struct->data_setup_time << 8) |
@@ -126,7 +124,7 @@ void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_stru
/* bank1 nor/sram timing register for write configuration, if extended mode is used */
if(xmc_rw_timing_struct->write_timing_enable == XMC_WRITE_TIMING_ENABLE)
{
XMC_BANK1E->bk1tmgwr[xmc_w_timing_struct->bank] =
XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr =
(uint32_t)xmc_w_timing_struct->addr_setup_time |
(xmc_w_timing_struct->addr_hold_time << 4) |
(xmc_w_timing_struct->data_setup_time << 8) |
@@ -137,7 +135,7 @@ void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_stru
}
else
{
XMC_BANK1E->bk1tmgwr[xmc_w_timing_struct->bank] = 0x0FFFFFFF;
XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr = 0x0FFFFFFF;
}
}
@@ -150,7 +148,7 @@ void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_stru
void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct)
{
/* reset nor/sram init structure parameters values */
xmc_nor_sram_init_struct->bank = XMC_BANK1_NOR_SRAM1;
xmc_nor_sram_init_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_nor_sram_init_struct->data_addr_multiplex = XMC_DATA_ADDR_MUX_ENABLE;
xmc_nor_sram_init_struct->device = XMC_DEVICE_SRAM;
xmc_nor_sram_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
@@ -176,7 +174,7 @@ void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_stru
void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct)
{
xmc_rw_timing_struct->bank = XMC_BANK1_NOR_SRAM1;
xmc_rw_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_rw_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
xmc_rw_timing_struct->addr_setup_time = 0xF;
xmc_rw_timing_struct->addr_hold_time = 0xF;
@@ -185,7 +183,7 @@ void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_t
xmc_rw_timing_struct->clk_psc = 0xF;
xmc_rw_timing_struct->data_latency_time = 0xF;
xmc_rw_timing_struct->mode = XMC_ACCESS_MODE_A;
xmc_w_timing_struct->bank = XMC_BANK1_NOR_SRAM1;
xmc_w_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_w_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
xmc_w_timing_struct->addr_setup_time = 0xF;
xmc_w_timing_struct->addr_hold_time = 0xF;
@@ -198,64 +196,51 @@ void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_t
/**
* @brief enable or disable the specified nor/sram memory bank.
* @param xmc_bank
* @param xmc_subbank
* this parameter can be one of the following values:
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM2
* - XMC_BANK1_NOR_SRAM3
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM4
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nor_sram_enable(xmc_nor_sram_bank_type xmc_bank, confirm_state new_state)
void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state)
{
XMC_BANK1->bk1ctrl_bit[xmc_bank].en = new_state;
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl_bit.en = new_state;
}
/**
* @brief config the bus turnaround phase.
* @param xmc_sub_bank
* this parameter can be one of the following values:
* - XMC_SUBBANK1_NOR_SRAM1
* - XMC_SUBBANK1_NOR_SRAM2
* - XMC_SUBBANK1_NOR_SRAM3
* - XMC_SUBBANK1_NOR_SRAM4
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM4
* @param w2w_timing :write timing
* @param r2r_timing :read timing
* @retval none
*/
void xmc_ext_timing_config(xmc_subbank1_nor_sram_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
{
XMC_BANK1H->bk1ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8;
XMC_BANK1H->bk1ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;
XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8;
XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;
}
/**
* @brief xmc nand flash registers reset
* @param xmc_bank
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* - XMC_BANK2_NAND
* @retval none
*/
void xmc_nand_reset(xmc_nand_bank_type xmc_bank)
void xmc_nand_reset(xmc_class_bank_type xmc_bank)
{
/* set the XMC_BANK2_NAND registers to their reset values */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl = 0x00000018;
XMC_BANK2->bk2sts = 0x00000040;
XMC_BANK2->bk2is = 0x00000040;
XMC_BANK2->bk2tmgatt = 0xFCFCFCFC;
XMC_BANK2->bk2tmgmem = 0xFCFCFCFC;
}
/* set the XMC_BANK3_NAND registers to their reset values */
else
{
XMC_BANK3->bk3ctrl = 0x00000018;
XMC_BANK3->bk3sts = 0x00000040;
XMC_BANK3->bk3tmgatt = 0xFCFCFCFC;
XMC_BANK3->bk3tmgmem = 0xFCFCFCFC;
}
}
/**
@@ -284,26 +269,21 @@ void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct)
{
XMC_BANK2->bk2ctrl = tempctrl;
}
/* xmc_bank3_nand registers configuration */
else
{
XMC_BANK3->bk3ctrl = tempctrl;
}
}
/**
* @brief initialize the xmc nand banks according to the specified
* parameters in the xmc_nandinitstruct.
* @param xmc_regular_spacetiming_struct : pointer to a xmc_nand_pccard_timinginit_type
* @param xmc_regular_spacetiming_struct : pointer to a xmc_nand_timinginit_type
* structure that contains the configuration information for the xmc
* nand specified banks.
* @param xmc_special_spacetiming_struct : pointer to a xmc_nand_pccard_timinginit_type
* @param xmc_special_spacetiming_struct : pointer to a xmc_nand_timinginit_type
* structure that contains the configuration information for the xmc
* nand specified banks.
* @retval none
*/
void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct)
void xmc_nand_timing_config(xmc_nand_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_timinginit_type* xmc_special_spacetiming_struct)
{
uint32_t tempmem = 0x0, tempatt = 0x0;
@@ -319,16 +299,11 @@ void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spaceti
(xmc_special_spacetiming_struct->mem_hold_time << 16) |
(xmc_special_spacetiming_struct->mem_hiz_time << 24);
/* xmc_bank2_nand registers configuration */
if(xmc_regular_spacetiming_struct->nand_bank == XMC_BANK2_NAND)
if(xmc_regular_spacetiming_struct->class_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2tmgatt = tempatt;
XMC_BANK2->bk2tmgmem = tempmem;
}
else
{
XMC_BANK3->bk3tmgatt = tempatt;
XMC_BANK3->bk3tmgmem = tempmem;
}
}
/**
@@ -351,21 +326,21 @@ void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct)
/**
* @brief fill each xmc_common_spacetiming_struct and xmc_attribute_spacetiming_struct member with its default value.
* @param xmc_common_spacetiming_struct: pointer to a xmc_nand_pccard_timinginit_type
* @param xmc_common_spacetiming_struct: pointer to a xmc_nand_timinginit_type
* structure which will be initialized.
* @param xmc_special_spacetiming_struct: pointer to a xmc_nand_pccard_timinginit_type
* @param xmc_special_spacetiming_struct: pointer to a xmc_nand_timinginit_type
* structure which will be initialized.
* @retval none
*/
void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct)
void xmc_nand_timing_default_para_init(xmc_nand_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_timinginit_type* xmc_special_spacetiming_struct)
{
xmc_regular_spacetiming_struct->nand_bank = XMC_BANK2_NAND;
xmc_regular_spacetiming_struct->class_bank = XMC_BANK2_NAND;
xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
xmc_special_spacetiming_struct->nand_bank = XMC_BANK2_NAND;
xmc_special_spacetiming_struct->class_bank = XMC_BANK2_NAND;
xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
@@ -377,22 +352,16 @@ void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regu
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nand_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state)
void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
{
/* enable or disable the nand bank2 by setting the en bit in the bk2ctrl register */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl_bit.en = new_state;
}
/* enable or disable the nand bank3 by setting the en bit in the bk3ctrl register */
else
{
XMC_BANK3->bk3ctrl_bit.en = new_state;
}
}
/**
@@ -400,22 +369,16 @@ void xmc_nand_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state)
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nand_ecc_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state)
void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
{
/* enable the selected nand bank2 ecc function by setting the eccen bit in the bk2ctrl register */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl_bit.eccen = new_state;
}
/* enable the selected nand bank3 ecc function by setting the eccen bit in the bk3ctrl register */
else
{
XMC_BANK3->bk3ctrl_bit.eccen = new_state;
}
}
/**
@@ -423,10 +386,9 @@ void xmc_nand_ecc_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state)
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* @retval the error correction code (ecc) value.
*/
uint32_t xmc_ecc_get(xmc_nand_bank_type xmc_bank)
uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank)
{
uint32_t eccvaule = 0x0;
@@ -435,11 +397,7 @@ uint32_t xmc_ecc_get(xmc_nand_bank_type xmc_bank)
{
eccvaule = XMC_BANK2->bk2ecc;
}
/* get the bk3ecc register value */
else
{
eccvaule = XMC_BANK3->bk3ecc;
}
/* return the error correction code value */
return eccvaule;
}
@@ -449,8 +407,6 @@ uint32_t xmc_ecc_get(xmc_nand_bank_type xmc_bank)
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* - XMC_BANK4_PCCARD
* @param xmc_int: specifies the xmc interrupt sources to be enabled or disabled.
* this parameter can be any combination of the following values:
* - XMC_INT_RISING_EDGE
@@ -459,24 +415,14 @@ uint32_t xmc_ecc_get(xmc_nand_bank_type xmc_bank)
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_interrupt_enable(xmc_nand_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state)
void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state)
{
if(new_state != FALSE)
{
/* enable the selected xmc_bank2 interrupts */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2sts |= xmc_int;
}
/* enable the selected xmc_bank3 interrupts */
else if(xmc_bank == XMC_BANK3_NAND)
{
XMC_BANK3->bk3sts |= xmc_int;
}
/* enable the selected xmc_bank4 interrupts */
else
{
XMC_BANK4->bk4sts |= xmc_int;
XMC_BANK2->bk2is |= xmc_int;
}
}
else
@@ -484,18 +430,8 @@ void xmc_interrupt_enable(xmc_nand_bank_type xmc_bank, xmc_interrupt_sources_typ
/* disable the selected xmc_bank2 interrupts */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2sts &= ~xmc_int;
}
/* disable the selected xmc_bank3 interrupts */
else if(xmc_bank == XMC_BANK3_NAND)
{
XMC_BANK3->bk3sts &= ~xmc_int;
}
/* disable the selected xmc_bank4 interrupts */
else
{
XMC_BANK4->bk4sts &= ~xmc_int;
}
XMC_BANK2->bk2is &= ~xmc_int;
}
}
}
@@ -504,8 +440,6 @@ void xmc_interrupt_enable(xmc_nand_bank_type xmc_bank, xmc_interrupt_sources_typ
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* - XMC_BANK4_PCCARD
* @param xmc_flag: specifies the flag to check.
* this parameter can be any combination of the following values:
* - XMC_RISINGEDGE_FLAG
@@ -514,22 +448,14 @@ void xmc_interrupt_enable(xmc_nand_bank_type xmc_bank, xmc_interrupt_sources_typ
* - XMC_FEMPT_FLAG
* @retval none
*/
flag_status xmc_flag_status_get(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
{
flag_status status = RESET;
uint32_t temp = 0;
if(xmc_bank == XMC_BANK2_NAND)
{
temp = XMC_BANK2->bk2sts;
}
else if(xmc_bank == XMC_BANK3_NAND)
{
temp = XMC_BANK3->bk3sts;
}
else
{
temp = XMC_BANK4->bk4sts;
temp = XMC_BANK2->bk2is;
}
/* get the flag status */
if((temp & xmc_flag) == RESET)
@@ -549,8 +475,6 @@ flag_status xmc_flag_status_get(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* - XMC_BANK4_PCCARD
* @param xmc_flag: specifies the flag to check.
* this parameter can be any combination of the following values:
* - XMC_RISINGEDGE_FLAG
@@ -559,148 +483,14 @@ flag_status xmc_flag_status_get(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_
* - XMC_FEMPT_FLAG
* @retval none
*/
void xmc_flag_clear(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
{
__IO uint32_t int_state;
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2sts &= ~xmc_flag;
int_state = XMC_BANK2->bk2is & 0x38; /* keep interrupt state */
XMC_BANK2->bk2is = (~(xmc_flag | 0x38) | int_state);
}
else if(xmc_bank == XMC_BANK3_NAND)
{
XMC_BANK3->bk3sts &= ~xmc_flag;
}
else
{
XMC_BANK4->bk4sts &= ~xmc_flag;
}
}
/**
* @brief xmc pc card registers reset
* @param none
* @retval none
*/
void xmc_pccard_reset(void)
{
/* Set the XMC_Bank4 registers to their reset values */
XMC_BANK4->bk4ctrl = 0x00000018;
XMC_BANK4->bk4sts = 0x00000000;
XMC_BANK4->bk4tmgatt = 0xFCFCFCFC;
XMC_BANK4->bk4tmgio = 0xFCFCFCFC;
XMC_BANK4->bk4tmgmem = 0xFCFCFCFC;
}
/**
* @brief initialize the xmc pccard bank according to the specified
* parameters in the xmc_pccard_init_struct.
* @param xmc_pccard_init_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @retval none
*/
void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct)
{
/* set the bk4ctrl register value according to xmc_pccard_init_struct parameters */
XMC_BANK4->bk4ctrl = (uint32_t)xmc_pccard_init_struct->enable_wait |
XMC_BUSTYPE_16_BITS |
(xmc_pccard_init_struct->delay_time_cr << 9) |
(xmc_pccard_init_struct->delay_time_ar << 13);
}
/**
* @brief initialize the xmc pccard bank according to the specified
* parameters in the xmc_common_spacetiming_struct/xmc_attribute_spacetiming_struct
* and xmc_iospace_timing_struct.
* @param xmc_regular_spacetiming_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @param xmc_special_spacetiming_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @param xmc_iospace_timing_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @retval none
*/
void xmc_pccard_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct)
{
/* set bk4tmgmem register value according to xmc_regular_spacetiming_struct parameters */
XMC_BANK4->bk4tmgmem = (uint32_t)xmc_regular_spacetiming_struct->mem_setup_time |
(xmc_regular_spacetiming_struct->mem_waite_time << 8) |
(xmc_regular_spacetiming_struct->mem_hold_time << 16) |
(xmc_regular_spacetiming_struct->mem_hiz_time << 24);
/* Set bk4tmgatt register value according to xmc_special_spacetiming_struct parameters */
XMC_BANK4->bk4tmgatt = (uint32_t)xmc_special_spacetiming_struct->mem_setup_time |
(xmc_special_spacetiming_struct->mem_waite_time << 8) |
(xmc_special_spacetiming_struct->mem_hold_time << 16) |
(xmc_special_spacetiming_struct->mem_hiz_time << 24);
/* Set bk4tmgio register value according to xmc_iospace_timing_struct parameters */
XMC_BANK4->bk4tmgio = (uint32_t)xmc_iospace_timing_struct->mem_setup_time |
(xmc_iospace_timing_struct->mem_waite_time << 8) |
(xmc_iospace_timing_struct->mem_hold_time << 16) |
(xmc_iospace_timing_struct->mem_hiz_time << 24);
}
/**
* @brief fill each xmc_pccard_init_struct member with its default value.
* @param xmc_pccard_init_struct: pointer to a xmc_pccardinittype
* structure which will be initialized.
* @retval none
*/
void xmc_pccard_default_para_init(xmc_pccard_init_type* xmc_pccard_init_struct)
{
/* reset pccard init structure parameters values */
xmc_pccard_init_struct->enable_wait = XMC_WAIT_OPERATION_DISABLE;
xmc_pccard_init_struct->delay_time_ar = 0x0;
xmc_pccard_init_struct->delay_time_cr = 0x0;
}
/**
* @brief fill each xmc_common_spacetiming_struct/xmc_attribute_spacetiming_struct
* and xmc_iospace_timing_struct member with its default value.
* @param xmc_regular_spacetiming_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @param xmc_special_spacetiming_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @param xmc_iospace_timing_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @retval none
*/
void xmc_pccard_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct)
{
xmc_regular_spacetiming_struct->nand_bank = XMC_BANK4_PCCARD;
xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
xmc_special_spacetiming_struct->nand_bank = XMC_BANK4_PCCARD;
xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
xmc_special_spacetiming_struct->mem_hiz_time = 0xFC;
xmc_iospace_timing_struct->nand_bank = XMC_BANK4_PCCARD;
xmc_iospace_timing_struct->mem_hold_time = 0xFC;
xmc_iospace_timing_struct->mem_waite_time = 0xFC;
xmc_iospace_timing_struct->mem_setup_time = 0xFC;
xmc_iospace_timing_struct->mem_hiz_time = 0xFC;
}
/**
* @brief enable or disable the pccard memory bank.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_pccard_enable(confirm_state new_state)
{
/* enable the pccard bank4 by setting the en bit in the bk4ctrl register */
XMC_BANK4->bk4ctrl_bit.en = new_state;
}
/**