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update version to v2.1.7

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This commit is contained in:
Artery-MCU
2024-01-25 10:05:33 +08:00
parent bd2ef6c955
commit 7c74102117
188 changed files with 6156 additions and 518 deletions
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6
libraries/cmsis/cm4/device_support/at32f403a_407.h
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@@ -161,7 +161,7 @@ extern "C" {
*/
#define __AT32F403A_407_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F403A_407_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */
#define __AT32F403A_407_LIBRARY_VERSION_MINOR (0x06) /*!< [15:8] minor version */
#define __AT32F403A_407_LIBRARY_VERSION_MINOR (0x07) /*!< [15:8] minor version */
#define __AT32F403A_407_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F403A_407_LIBRARY_VERSION ((__AT32F403A_407_LIBRARY_VERSION_MAJOR << 24) | \
(__AT32F403A_407_LIBRARY_VERSION_MIDDLE << 16) | \
@@ -280,7 +280,7 @@ typedef enum IRQn
DMA2_Channel6_7_IRQn = 75, /*!< dma2 channel 6 and channel 7 global interrupt */
USART6_IRQn = 76, /*!< usart6 interrupt */
UART7_IRQn = 77, /*!< uart7 interrupt */
UART8_IRQn = 78, /*!< uart8 interrupt */
UART8_IRQn = 78 /*!< uart8 interrupt */
#endif
#if defined (AT32F407xx)
@@ -342,7 +342,7 @@ typedef enum IRQn
UART7_IRQn = 77, /*!< uart7 interrupt */
UART8_IRQn = 78, /*!< uart8 interrupt */
EMAC_IRQn = 79, /*!< emac interrupt */
EMAC_WKUP_IRQn = 80, /*!< emac wakeup interrupt */
EMAC_WKUP_IRQn = 80 /*!< emac wakeup interrupt */
#endif
} IRQn_Type;

BIN
libraries/drivers/ReleaseNotes_AT32F403A_407_Firmware_Library_Drivers.pdf
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Binary file not shown.

1
libraries/drivers/inc/at32f403a_407_dma.h
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@@ -525,6 +525,7 @@ void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, con
void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state);
void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request);
flag_status dma_flag_get(uint32_t dmax_flag);
flag_status dma_interrupt_flag_get(uint32_t dmax_flag);
void dma_flag_clear(uint32_t dmax_flag);
void dma_default_para_init(dma_init_type* dma_init_struct);
void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct);

34
libraries/drivers/inc/at32f403a_407_emac.h
View File

@@ -44,6 +44,7 @@ extern "C" {
*/
#define PHY_TIMEOUT (0x000FFFFF) /*!< timeout for phy response */
#define EMAC_USE_ENHANCED_DMA_DESCRIPTOR
/** @defgroup EMAC_smi_clock_border_definition
* @brief emac smi clock border
@@ -269,6 +270,15 @@ extern "C" {
#define EMAC_DMA_AIS_FLAG ((uint32_t)0x00008000) /*!< emac dma abnormal interrupt summary */
#define EMAC_DMA_NIS_FLAG ((uint32_t)0x00010000) /*!< emac dma normal interrupt summary */
/**
* @brief emac ptp time sign
*/
#define EMAC_PTP_POSITIVETIME ((uint32_t)0x00000000) /*!< Positive time value */
#define EMAC_PTP_NEGATIVETIME ((uint32_t)0x80000000) /*!< Negative time value */
#define EMAC_PTP_TI_FLAG ((uint32_t)0x00000004) /*!< Time Stamp Initialized */
#define EMAC_PTP_TU_FLAG ((uint32_t)0x00000008) /*!< Time Stamp Updated */
#define EMAC_PTP_ARU_FLAG ((uint32_t)0x00000020) /*!< Addend Register Updated */
/** @defgroup EMAC_exported_types
* @{
*/
@@ -343,9 +353,10 @@ typedef enum
*/
typedef enum
{
EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */
EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */
EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */
EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */
EMAC_CONTROL_FRAME_PASSING_ALL_EXCEPT_PAUSE = 0x01, /*!< pass all control frames to application except pause frame */
EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */
EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */
} emac_control_frames_filter_type;
/**
@@ -631,6 +642,10 @@ typedef struct {
uint32_t controlsize; /*!< control and buffer1, buffer2 lengths */
uint32_t buf1addr; /*!< buffer1 address pointer */
uint32_t buf2nextdescaddr; /*!< buffer2 or next descriptor address pointer */
uint32_t extendedstatus;
uint32_t reserved1;
uint32_t timestamp_l;
uint32_t timestamp_h;
} emac_dma_desc_type;
/**
@@ -889,7 +904,7 @@ typedef struct
__IO uint32_t reserved1 : 8; /* [16:23] */
__IO uint32_t mbc : 6; /* [24:29] */
__IO uint32_t sa : 1; /* [30] */
__IO uint32_t ae : 1; /* [31] */
__IO uint32_t ae : 1; /* [31] */
} a1h_bit;
};
@@ -1326,7 +1341,7 @@ typedef struct
__IO uint32_t swr : 1; /* [0] */
__IO uint32_t da : 1; /* [1] */
__IO uint32_t dsl : 5; /* [2:6] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t atds : 1; /* [7] */
__IO uint32_t pbl : 6; /* [8:13] */
__IO uint32_t pr : 2; /* [14:15] */
__IO uint32_t fb : 1; /* [16] */
@@ -1334,7 +1349,7 @@ typedef struct
__IO uint32_t usp : 1; /* [23] */
__IO uint32_t pblx8 : 1; /* [24] */
__IO uint32_t aab : 1; /* [25] */
__IO uint32_t reserved2 : 6; /* [26:31] */
__IO uint32_t reserved : 6; /* [26:31] */
} bm_bit;
};
@@ -1626,6 +1641,7 @@ void emac_address_filter_set(emac_address_type mac, emac_address_filter_type fil
uint32_t emac_received_packet_size_get(void);
uint32_t emac_dmarxdesc_frame_length_get(emac_dma_desc_type *dma_rx_desc);
void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, uint8_t *buff, uint32_t buffer_count);
void emac_ptp_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, emac_dma_desc_type *ptp_dma_desc_tab, uint8_t *buff, uint32_t buffer_count);
uint32_t emac_dma_descriptor_list_address_get(emac_dma_tx_rx_type transfer_type);
void emac_dma_rx_desc_interrupt_config(emac_dma_desc_type *dma_rx_desc, confirm_state new_state);
void emac_dma_para_init(emac_dma_config_type *control_para);
@@ -1648,6 +1664,7 @@ uint8_t emac_dma_missing_overflow_bit_get(void);
uint16_t emac_dma_application_missing_frame_get(void);
uint8_t emac_dma_fifo_overflow_bit_get(void);
uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_type);
void emac_dma_alternate_desc_size(confirm_state new_state);
void emac_mmc_counter_reset(void);
void emac_mmc_rollover_stop(confirm_state new_state);
void emac_mmc_reset_on_read_enable(confirm_state new_state);
@@ -1674,13 +1691,12 @@ void emac_ptp_snapshot_event_message_enable(confirm_state new_state);
void emac_ptp_snapshot_master_event_enable(confirm_state new_state);
void emac_ptp_clock_node_set(emac_ptp_clock_node_type node);
void emac_ptp_mac_address_filter_enable(confirm_state new_state);
flag_status emac_ptp_flag_get(uint32_t flag);
void emac_ptp_subsecond_increment_set(uint8_t value);
uint32_t emac_ptp_system_second_get(void);
uint32_t emac_ptp_system_subsecond_get(void);
confirm_state emac_ptp_system_time_sign_get(void);
void emac_ptp_system_second_set(uint32_t second);
void emac_ptp_system_subsecond_set(uint32_t subsecond);
void emac_ptp_system_time_sign_set(confirm_state sign);
void emac_ptp_system_time_set(uint32_t sign, uint32_t second, uint32_t subsecond);
void emac_ptp_timestamp_addend_set(uint32_t value);
void emac_ptp_target_second_set(uint32_t value);
void emac_ptp_target_nanosecond_set(uint32_t value);

2
libraries/drivers/inc/at32f403a_407_flash.h
View File

@@ -188,7 +188,7 @@ typedef enum
typedef enum
{
FLASH_SPIM_MODEL1 = 0x01, /*!< spim model 1 */
FLASH_SPIM_MODEL2 = 0x02, /*!< spim model 2 */
FLASH_SPIM_MODEL2 = 0x02 /*!< spim model 2 */
} flash_spim_model_type;
/**

46
libraries/drivers/src/at32f403a_407_dma.c
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@@ -278,6 +278,52 @@ void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_re
}
}
/**
* @brief get dma interrupt flag
* @param dmax_flag
* this parameter can be one of the following values:
* - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
* - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
* - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
* - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
* - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
* - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
* - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
* - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
* - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
* - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
* - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
* - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
* - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
* - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
* @retval state of dma flag
*/
flag_status dma_interrupt_flag_get(uint32_t dmax_flag)
{
flag_status status = RESET;
uint32_t temp = 0;
if(dmax_flag > 0x10000000)
{
temp = DMA2->sts;
}
else
{
temp = DMA1->sts;
}
if ((temp & dmax_flag) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief get dma flag
* @param dmax_flag

157
libraries/drivers/src/at32f403a_407_emac.c
View File

@@ -43,8 +43,10 @@
/**
* @brief global pointers on tx and rx descriptor used to track transmit and receive descriptors
*/
emac_dma_desc_type *dma_tx_desc_to_set;
emac_dma_desc_type *dma_rx_desc_to_get;
__IO emac_dma_desc_type *dma_tx_desc_to_set;
__IO emac_dma_desc_type *dma_rx_desc_to_get;
__IO emac_dma_desc_type *ptp_dma_tx_desc_to_set;
__IO emac_dma_desc_type *ptp_dma_rx_desc_to_get;
/* emac private function */
static void emac_delay(uint32_t delay);
@@ -523,6 +525,7 @@ void emac_broadcast_frames_disable(confirm_state new_state)
* @param condition: set what control frame can pass filter.
* this parameter can be one of the following values:
* - EMAC_CONTROL_FRAME_PASSING_NO
* - EMAC_CONTROL_FRAME_PASSING_ALL_EXCEPT_PAUSE
* - EMAC_CONTROL_FRAME_PASSING_ALL
* - EMAC_CONTROL_FRAME_PASSING_MATCH
* @retval none
@@ -982,6 +985,90 @@ void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, ema
}
}
/**
* @brief set transmit/receive descriptor list address
* @param transfer_type: it will be transmit or receive
* this parameter can be one of the following values:
* - EMAC_DMA_TRANSMIT
* - EMAC_DMA_RECEIVE
* @param dma_desc_tab: pointer on the first tx desc list
* @param buff: pointer on the first tx/rx buffer list
* @param buffer_count: number of the used Tx desc in the list
* @retval none
*/
void emac_ptp_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, emac_dma_desc_type *ptp_dma_desc_tab, uint8_t *buff, uint32_t buffer_count)
{
uint32_t i = 0;
emac_dma_desc_type *dma_descriptor;
switch(transfer_type)
{
case EMAC_DMA_TRANSMIT:
{
dma_tx_desc_to_set = dma_desc_tab;
ptp_dma_tx_desc_to_set = ptp_dma_desc_tab;
for(i = 0; i < buffer_count; i++)
{
dma_descriptor = dma_desc_tab + i;
dma_descriptor->status = EMAC_DMATXDESC_TCH | EMAC_DMATXDESC_TTSE;
dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]);
if(i < (buffer_count - 1))
{
dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1);
}
else
{
dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab;
}
(&ptp_dma_desc_tab[i])->buf1addr = dma_descriptor->buf1addr;
(&ptp_dma_desc_tab[i])->buf2nextdescaddr = dma_descriptor->buf2nextdescaddr;
}
(&ptp_dma_desc_tab[i-1])->status = (uint32_t) ptp_dma_desc_tab;
EMAC_DMA->tdladdr_bit.stl = (uint32_t) dma_desc_tab;
break;
}
case EMAC_DMA_RECEIVE:
{
dma_rx_desc_to_get = dma_desc_tab;
ptp_dma_rx_desc_to_get = ptp_dma_desc_tab;
for(i = 0; i < buffer_count; i++)
{
dma_descriptor = dma_desc_tab + i;
dma_descriptor->status = EMAC_DMARXDESC_OWN;
dma_descriptor->controlsize = EMAC_DMARXDESC_RCH | (uint32_t)EMAC_MAX_PACKET_LENGTH;
dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]);
if(i < (buffer_count - 1))
{
dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1);
}
else
{
dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab;
}
(&ptp_dma_desc_tab[i])->buf1addr = dma_descriptor->buf1addr;
(&ptp_dma_desc_tab[i])->buf2nextdescaddr = dma_descriptor->buf2nextdescaddr;
}
(&ptp_dma_desc_tab[i-1])->status = (uint32_t) ptp_dma_desc_tab;
EMAC_DMA->rdladdr_bit.srl = (uint32_t) dma_desc_tab;
break;
}
}
}
/**
* @brief enable or disable the specified dma rx descriptor receive interrupt
* @param dma_rx_desc: pointer on a rx desc.
@@ -1042,7 +1129,7 @@ uint32_t emac_received_packet_size_get(void)
((dma_rx_desc_to_get->status & EMAC_DMARXDESC_LS) != (uint32_t)RESET) &&
((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FS) != (uint32_t)RESET))
{
frame_length = emac_dmarxdesc_frame_length_get(dma_rx_desc_to_get);
frame_length = emac_dmarxdesc_frame_length_get((emac_dma_desc_type*) dma_rx_desc_to_get);
}
return frame_length;
@@ -1653,6 +1740,16 @@ uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_ty
return address;
}
/**
* @brief alternate dma descriptor size
* @param new_state: TRUE or FALSE
* @retval none
*/
void emac_dma_alternate_desc_size(confirm_state new_state)
{
EMAC_DMA->bm_bit.atds = new_state;
}
/**
* @brief reset all counter
* @param none
@@ -2032,6 +2129,27 @@ void emac_ptp_mac_address_filter_enable(confirm_state new_state)
EMAC_PTP->tsctrl_bit.emafpff = new_state;
}
/**
* @brief check whether the specified emac ptp flag is set or not.
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - EMAC_PTP_TI_FLAG: time stamp initialized flag
* - EMAC_PTP_TU_FLAG: time stamp updtated flag
* - EMAC_PTP_ARU_FLAG: transmit data buffer empty flag
* @retval the new state of usart_flag (SET or RESET).
*/
flag_status emac_ptp_flag_get(uint32_t flag)
{
if(EMAC_PTP->tsctrl & flag)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief set subsecond increment value
* @param value: add to subsecond value for every update
@@ -2082,42 +2200,19 @@ confirm_state emac_ptp_system_time_sign_get(void)
}
/**
* @brief set system time second
* @brief set system time
* @param sign: plus or minus
* @param second: system time second
* @retval none
*/
void emac_ptp_system_second_set(uint32_t second)
{
EMAC_PTP->tshud_bit.ts = second;
}
/**
* @brief set system time subsecond
* @param subsecond: system time subsecond
* @retval none
*/
void emac_ptp_system_subsecond_set(uint32_t subsecond)
void emac_ptp_system_time_set(uint32_t sign, uint32_t second, uint32_t subsecond)
{
EMAC_PTP->tslud_bit.ast = sign ? 1 : 0;
EMAC_PTP->tshud_bit.ts = second;
EMAC_PTP->tslud_bit.tss = subsecond;
}
/**
* @brief set system time sign
* @param sign: TRUE or FALSE.
* @retval none
*/
void emac_ptp_system_time_sign_set(confirm_state sign)
{
if(sign)
{
EMAC_PTP->tslud_bit.ast = 1;
}
else
{
EMAC_PTP->tslud_bit.ast = 0;
}
}
/**
* @brief set time stamp addend
* @param value: to achieve time synchronization

6
libraries/drivers/src/at32f403a_407_exint.c
View File

@@ -175,8 +175,10 @@ flag_status exint_flag_get(uint32_t exint_line)
flag_status exint_interrupt_flag_get(uint32_t exint_line)
{
flag_status status = RESET;
uint32_t exint_flag =0;
exint_flag = EXINT->intsts & exint_line & EXINT->inten;
uint32_t exint_flag = 0;
exint_flag = EXINT->intsts & exint_line;
exint_flag = exint_flag & EXINT->inten;
if((exint_flag != (uint16_t)RESET))
{
status = SET;

2
libraries/drivers/src/at32f403a_407_i2c.c
View File

@@ -641,7 +641,7 @@ flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag)
break;
case I2C_RDBF_FLAG:
case I2C_TDBE_FLAG:
iten = i2c_x->ctrl2_bit.dataien & i2c_x->ctrl2_bit.evtien;
iten = i2c_x->ctrl2_bit.dataien && i2c_x->ctrl2_bit.evtien;
break;
case I2C_BUSERR_FLAG:
case I2C_ARLOST_FLAG:

6
libraries/drivers/src/at32f403a_407_xmc.c
View File

@@ -487,17 +487,17 @@ flag_status xmc_interrupt_flag_status_get(xmc_class_bank_type xmc_bank, xmc_inte
switch(xmc_flag)
{
case XMC_RISINGEDGE_FLAG:
if(XMC_BANK2->bk2is_bit.reien & XMC_BANK2->bk2is_bit.res)
if(XMC_BANK2->bk2is_bit.reien && XMC_BANK2->bk2is_bit.res)
status = SET;
break;
case XMC_LEVEL_FLAG:
if(XMC_BANK2->bk2is_bit.feien & XMC_BANK2->bk2is_bit.fes)
if(XMC_BANK2->bk2is_bit.feien && XMC_BANK2->bk2is_bit.fes)
status = SET;
break;
case XMC_FALLINGEDGE_FLAG:
if(XMC_BANK2->bk2is_bit.hlien & XMC_BANK2->bk2is_bit.hls)
if(XMC_BANK2->bk2is_bit.hlien && XMC_BANK2->bk2is_bit.hls)
status = SET;
break;