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update version to v2.1.5

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Artery-MCU
2023-08-08 19:27:03 +08:00
parent 3bac77751d
commit 4dcec715e1
719 changed files with 231851 additions and 2580 deletions
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2
project/at_start_f403a/examples/acc/calibration/readme.txt
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@@ -7,4 +7,4 @@
this demo is based on the at-start board, in this demo, acc will calibration
hick when usb is connecting.
for more detailed information. please refer to the application note document AN0107.
for more detailed information. please refer to the application note document AN0107.

6
project/at_start_f403a/examples/acc/calibration/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

4
project/at_start_f403a/examples/acc/calibration/src/main.c
View File

@@ -158,11 +158,7 @@ void system_clock_config_for_acc(void)
/* reset crm */
crm_reset();
#ifdef SCLK_FROM_HICK
crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE);
#elif defined SCLK_FROM_HEXT
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
#endif
/* wait till hick is ready */
while(SET != crm_flag_get(CRM_HICK_STABLE_FLAG))

2
project/at_start_f403a/examples/adc/combine_mode_ordinary_simult/readme.txt
View File

@@ -11,4 +11,4 @@
- adc1_ordinary_valuetab[n][0] ---> (adc2_channel_7<<16) | adc1_channel_4
- adc1_ordinary_valuetab[n][1] ---> (adc2_channel_8<<16) | adc1_channel_5
- adc1_ordinary_valuetab[n][2] ---> (adc2_channel_9<<16) | adc1_channel_6
for more detailed information. please refer to the application note document AN0112.
for more detailed information. please refer to the application note document AN0112.

6
project/at_start_f403a/examples/adc/combine_mode_ordinary_simult/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/adc/current_vref_value_check/readme.txt
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@@ -9,4 +9,4 @@
the adc1 internal channel17 to check vref value.
the convert data as follow:
- adc1_ordinary_value ---> adc1_channel_17
for more detailed information. please refer to the application note document AN0112.
for more detailed information. please refer to the application note document AN0112.

6
project/at_start_f403a/examples/adc/current_vref_value_check/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/adc/exint_trigger_partitioned/readme.txt
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@@ -17,4 +17,4 @@
trigger source:
- ordinary --> exint line11(pc11)
- preempt --> exint line15(pa15)
for more detailed information. please refer to the application note document AN0112.
for more detailed information. please refer to the application note document AN0112.

6
project/at_start_f403a/examples/adc/exint_trigger_partitioned/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/adc/internal_temperature_sensor/readme.txt
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@@ -9,4 +9,4 @@
the internal_temperature_sensor.
the convert data as follow:
- adc1_ordinary_value ---> adc1_channel_16
for more detailed information. please refer to the application note document AN0112.
for more detailed information. please refer to the application note document AN0112.

6
project/at_start_f403a/examples/adc/internal_temperature_sensor/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/adc/repeat_conversion_loop_transfer/readme.txt
View File

@@ -11,4 +11,4 @@
- adc1_ordinary_valuetab[0] ---> adc1_channel_4
- adc1_ordinary_valuetab[1] ---> adc1_channel_5
- adc1_ordinary_valuetab[2] ---> adc1_channel_6
for more detailed information. please refer to the application note document AN0112.
for more detailed information. please refer to the application note document AN0112.

6
project/at_start_f403a/examples/adc/repeat_conversion_loop_transfer/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/adc/software_trigger_repeat/readme.txt
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@@ -11,4 +11,4 @@
- adc1_ordinary_valuetab[0] ---> adc1_channel_4
- adc1_ordinary_valuetab[1] ---> adc1_channel_5
- adc1_ordinary_valuetab[2] ---> adc1_channel_6
for more detailed information. please refer to the application note document AN0112.
for more detailed information. please refer to the application note document AN0112.

6
project/at_start_f403a/examples/adc/software_trigger_repeat/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/adc/tmr_trigger_automatic_preempted/readme.txt
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@@ -15,4 +15,4 @@
- adc1_preempt_valuetab[n][0] ---> adc1_channel_7
- adc1_preempt_valuetab[n][1] ---> adc1_channel_8
- adc1_preempt_valuetab[n][2] ---> adc1_channel_9
for more detailed information. please refer to the application note document AN0112.
for more detailed information. please refer to the application note document AN0112.

6
project/at_start_f403a/examples/adc/tmr_trigger_automatic_preempted/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/adc/triple_adc_synchro_trigger/readme.txt
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@@ -14,4 +14,4 @@
- adc3_ordinary_valuetab[n][0] ---> adc3_channel_10
- adc3_ordinary_valuetab[n][1] ---> adc3_channel_11
- adc3_ordinary_valuetab[n][2] ---> adc3_channel_12
for more detailed information. please refer to the application note document AN0112.
for more detailed information. please refer to the application note document AN0112.

6
project/at_start_f403a/examples/adc/triple_adc_synchro_trigger/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/adc/voltage_monitoring/readme.txt
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@@ -12,4 +12,4 @@
- adc1_ordinary_valuetab[1] ---> adc1_channel_5
- adc1_ordinary_valuetab[2] ---> adc1_channel_6
the voltage monitoring channel is: adc1_channel_5
for more detailed information. please refer to the application note document AN0112.
for more detailed information. please refer to the application note document AN0112.

6
project/at_start_f403a/examples/adc/voltage_monitoring/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/bpr/bpr_data/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/bpr/tamper/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/can/communication_mode/readme.txt
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@@ -13,4 +13,4 @@
- can tx ---> pb9
- can rx ---> pb8
for more detailed information. please refer to the application note document AN0095.
for more detailed information. please refer to the application note document AN0095.

6
project/at_start_f403a/examples/can/communication_mode/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/can/filter/readme.txt
View File

@@ -14,4 +14,4 @@
- can tx ---> pb9
- can rx ---> pb8
for more detailed information. please refer to the application note document AN0095.
for more detailed information. please refer to the application note document AN0095.

6
project/at_start_f403a/examples/can/filter/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/can/loopback_mode/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/cortex_m4/bit_band/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/cortex_m4/cmsis_dsp/readme.txt
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@@ -8,4 +8,4 @@
this demo is based on the at-start board, demonstrates the use the maximum,
minimum, mean, standard deviation, variance and matrix functions to calculate
statistical values of marks obtained in a class. for more detailed information.
please refer to the application note document AN0036.
please refer to the application note document AN0036.

6
project/at_start_f403a/examples/cortex_m4/cmsis_dsp/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/cortex_m4/fpu/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/cortex_m4/systick_interrupt/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/crc/calculation/readme.txt
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@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, shows how to use
crc calculation unit to get a crc code of a given buffer of data word(32-bit),
if get a correct crc value led3 will be turn on, else led4 will be turn on.
for more detailed information. please refer to the application note document AN0109.
for more detailed information. please refer to the application note document AN0109.

6
project/at_start_f403a/examples/crc/calculation/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/crm/clock_failure_detection/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/crm/clock_failure_detection/src/main.c
View File

@@ -90,9 +90,9 @@ void clock_failure_detection_handler(void)
/**
* @brief config sclk 240 mhz with hick clock source.
* @note the system clock is configured as follow:
* - system clock = hick / 2 * pll_mult
* - system clock source = pll (hick)
* - hick = 8000000
* system clock (sclk) = hick / 2 * pll_mult
* system clock source = pll (hick)
* - hick = HICK_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/crm/sysclk_switch/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

12
project/at_start_f403a/examples/crm/sysclk_switch/src/main.c
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@@ -87,9 +87,9 @@ static void switch_system_clock(void)
/**
* @brief config sclk 64 mhz with hick clock source.
* @note the system clock is configured as follow:
* - system clock = hick / 2 * pll_mult
* - system clock source = pll (hick)
* - hick = 8000000
* system clock (sclk) = hick / 2 * pll_mult
* system clock source = pll (hick)
* - hick = HICK_VALUE
* - sclk = 64000000
* - ahbdiv = 1
* - ahbclk = 64000000
@@ -161,9 +161,9 @@ static void sclk_64m_hick_config(void)
/**
* @brief config sclk 96 mhz with hext clock source.
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hick = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 96000000
* - ahbdiv = 1
* - ahbclk = 96000000

2
project/at_start_f403a/examples/dac/double_mode_dma_sinewave/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, pa4 pa5 output sine
waveform
for more detailed information. please refer to the application note document AN0101.
for more detailed information. please refer to the application note document AN0101.

6
project/at_start_f403a/examples/dac/double_mode_dma_sinewave/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/dac/double_mode_dma_squarewave/readme.txt
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@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, pa4 pa5 output
square waveform.
for more detailed information. please refer to the application note document AN0101.
for more detailed information. please refer to the application note document AN0101.

6
project/at_start_f403a/examples/dac/double_mode_dma_squarewave/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/dac/one_dac_dma_escalator/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, pa4 output an
escalator waveform.
for more detailed information. please refer to the application note document AN0101.
for more detailed information. please refer to the application note document AN0101.

6
project/at_start_f403a/examples/dac/one_dac_dma_escalator/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/dac/one_dac_noisewave/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, pa4 output a noise
waveform.
for more detailed information. please refer to the application note document AN0101.
for more detailed information. please refer to the application note document AN0101.

6
project/at_start_f403a/examples/dac/one_dac_noisewave/src/at32f403a_407_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/dac/two_dac_trianglewave/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, pa4 pa5 output
triangle waveform.
for more detailed information. please refer to the application note document AN0101.
for more detailed information. please refer to the application note document AN0101.

6
project/at_start_f403a/examples/dac/two_dac_trianglewave/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/debug/tmr1/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/dma/data_to_gpio_flexible/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/dma/data_to_gpio_flexible/src/main.c
View File

@@ -101,7 +101,7 @@ int main(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA2_CHANNEL1, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA2_CHANNEL1, DMA_FDT_INT, TRUE);
/* dma2 channel1 interrupt nvic init */

6
project/at_start_f403a/examples/dma/flash_to_sram/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/dma/flash_to_sram/src/main.c
View File

@@ -117,7 +117,7 @@ int main(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL1, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
/* dma1 channel1 interrupt nvic init */

2
project/at_start_f403a/examples/exint/exint_config/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, shows how to configure
external interrupt lines. exint line (exint line0 pa0) are configured to generate
an interrupt on each rising edge. in the interrupt routine a led2/3/4 is toggled.
for more detailed information. please refer to the application note document AN0104.
for more detailed information. please refer to the application note document AN0104.

6
project/at_start_f403a/examples/exint/exint_config/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/exint/exint_software_trigger/readme.txt
View File

@@ -10,4 +10,4 @@
software trigger will be generate in tmr1 overflow interrupt.
led2 toggle means tmr1 overflow interrupt respond.
led3 and led4 toggle means exint line 4 interrupt respond.
for more detailed information. please refer to the application note document AN0104.
for more detailed information. please refer to the application note document AN0104.

6
project/at_start_f403a/examples/exint/exint_software_trigger/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/flash/fap_enable/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/flash/flash_write_read/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/flash/operate_spim/readme.txt
View File

@@ -15,4 +15,4 @@
- spim io1 ---> pb11
- spim io2 ---> pb7
- spim io3 ---> pb6
for more detailed information. please refer to the application note document AN0042.
for more detailed information. please refer to the application note document AN0042.

6
project/at_start_f403a/examples/flash/operate_spim/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 180000000
* - ahbdiv = 1
* - ahbclk = 180000000

5
project/at_start_f403a/examples/flash/run_in_spim/mdk_v5/run_in_spim.uvoptx
View File

@@ -117,6 +117,11 @@
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN2 -FF0AT32F403A_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:-AT32F403AVGT7$Flash\AT32F403A_1024.FLM) -FF1AT32F403A_EXT_TYPE2_REAMP1_GENERAT32F403A Type 2 REMAP_1 Ext.Flash(SPIM) -FS18400000 -FL11000000 -FP1($$Device:-AT32F403AVGT7$Flash\AT32F403A_EXT_TYPE2_REAMP1_GENERAL.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>

2
project/at_start_f403a/examples/flash/run_in_spim/readme.txt
View File

@@ -20,4 +20,4 @@
- spim io1 ---> pb11
- spim io2 ---> pb7
- spim io3 ---> pb6
for more detailed information. please refer to the application note document AN0042.
for more detailed information. please refer to the application note document AN0042.

6
project/at_start_f403a/examples/flash/run_in_spim/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 180000000
* - ahbdiv = 1
* - ahbclk = 180000000

2
project/at_start_f403a/examples/gpio/io_toggle/readme.txt
View File

@@ -6,4 +6,4 @@
*/
this demo is based on the at-start board, this demo toggle pa.01 forever,
to describes how to use scr and clr register for max io toggling.
to describes how to use scr and clr register for max io toggling.

6
project/at_start_f403a/examples/gpio/io_toggle/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/gpio/led_toggle/readme.txt
View File

@@ -7,4 +7,4 @@
this demo is based on the at-start board, in this demo, configure systick
timer used for delay function.
for more detailed information. please refer to the application note document AN0110.
for more detailed information. please refer to the application note document AN0110.

6
project/at_start_f403a/examples/gpio/led_toggle/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/gpio/swjtag_remap/readme.txt
View File

@@ -12,4 +12,4 @@
pb2 is pressed the swj-dp will be disabled. the swj-dp pins are configured
as output push-pull. the pa13(jtms/swdat), pa14(jtck/swclk), pa15(jtdi),
pb3(jtdo) and pb4(jtrst) pins are toggled in an infinite loop.
for more detailed information. please refer to the application note document AN0110.
for more detailed information. please refer to the application note document AN0110.

6
project/at_start_f403a/examples/gpio/swjtag_remap/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/i2c/communication_dma/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/i2c/communication_int/readme.txt
View File

@@ -17,4 +17,4 @@
pin used:
1. scl --- pb6
2. sda --- pb7
2. sda --- pb7

6
project/at_start_f403a/examples/i2c/communication_int/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/i2c/communication_poll/readme.txt
View File

@@ -17,4 +17,4 @@
pin used:
1. scl --- pb6
2. sda --- pb7
2. sda --- pb7

6
project/at_start_f403a/examples/i2c/communication_poll/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/i2c/eeprom/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/i2s/fullduplex_dma/readme.txt
View File

@@ -14,4 +14,4 @@
- pb14(miso_ext) rx <---> pc11(miso_ext) tx
- pb15(mosi) tx <---> pc12(mosi) rx
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f403a/examples/i2s/fullduplex_dma/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/i2s/halfduplex_dma/readme.txt
View File

@@ -13,4 +13,4 @@
- pb13 <---> pb3
- pb15 <---> pb5
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f403a/examples/i2s/halfduplex_dma/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/i2s/halfduplex_interrupt/readme.txt
View File

@@ -13,4 +13,4 @@
- pb13 <---> pb3
- pb15 <---> pb5
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f403a/examples/i2s/halfduplex_interrupt/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/i2s/spii2s_switch_halfduplex_polling/readme.txt
View File

@@ -13,4 +13,4 @@
- pb13 <---> pb3
- pb15 <---> pb5
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f403a/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/pwc/deepsleep_rtc/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, shows how to exit
deepsleep mode by interrupt of rtc alarm.
for more detailed information. please refer to the application note document AN0100.
for more detailed information. please refer to the application note document AN0100.

6
project/at_start_f403a/examples/pwc/deepsleep_rtc/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/pwc/deepsleep_rtc/src/main.c
View File

@@ -46,7 +46,7 @@ void rtc_config(void)
exint_init_struct.line_select = EXINT_LINE_17;
exint_init_struct.line_enable = TRUE;
exint_init_struct.line_mode = EXINT_LINE_INTERRUPUT;
exint_init_struct.line_polarity = EXINT_TRIGGER_BOTH_EDGE;
exint_init_struct.line_polarity = EXINT_TRIGGER_RISING_EDGE;
exint_init(&exint_init_struct);
/* enable the battery-powered domain write operations */
@@ -177,8 +177,8 @@ int main(void)
/* restore systick register configuration */
SysTick->CTRL |= systick_index;
/* wait clock stable */
/* wait clock stable */
delay_us(120);
/* wake up from deep sleep mode, congfig the system clock */

6
project/at_start_f403a/examples/pwc/power_voltage_monitor/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/pwc/sleep_tmr2/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, shows how to exit
sleep mode by interrupt of timer2 overflow.
for more detailed information. please refer to the application note document AN0100.
for more detailed information. please refer to the application note document AN0100.

6
project/at_start_f403a/examples/pwc/sleep_tmr2/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/pwc/sleep_usart1/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, shows how to exit
sleep mode by interrupt of usart1 receive data buffer full.
for more detailed information. please refer to the application note document AN0100.
for more detailed information. please refer to the application note document AN0100.

6
project/at_start_f403a/examples/pwc/sleep_usart1/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/pwc/standby_rtc/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, shows how to exit
standby mode by rtc alarm.
for more detailed information. please refer to the application note document AN0100.
for more detailed information. please refer to the application note document AN0100.

6
project/at_start_f403a/examples/pwc/standby_rtc/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

6
project/at_start_f403a/examples/pwc/standby_wakeup_pin/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/pwc/standby_wakeup_pin/src/main.c
View File

@@ -74,7 +74,7 @@ int main(void)
}
at32_led_on(LED4);
/*delay to check led status*/
delay_ms(1000);

2
project/at_start_f403a/examples/rtc/calendar/readme.txt
View File

@@ -9,4 +9,4 @@
rtc peripherals to implement calendar and alarm clock functions. use usart1
to view calendar information. led3 flashes once when the seconds are updated,
and led4 turns on when the alarm is generated.
for more detailed information. please refer to the application note document AN0111.
for more detailed information. please refer to the application note document AN0111.

6
project/at_start_f403a/examples/rtc/calendar/src/at32f403a_407_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000

2
project/at_start_f403a/examples/rtc/lick_calibration/readme.txt
View File

@@ -7,4 +7,4 @@
this demo is based on the at-start board, in this demo, shows how to use
timer to calibrate the lick clock. use usart1 to view calibrate information.
for more detailed information. please refer to the application note document AN0111.
for more detailed information. please refer to the application note document AN0111.

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