yemai/AT32F403A_407_Firmware_Library
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update version to v2.1.5

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This commit is contained in:
Artery-MCU
2023-08-08 19:27:03 +08:00
parent 3bac77751d
commit 4dcec715e1
719 changed files with 231851 additions and 2580 deletions
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BIN
libraries/drivers/ReleaseNotes_AT32F403A_407_Firmware_Library_Drivers.pdf
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32
libraries/drivers/inc/at32f403a_407_crc.h
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@@ -66,6 +66,17 @@ typedef enum
CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
} crc_reverse_output_type;
/**
* @brief crc polynomial size
*/
typedef enum
{
CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */
CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */
CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */
CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */
} crc_poly_size_type;
/**
* @brief type define crc register all
*/
@@ -97,7 +108,7 @@ typedef struct
};
/**
* @brief crc ctrl register, offset:0x08
* @brief crc ctrl register, offset:0x08
*/
union
{
@@ -105,7 +116,8 @@ typedef struct
struct
{
__IO uint32_t rst : 1 ; /* [0] */
__IO uint32_t reserved1 : 4 ; /* [4:1] */
__IO uint32_t reserved1 : 2 ; /* [2:1] */
__IO uint32_t poly_size : 2 ; /* [4:3] */
__IO uint32_t revid : 2 ; /* [6:5] */
__IO uint32_t revod : 1 ; /* [7] */
__IO uint32_t reserved2 : 24 ;/* [31:8] */
@@ -129,6 +141,18 @@ typedef struct
} idt_bit;
};
/**
* @brief crc polynomial register, offset:0x14
*/
union
{
__IO uint32_t poly;
struct
{
__IO uint32_t poly : 32; /* [31:0] */
} poly_bit;
};
} crc_type;
/**
@@ -150,6 +174,10 @@ uint8_t crc_common_data_get(void);
void crc_init_data_set(uint32_t value);
void crc_reverse_input_data_set(crc_reverse_input_type value);
void crc_reverse_output_data_set(crc_reverse_output_type value);
void crc_poly_value_set(uint32_t value);
uint32_t crc_poly_value_get(void);
void crc_poly_size_set(crc_poly_size_type size);
crc_poly_size_type crc_poly_size_get(void);
/**
* @}

2
libraries/drivers/inc/at32f403a_407_flash.h
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@@ -698,6 +698,8 @@ uint8_t flash_ssb_status_get(void);
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
void flash_spim_model_select(flash_spim_model_type mode);
void flash_spim_encryption_range_set(uint32_t decode_address);
void flash_spim_dummy_read(void);
flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt);
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector);
error_status flash_slib_disable(uint32_t pwd);
uint32_t flash_slib_remaining_count_get(void);

4
libraries/drivers/inc/at32f403a_407_gpio.h
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@@ -213,8 +213,8 @@ extern "C" {
#define SPI3_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 24, 4, 0x02) /*!< spi3_cs/i2s3_ws(pa15), spi3_sck/i2s3_ck(pb3), spi3_miso(pb4), spi3_mosi/i2s3_sd(pb5), i2s3_mck(pb10) */
#define SPI3_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 24, 4, 0x03) /*!< spi3_cs/i2s3_ws(pa4), spi3_sck/i2s3_ck(pc10), spi3_miso(pc11), spi3_mosi/i2s3_sd(pc12), i2s3_mck(pb10) */
#define SPI4_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x01) /*!< spi4_cs/i2s4_ws(pe12), spi4_sck/i2s4_ck(pe11), spi4_miso(pe13), spi4_mosi/i2s4_sd(pe14), i2s4_mck(pc8) */
#define SPI4_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x02) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb8), i2s4_mck(pc8) */
#define SPI4_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x03) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb8), i2s4_mck(pa10) */
#define SPI4_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x02) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb9), i2s4_mck(pc8) */
#define SPI4_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x03) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb9), i2s4_mck(pa10) */
/**
* @}

6
libraries/drivers/inc/at32f403a_407_usb.h
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@@ -199,9 +199,9 @@ typedef enum
typedef enum
{
EPT_CONTROL_TYPE = 0x00, /*!< usb transfer type control */
EPT_BULK_TYPE = 0x01, /*!< usb transfer type bulk */
EPT_INT_TYPE = 0x02, /*!< usb transfer type interrut */
EPT_ISO_TYPE = 0x03 /*!< usb transfer type iso */
EPT_ISO_TYPE = 0x01, /*!< usb transfer type iso */
EPT_BULK_TYPE = 0x02, /*!< usb transfer type bulk */
EPT_INT_TYPE = 0x03 /*!< usb transfer type interrupt */
}ept_trans_type;
/**

2
libraries/drivers/inc/at32f403a_407_xmc.h
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@@ -532,7 +532,7 @@ void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_stru
void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct);
void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state);
void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
void xmc_nand_reset(xmc_class_bank_type xmc_bank);
void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct);
void xmc_nand_timing_config(xmc_nand_timinginit_type* xmc_common_spacetiming_struct,

218
libraries/drivers/src/at32f403a_407_adc.c
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@@ -114,7 +114,7 @@ void adc_combine_mode_select(adc_combine_mode_type combine_mode)
* - ADC_LEFT_ALIGNMENT
* @param ordinary_channel_length: configure the adc ordinary channel sequence length.
* this parameter can be:
* - (0x1~0xf)
* - (0x1~0x10)
* @retval none
*/
void adc_base_default_para_init(adc_base_config_type *adc_base_struct)
@@ -140,7 +140,7 @@ void adc_base_default_para_init(adc_base_config_type *adc_base_struct)
* - ADC_LEFT_ALIGNMENT
* @param ordinary_channel_length: configure the adc ordinary channel sequence length.
* this parameter can be:
* - (0x1~0xf)
* - (0x1~0x10)
* @retval none
*/
void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct)
@@ -345,117 +345,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele
*/
void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
{
switch(adc_channel)
uint32_t tmp_reg;
if(adc_channel < ADC_CHANNEL_10)
{
case ADC_CHANNEL_0:
adc_x->spt2_bit.cspt0 = adc_sampletime;
break;
case ADC_CHANNEL_1:
adc_x->spt2_bit.cspt1 = adc_sampletime;
break;
case ADC_CHANNEL_2:
adc_x->spt2_bit.cspt2 = adc_sampletime;
break;
case ADC_CHANNEL_3:
adc_x->spt2_bit.cspt3 = adc_sampletime;
break;
case ADC_CHANNEL_4:
adc_x->spt2_bit.cspt4 = adc_sampletime;
break;
case ADC_CHANNEL_5:
adc_x->spt2_bit.cspt5 = adc_sampletime;
break;
case ADC_CHANNEL_6:
adc_x->spt2_bit.cspt6 = adc_sampletime;
break;
case ADC_CHANNEL_7:
adc_x->spt2_bit.cspt7 = adc_sampletime;
break;
case ADC_CHANNEL_8:
adc_x->spt2_bit.cspt8 = adc_sampletime;
break;
case ADC_CHANNEL_9:
adc_x->spt2_bit.cspt9 = adc_sampletime;
break;
case ADC_CHANNEL_10:
adc_x->spt1_bit.cspt10 = adc_sampletime;
break;
case ADC_CHANNEL_11:
adc_x->spt1_bit.cspt11 = adc_sampletime;
break;
case ADC_CHANNEL_12:
adc_x->spt1_bit.cspt12 = adc_sampletime;
break;
case ADC_CHANNEL_13:
adc_x->spt1_bit.cspt13 = adc_sampletime;
break;
case ADC_CHANNEL_14:
adc_x->spt1_bit.cspt14 = adc_sampletime;
break;
case ADC_CHANNEL_15:
adc_x->spt1_bit.cspt15 = adc_sampletime;
break;
case ADC_CHANNEL_16:
adc_x->spt1_bit.cspt16 = adc_sampletime;
break;
case ADC_CHANNEL_17:
adc_x->spt1_bit.cspt17 = adc_sampletime;
break;
default:
break;
tmp_reg = adc_x->spt2;
tmp_reg &= ~(0x07 << 3 * adc_channel);
tmp_reg |= adc_sampletime << 3 * adc_channel;
adc_x->spt2 = tmp_reg;
}
switch(adc_sequence)
else
{
case 1:
adc_x->osq3_bit.osn1 = adc_channel;
break;
case 2:
adc_x->osq3_bit.osn2 = adc_channel;
break;
case 3:
adc_x->osq3_bit.osn3 = adc_channel;
break;
case 4:
adc_x->osq3_bit.osn4 = adc_channel;
break;
case 5:
adc_x->osq3_bit.osn5 = adc_channel;
break;
case 6:
adc_x->osq3_bit.osn6 = adc_channel;
break;
case 7:
adc_x->osq2_bit.osn7 = adc_channel;
break;
case 8:
adc_x->osq2_bit.osn8 = adc_channel;
break;
case 9:
adc_x->osq2_bit.osn9 = adc_channel;
break;
case 10:
adc_x->osq2_bit.osn10 = adc_channel;
break;
case 11:
adc_x->osq2_bit.osn11 = adc_channel;
break;
case 12:
adc_x->osq2_bit.osn12 = adc_channel;
break;
case 13:
adc_x->osq1_bit.osn13 = adc_channel;
break;
case 14:
adc_x->osq1_bit.osn14 = adc_channel;
break;
case 15:
adc_x->osq1_bit.osn15 = adc_channel;
break;
case 16:
adc_x->osq1_bit.osn16 = adc_channel;
break;
default:
break;
tmp_reg = adc_x->spt1;
tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10));
tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10);
adc_x->spt1 = tmp_reg;
}
if(adc_sequence >= 13)
{
tmp_reg = adc_x->osq1;
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13));
tmp_reg |= adc_channel << 5 * (adc_sequence - 13);
adc_x->osq1 = tmp_reg;
}
else if(adc_sequence >= 7)
{
tmp_reg = adc_x->osq2;
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7));
tmp_reg |= adc_channel << 5 * (adc_sequence - 7);
adc_x->osq2 = tmp_reg;
}
else
{
tmp_reg = adc_x->osq3;
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1));
tmp_reg |= adc_channel << 5 * (adc_sequence - 1);
adc_x->osq3 = tmp_reg;
}
}
@@ -503,66 +428,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght)
*/
void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
{
uint16_t sequence_index=0;
switch(adc_channel)
uint32_t tmp_reg;
uint8_t sequence_index;
if(adc_channel < ADC_CHANNEL_10)
{
case ADC_CHANNEL_0:
adc_x->spt2_bit.cspt0 = adc_sampletime;
break;
case ADC_CHANNEL_1:
adc_x->spt2_bit.cspt1 = adc_sampletime;
break;
case ADC_CHANNEL_2:
adc_x->spt2_bit.cspt2 = adc_sampletime;
break;
case ADC_CHANNEL_3:
adc_x->spt2_bit.cspt3 = adc_sampletime;
break;
case ADC_CHANNEL_4:
adc_x->spt2_bit.cspt4 = adc_sampletime;
break;
case ADC_CHANNEL_5:
adc_x->spt2_bit.cspt5 = adc_sampletime;
break;
case ADC_CHANNEL_6:
adc_x->spt2_bit.cspt6 = adc_sampletime;
break;
case ADC_CHANNEL_7:
adc_x->spt2_bit.cspt7 = adc_sampletime;
break;
case ADC_CHANNEL_8:
adc_x->spt2_bit.cspt8 = adc_sampletime;
break;
case ADC_CHANNEL_9:
adc_x->spt2_bit.cspt9 = adc_sampletime;
break;
case ADC_CHANNEL_10:
adc_x->spt1_bit.cspt10 = adc_sampletime;
break;
case ADC_CHANNEL_11:
adc_x->spt1_bit.cspt11 = adc_sampletime;
break;
case ADC_CHANNEL_12:
adc_x->spt1_bit.cspt12 = adc_sampletime;
break;
case ADC_CHANNEL_13:
adc_x->spt1_bit.cspt13 = adc_sampletime;
break;
case ADC_CHANNEL_14:
adc_x->spt1_bit.cspt14 = adc_sampletime;
break;
case ADC_CHANNEL_15:
adc_x->spt1_bit.cspt15 = adc_sampletime;
break;
case ADC_CHANNEL_16:
adc_x->spt1_bit.cspt16 = adc_sampletime;
break;
case ADC_CHANNEL_17:
adc_x->spt1_bit.cspt17 = adc_sampletime;
break;
default:
break;
tmp_reg = adc_x->spt2;
tmp_reg &= ~(0x07 << 3 * adc_channel);
tmp_reg |= adc_sampletime << 3 * adc_channel;
adc_x->spt2 = tmp_reg;
}
else
{
tmp_reg = adc_x->spt1;
tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10));
tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10);
adc_x->spt1 = tmp_reg;
}
sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen;
switch(sequence_index)
{

46
libraries/drivers/src/at32f403a_407_crc.c
View File

@@ -147,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value)
CRC->ctrl_bit.revod = value;
}
/**
* @brief config crc polynomial value
* @param value
* 32-bit new data of crc poly value
* @retval none.
*/
void crc_poly_value_set(uint32_t value)
{
CRC->poly = value;
}
/**
* @brief return crc polynomial value
* @param none
* @retval 32-bit value of the polynomial value.
*/
uint32_t crc_poly_value_get(void)
{
return (CRC->poly);
}
/**
* @brief config crc polynomial data size
* @param size
* this parameter can be one of the following values:
* - CRC_POLY_SIZE_32B
* - CRC_POLY_SIZE_16B
* - CRC_POLY_SIZE_8B
* - CRC_POLY_SIZE_7B
* @retval none.
*/
void crc_poly_size_set(crc_poly_size_type size)
{
CRC->ctrl_bit.poly_size = size;
}
/**
* @brief return crc polynomial data size
* @param none
* @retval polynomial data size.
*/
crc_poly_size_type crc_poly_size_get(void)
{
return (crc_poly_size_type)(CRC->ctrl_bit.poly_size);
}
/**
* @}
*/

18
libraries/drivers/src/at32f403a_407_exint.c
View File

@@ -123,15 +123,15 @@ void exint_init(exint_init_type *exint_struct)
*/
void exint_flag_clear(uint32_t exint_line)
{
if((EXINT->swtrg & exint_line) == exint_line)
{
EXINT->intsts = exint_line;
EXINT->intsts = exint_line;
}
else
{
EXINT->intsts = exint_line;
}
if((EXINT->swtrg & exint_line) == exint_line)
{
EXINT->intsts = exint_line;
EXINT->intsts = exint_line;
}
else
{
EXINT->intsts = exint_line;
}
}
/**

81
libraries/drivers/src/at32f403a_407_flash.c
View File

@@ -480,8 +480,11 @@ flash_status_type flash_sector_erase(uint32_t sector_address)
/* disable the secers bit */
FLASH->ctrl3_bit.secers = FALSE;
/* dummy read */
flash_spim_dummy_read();
}
/* return the erase status */
return status;
}
@@ -576,7 +579,7 @@ flash_status_type flash_bank2_erase(void)
flash_status_type flash_spim_all_erase(void)
{
flash_status_type status = FLASH_OPERATE_DONE;
FLASH->ctrl3_bit.chpers = TRUE;
FLASH->ctrl3_bit.erstr = TRUE;
@@ -586,6 +589,9 @@ flash_status_type flash_spim_all_erase(void)
/* disable the chpers bit */
FLASH->ctrl3_bit.chpers = FALSE;
/* dummy read */
flash_spim_dummy_read();
/* return the erase status */
return status;
}
@@ -601,7 +607,7 @@ flash_status_type flash_user_system_data_erase(void)
{
flash_status_type status = FLASH_OPERATE_DONE;
uint16_t fap_val = FAP_RELIEVE_KEY;
/* get the flash access protection status */
if(flash_fap_status_get() != RESET)
{
@@ -682,6 +688,9 @@ flash_status_type flash_word_program(uint32_t address, uint32_t data)
/* disable the fprgm bit */
FLASH->ctrl3_bit.fprgm = FALSE;
/* dummy read */
flash_spim_dummy_read();
}
/* return the program status */
@@ -728,6 +737,9 @@ flash_status_type flash_halfword_program(uint32_t address, uint16_t data)
/* disable the fprgm bit */
FLASH->ctrl3_bit.fprgm = FALSE;
/* dummy read */
flash_spim_dummy_read();
}
/* return the program status */
@@ -779,7 +791,7 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data)
flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data)
{
flash_status_type status = FLASH_OPERATE_DONE;
if(address == USD_BASE)
{
if(data != 0xA5)
@@ -1024,6 +1036,9 @@ void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state)
void flash_spim_model_select(flash_spim_model_type mode)
{
FLASH->select = mode;
/* dummy read */
flash_spim_dummy_read();
}
/**
@@ -1038,6 +1053,62 @@ void flash_spim_encryption_range_set(uint32_t decode_address)
FLASH->da = decode_address;
}
/**
* @brief operate the flash spim dummy read.
* @param none
* @retval none
*/
void flash_spim_dummy_read(void)
{
UNUSED(*(__IO uint32_t*)FLASH_SPIM_START_ADDR);
UNUSED(*(__IO uint32_t*)(FLASH_SPIM_START_ADDR + 0x1000));
UNUSED(*(__IO uint32_t*)(FLASH_SPIM_START_ADDR + 0x2000));
}
/**
* @brief mass program for flash spim.
* @param address: specifies the start address to be programmed, word or halfword alignment is recommended.
* @param buf: specifies the pointer of data to be programmed.
* @param cnt: specifies the data counter to be programmed.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt)
{
flash_status_type status = FLASH_OPERATE_DONE;
uint32_t index, temp_offset;
if(address >= FLASH_SPIM_START_ADDR)
{
temp_offset = cnt % 4;
if((temp_offset != 0) && (temp_offset != 2))
return status;
FLASH->ctrl3_bit.fprgm = TRUE;
for(index = 0; index < cnt / 4; index++)
{
*(__IO uint32_t*)(address + index * 4) = *(uint32_t*)(buf + index * 4);
/* wait for operation to be completed */
status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT);
if(status != FLASH_OPERATE_DONE)
return status;
}
if(temp_offset == 2)
{
*(__IO uint16_t*)(address + index * 4) = *(uint16_t*)(buf + index * 4);
/* wait for operation to be completed */
status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT);
}
/* disable the fprgm bit */
FLASH->ctrl3_bit.fprgm = FALSE;
/* dummy read */
flash_spim_dummy_read();
}
/* return the program status */
return status;
}
/**
* @brief enable security library function.
* @param pwd: slib password
@@ -1056,7 +1127,7 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_
if((start_sector>=data_start_sector) || ((data_start_sector > end_sector) && \
(data_start_sector != 0x7FF)) || (start_sector > end_sector))
return FLASH_PROGRAM_ERROR;
/* unlock slib cfg register */
FLASH->slib_unlock = SLIB_UNLOCK_KEY;
while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);

6
libraries/drivers/src/at32f403a_407_i2c.c
View File

@@ -622,14 +622,14 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag)
* @retval none
*/
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag)
{
{
i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x0000DF00);
if(i2c_x->sts1 & I2C_ADDR7F_FLAG)
{
UNUSED(i2c_x->sts2);
}
if(i2c_x->sts1 & I2C_STOPF_FLAG)
{
i2c_x->ctrl1_bit.i2cen = TRUE;

15
libraries/drivers/src/at32f403a_407_tmr.c
View File

@@ -296,8 +296,7 @@ uint32_t tmr_counter_value_get(tmr_type *tmr_x)
* this parameter can be one of the following values:
* TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
* TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
* @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF,
* for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
* @param tmr_div_value (0x0000~0xFFFF)
* @retval none
*/
void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value)
@@ -342,7 +341,7 @@ void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_chan
chx_offset = (8 + tmr_channel);
chcx_offset = (9 + tmr_channel);
/* get channel idle state bit position in ctrl2 register */
channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << chx_offset);
@@ -835,7 +834,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct
switch(channel)
{
case TMR_SELECT_CHANNEL_1:
tmr_x->cctrl_bit.c1en = FALSE;
tmr_x->cctrl_bit.c1en = FALSE;
tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select;
tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1;
tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select;
@@ -845,7 +844,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct
break;
case TMR_SELECT_CHANNEL_2:
tmr_x->cctrl_bit.c2en = FALSE;
tmr_x->cctrl_bit.c2en = FALSE;
tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select;
tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1;
tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select;
@@ -855,7 +854,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct
break;
case TMR_SELECT_CHANNEL_3:
tmr_x->cctrl_bit.c3en = FALSE;
tmr_x->cctrl_bit.c3en = FALSE;
tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select;
tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1;
tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select;
@@ -865,7 +864,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct
break;
case TMR_SELECT_CHANNEL_4:
tmr_x->cctrl_bit.c4en = FALSE;
tmr_x->cctrl_bit.c4en = FALSE;
tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select;
tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select;
tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value;
@@ -1728,7 +1727,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le
}
/**
* @brief config tmr break mode and dead-time
* @brief config tmr brake mode and dead-time
* @param tmr_x: select the tmr peripheral.
* this parameter can be one of the following values:
* TMR1, TMR8

3
libraries/drivers/src/at32f403a_407_usart.c
View File

@@ -104,6 +104,9 @@ void usart_reset(usart_type* usart_x)
* this parameter can be one of the following values:
* - USART_DATA_8BITS
* - USART_DATA_9BITS.
* note：
* - when parity check is disabled, the data bit width is the actual data bit number.
* - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit.
* @param stop_bit: stop bits transmitted
* this parameter can be one of the following values:
* - USART_STOP_1_BIT

2
libraries/drivers/src/at32f403a_407_xmc.c
View File

@@ -216,7 +216,7 @@ void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state ne
* @param r2r_timing :read timing
* @retval none
*/
void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
{
XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing;
XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;