ArteryTek/AT32F415_Firmware_Library
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update version to v2.1.0

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This commit is contained in:
Artery-MCU
2023-08-08 19:30:55 +08:00
parent d7bcb64bf8
commit f49a554036
408 changed files with 224076 additions and 1271 deletions
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BIN
AT32F415_periph_lib_V2.0.9.chm → AT32F415_periph_lib_V2.1.0.chm
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document/AT32F415固件库BSP&Pack应用指南.pdf
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document/ReleaseNotes_AT32F415_Firmware_Library.pdf
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28
libraries/cmsis/cm4/device_support/at32f415.h
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@@ -68,6 +68,9 @@ extern "C" {
#define AT32F415xx
#endif
/**
* define with package
*/
#if defined (AT32F415RCT7) || defined (AT32F415RCT7_7) || defined (AT32F415RBT7) || \
defined (AT32F415RBT7_7) || defined (AT32F415R8T7) || defined (AT32F415R8T7_7)
@@ -85,6 +88,27 @@ extern "C" {
#define AT32F415Kx
#endif
/**
* define with memory density
*/
#if defined (AT32F415R8T7) || defined (AT32F415R8T7_7) || defined (AT32F415C8T7) || \
defined (AT32F415K8U7_4)
#define AT32F415x8
#endif
#if defined (AT32F415RBT7) || defined (AT32F415RBT7_7) || defined (AT32F415CBT7) || \
defined (AT32F415CBU7) || defined (AT32F415KBU7_4)
#define AT32F415xB
#endif
#if defined (AT32F415RCT7) || defined (AT32F415RCT7_7) || defined (AT32F415CCT7) || \
defined (AT32F415CCU7) || defined (AT32F415KCU7_4)
#define AT32F415xC
#endif
#ifndef USE_STDPERIPH_DRIVER
/**
* @brief comment the line below if you will not use the peripherals drivers.
@@ -103,8 +127,8 @@ extern "C" {
* @brief at32f415 standard peripheral library version number
*/
#define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F415_LIBRARY_VERSION_MIDDLE (0x00) /*!< [23:16] middle version */
#define __AT32F415_LIBRARY_VERSION_MINOR (0x09) /*!< [15:8] minor version */
#define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */
#define __AT32F415_LIBRARY_VERSION_MINOR (0x00) /*!< [15:8] minor version */
#define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24) | \
(__AT32F415_LIBRARY_VERSION_MIDDLE << 16) | \

BIN
libraries/drivers/ReleaseNotes_AT32F415_Firmware_Library_Drivers.pdf
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30
libraries/drivers/inc/at32f415_crc.h
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@@ -66,6 +66,17 @@ typedef enum
CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
} crc_reverse_output_type;
/**
* @brief crc polynomial size
*/
typedef enum
{
CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */
CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */
CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */
CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */
} crc_poly_size_type;
/**
* @brief type define crc register all
*/
@@ -105,7 +116,8 @@ typedef struct
struct
{
__IO uint32_t rst : 1 ; /* [0] */
__IO uint32_t reserved1 : 4 ; /* [4:1] */
__IO uint32_t reserved1 : 2 ; /* [2:1] */
__IO uint32_t poly_size : 2 ; /* [4:3] */
__IO uint32_t revid : 2 ; /* [6:5] */
__IO uint32_t revod : 1 ; /* [7] */
__IO uint32_t reserved2 : 24 ;/* [31:8] */
@@ -129,6 +141,18 @@ typedef struct
} idt_bit;
};
/**
* @brief crc polynomial register, offset:0x14
*/
union
{
__IO uint32_t poly;
struct
{
__IO uint32_t poly : 32; /* [31:0] */
} poly_bit;
};
} crc_type;
/**
@@ -150,6 +174,10 @@ uint8_t crc_common_data_get(void);
void crc_init_data_set(uint32_t value);
void crc_reverse_input_data_set(crc_reverse_input_type value);
void crc_reverse_output_data_set(crc_reverse_output_type value);
void crc_poly_value_set(uint32_t value);
uint32_t crc_poly_value_get(void);
void crc_poly_size_set(crc_poly_size_type size);
crc_poly_size_type crc_poly_size_get(void);
/**
* @}

4
libraries/drivers/inc/at32f415_ertc.h
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@@ -87,10 +87,6 @@ extern "C" {
#define ERTC_ALARM_MASK_DATE_WEEK ((uint32_t)0x80000000) /*!< ertc alarm don't match date or week */
#define ERTC_ALARM_MASK_ALL ((uint32_t)0x80808080) /*!< ertc alarm don't match all */
/**
* @}
*/
/**
* @brief compatible with older versions
*/

1
libraries/drivers/inc/at32f415_usb.h
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@@ -705,6 +705,7 @@ typedef struct
__IO uint32_t nptxfspcavail : 16; /* [15:0] */
__IO uint32_t nptxqspcavail : 8; /* [23:16] */
__IO uint32_t nptxqtop : 7; /* [30:24] */
__IO uint32_t reserved1 : 1; /* [31] */
} gnptxsts_bit;
};

216
libraries/drivers/src/at32f415_adc.c
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@@ -82,7 +82,7 @@ void adc_enable(adc_type *adc_x, confirm_state new_state)
* - ADC_LEFT_ALIGNMENT
* @param ordinary_channel_length: configure the adc ordinary channel sequence length.
* this parameter can be:
* - (0x1~0xf)
* - (0x1~0x10)
* @retval none
*/
void adc_base_default_para_init(adc_base_config_type *adc_base_struct)
@@ -312,117 +312,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele
*/
void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
{
switch(adc_channel)
uint32_t tmp_reg;
if(adc_channel < ADC_CHANNEL_10)
{
case ADC_CHANNEL_0:
adc_x->spt2_bit.cspt0 = adc_sampletime;
break;
case ADC_CHANNEL_1:
adc_x->spt2_bit.cspt1 = adc_sampletime;
break;
case ADC_CHANNEL_2:
adc_x->spt2_bit.cspt2 = adc_sampletime;
break;
case ADC_CHANNEL_3:
adc_x->spt2_bit.cspt3 = adc_sampletime;
break;
case ADC_CHANNEL_4:
adc_x->spt2_bit.cspt4 = adc_sampletime;
break;
case ADC_CHANNEL_5:
adc_x->spt2_bit.cspt5 = adc_sampletime;
break;
case ADC_CHANNEL_6:
adc_x->spt2_bit.cspt6 = adc_sampletime;
break;
case ADC_CHANNEL_7:
adc_x->spt2_bit.cspt7 = adc_sampletime;
break;
case ADC_CHANNEL_8:
adc_x->spt2_bit.cspt8 = adc_sampletime;
break;
case ADC_CHANNEL_9:
adc_x->spt2_bit.cspt9 = adc_sampletime;
break;
case ADC_CHANNEL_10:
adc_x->spt1_bit.cspt10 = adc_sampletime;
break;
case ADC_CHANNEL_11:
adc_x->spt1_bit.cspt11 = adc_sampletime;
break;
case ADC_CHANNEL_12:
adc_x->spt1_bit.cspt12 = adc_sampletime;
break;
case ADC_CHANNEL_13:
adc_x->spt1_bit.cspt13 = adc_sampletime;
break;
case ADC_CHANNEL_14:
adc_x->spt1_bit.cspt14 = adc_sampletime;
break;
case ADC_CHANNEL_15:
adc_x->spt1_bit.cspt15 = adc_sampletime;
break;
case ADC_CHANNEL_16:
adc_x->spt1_bit.cspt16 = adc_sampletime;
break;
case ADC_CHANNEL_17:
adc_x->spt1_bit.cspt17 = adc_sampletime;
break;
default:
break;
tmp_reg = adc_x->spt2;
tmp_reg &= ~(0x07 << 3 * adc_channel);
tmp_reg |= adc_sampletime << 3 * adc_channel;
adc_x->spt2 = tmp_reg;
}
switch(adc_sequence)
else
{
case 1:
adc_x->osq3_bit.osn1 = adc_channel;
break;
case 2:
adc_x->osq3_bit.osn2 = adc_channel;
break;
case 3:
adc_x->osq3_bit.osn3 = adc_channel;
break;
case 4:
adc_x->osq3_bit.osn4 = adc_channel;
break;
case 5:
adc_x->osq3_bit.osn5 = adc_channel;
break;
case 6:
adc_x->osq3_bit.osn6 = adc_channel;
break;
case 7:
adc_x->osq2_bit.osn7 = adc_channel;
break;
case 8:
adc_x->osq2_bit.osn8 = adc_channel;
break;
case 9:
adc_x->osq2_bit.osn9 = adc_channel;
break;
case 10:
adc_x->osq2_bit.osn10 = adc_channel;
break;
case 11:
adc_x->osq2_bit.osn11 = adc_channel;
break;
case 12:
adc_x->osq2_bit.osn12 = adc_channel;
break;
case 13:
adc_x->osq1_bit.osn13 = adc_channel;
break;
case 14:
adc_x->osq1_bit.osn14 = adc_channel;
break;
case 15:
adc_x->osq1_bit.osn15 = adc_channel;
break;
case 16:
adc_x->osq1_bit.osn16 = adc_channel;
break;
default:
break;
tmp_reg = adc_x->spt1;
tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10));
tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10);
adc_x->spt1 = tmp_reg;
}
if(adc_sequence >= 13)
{
tmp_reg = adc_x->osq1;
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13));
tmp_reg |= adc_channel << 5 * (adc_sequence - 13);
adc_x->osq1 = tmp_reg;
}
else if(adc_sequence >= 7)
{
tmp_reg = adc_x->osq2;
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7));
tmp_reg |= adc_channel << 5 * (adc_sequence - 7);
adc_x->osq2 = tmp_reg;
}
else
{
tmp_reg = adc_x->osq3;
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1));
tmp_reg |= adc_channel << 5 * (adc_sequence - 1);
adc_x->osq3 = tmp_reg;
}
}
@@ -470,66 +395,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght)
*/
void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
{
uint16_t sequence_index=0;
switch(adc_channel)
uint32_t tmp_reg;
uint8_t sequence_index;
if(adc_channel < ADC_CHANNEL_10)
{
case ADC_CHANNEL_0:
adc_x->spt2_bit.cspt0 = adc_sampletime;
break;
case ADC_CHANNEL_1:
adc_x->spt2_bit.cspt1 = adc_sampletime;
break;
case ADC_CHANNEL_2:
adc_x->spt2_bit.cspt2 = adc_sampletime;
break;
case ADC_CHANNEL_3:
adc_x->spt2_bit.cspt3 = adc_sampletime;
break;
case ADC_CHANNEL_4:
adc_x->spt2_bit.cspt4 = adc_sampletime;
break;
case ADC_CHANNEL_5:
adc_x->spt2_bit.cspt5 = adc_sampletime;
break;
case ADC_CHANNEL_6:
adc_x->spt2_bit.cspt6 = adc_sampletime;
break;
case ADC_CHANNEL_7:
adc_x->spt2_bit.cspt7 = adc_sampletime;
break;
case ADC_CHANNEL_8:
adc_x->spt2_bit.cspt8 = adc_sampletime;
break;
case ADC_CHANNEL_9:
adc_x->spt2_bit.cspt9 = adc_sampletime;
break;
case ADC_CHANNEL_10:
adc_x->spt1_bit.cspt10 = adc_sampletime;
break;
case ADC_CHANNEL_11:
adc_x->spt1_bit.cspt11 = adc_sampletime;
break;
case ADC_CHANNEL_12:
adc_x->spt1_bit.cspt12 = adc_sampletime;
break;
case ADC_CHANNEL_13:
adc_x->spt1_bit.cspt13 = adc_sampletime;
break;
case ADC_CHANNEL_14:
adc_x->spt1_bit.cspt14 = adc_sampletime;
break;
case ADC_CHANNEL_15:
adc_x->spt1_bit.cspt15 = adc_sampletime;
break;
case ADC_CHANNEL_16:
adc_x->spt1_bit.cspt16 = adc_sampletime;
break;
case ADC_CHANNEL_17:
adc_x->spt1_bit.cspt17 = adc_sampletime;
break;
default:
break;
tmp_reg = adc_x->spt2;
tmp_reg &= ~(0x07 << 3 * adc_channel);
tmp_reg |= adc_sampletime << 3 * adc_channel;
adc_x->spt2 = tmp_reg;
}
else
{
tmp_reg = adc_x->spt1;
tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10));
tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10);
adc_x->spt1 = tmp_reg;
}
sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen;
switch(sequence_index)
{

46
libraries/drivers/src/at32f415_crc.c
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@@ -147,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value)
CRC->ctrl_bit.revod = value;
}
/**
* @brief config crc polynomial value
* @param value
* 32-bit new data of crc poly value
* @retval none.
*/
void crc_poly_value_set(uint32_t value)
{
CRC->poly = value;
}
/**
* @brief return crc polynomial value
* @param none
* @retval 32-bit value of the polynomial value.
*/
uint32_t crc_poly_value_get(void)
{
return (CRC->poly);
}
/**
* @brief config crc polynomial data size
* @param size
* this parameter can be one of the following values:
* - CRC_POLY_SIZE_32B
* - CRC_POLY_SIZE_16B
* - CRC_POLY_SIZE_8B
* - CRC_POLY_SIZE_7B
* @retval none.
*/
void crc_poly_size_set(crc_poly_size_type size)
{
CRC->ctrl_bit.poly_size = size;
}
/**
* @brief return crc polynomial data size
* @param none
* @retval polynomial data size.
*/
crc_poly_size_type crc_poly_size_get(void)
{
return (crc_poly_size_type)(CRC->ctrl_bit.poly_size);
}
/**
* @}
*/

5
libraries/drivers/src/at32f415_tmr.c
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@@ -258,8 +258,7 @@ uint32_t tmr_counter_value_get(tmr_type *tmr_x)
* @param tmr_x: select the tmr peripheral.
* this parameter can be one of the following values:
* TMR1, TMR2, TMR3, TMR4, TMR5, TMR9, TMR10, TMR11
* @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF,
* for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
* @param tmr_div_value (0x0000~0xFFFF)
* @retval none
*/
void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value)
@@ -1681,7 +1680,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le
}
/**
* @brief config tmr break mode and dead-time
* @brief config tmr brake mode and dead-time
* @param tmr_x: select the tmr peripheral.
* this parameter can be one of the following values:
* TMR1

3
libraries/drivers/src/at32f415_usart.c
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@@ -90,6 +90,9 @@ void usart_reset(usart_type* usart_x)
* this parameter can be one of the following values:
* - USART_DATA_8BITS
* - USART_DATA_9BITS.
* note：
* - when parity check is disabled, the data bit width is the actual data bit number.
* - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit.
* @param stop_bit: stop bits transmitted
* this parameter can be one of the following values:
* - USART_STOP_1_BIT

3
libraries/drivers/src/at32f415_usb.c
View File

@@ -100,7 +100,7 @@ void usb_global_init(otg_global_type *usbx)
*/
otg_global_type *usb_global_select_core(uint8_t usb_id)
{
/* use otg1 */
UNUSED(usb_id);
return OTG1_GLOBAL;
}
@@ -440,6 +440,7 @@ void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uin
uint32_t n_index;
uint32_t nhbytes = (nbytes + 3) / 4;
uint32_t *pbuf = (uint32_t *)pusr_buf;
UNUSED(num);
for(n_index = 0; n_index < nhbytes; n_index ++)
{
#if defined (__ICCARM__) && (__VER__ < 7000000)

5
middlewares/usb_drivers/inc/usb_std.h
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@@ -248,8 +248,13 @@ typedef struct
/**
* @brief min and max define
*/
#ifndef MIN
#define MIN(a, b) (uint16_t)(((a) < (b)) ? (a) : (b)) /*!< min define*/
#endif
#ifndef MAX
#define MAX(a, b) (uint16_t)(((a) > (b)) ? (a) : (b)) /*!< max define*/
#endif
/**
* @brief low byte and high byte define

20
middlewares/usb_drivers/src/usbd_sdr.c
View File

@@ -396,9 +396,11 @@ usb_sts_type usbd_interface_request(usbd_core_type *udev)
usb_setup_type *setup = &udev->setup;
switch(udev->conn_state)
{
case USB_CONN_STATE_DEFAULT:
case USB_CONN_STATE_ADDRESSED:
case USB_CONN_STATE_CONFIGURED:
udev->class_handler->setup_handler(udev, &udev->setup);
if(setup->wLength == 0)
ret = udev->class_handler->setup_handler(udev, &udev->setup);
if(setup->wLength == 0 && ret == USB_OK)
{
usbd_ctrl_send_status(udev);
}
@@ -422,9 +424,10 @@ usb_sts_type usbd_endpoint_request(usbd_core_type *udev)
uint8_t ept_addr = LBYTE(setup->wIndex);
usb_ept_info *ept_info;
if((setup->bmRequestType & USB_REQ_TYPE_RESERVED) == USB_REQ_TYPE_CLASS)
if((setup->bmRequestType & USB_REQ_TYPE_RESERVED) != USB_REQ_TYPE_STANDARD)
{
udev->class_handler->setup_handler(udev, &udev->setup);
return ret;
}
switch(setup->bRequest)
{
@@ -436,6 +439,17 @@ usb_sts_type usbd_endpoint_request(usbd_core_type *udev)
{
usbd_set_stall(udev, ept_addr);
}
if((ept_addr & 0x80) != 0)
{
ept_info = &udev->ept_in[ept_addr & 0x7F];
}
else
{
ept_info = &udev->ept_out[ept_addr & 0x7F];
}
ept_info->status = 0x0000;
usbd_ctrl_send(udev, (uint8_t *)(&ept_info->status), 2);
break;
case USB_CONN_STATE_CONFIGURED:
{

6
middlewares/usbd_class/audio/audio_class.c
View File

@@ -192,8 +192,12 @@ static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup)
audio_set_interface(udev, setup);
usbd_ctrl_send_status(pudev);
break;
case USB_STD_REQ_CLEAR_FEATURE:
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;

5
middlewares/usbd_class/audio/audio_desc.c
View File

@@ -52,7 +52,10 @@ static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_desc_buffer[256] ALIGNED_TAIL;
/**
* @brief device descriptor handler structure

10
middlewares/usbd_class/audio_hid/audio_hid_class.c
View File

@@ -209,7 +209,12 @@ static usb_sts_type class_audio_setup_handler(void *udev, usb_setup_type *setup)
usbd_ctrl_send_status(pudev);
break;
case USB_STD_REQ_CLEAR_FEATURE:
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;
@@ -286,7 +291,12 @@ static usb_sts_type class_hid_setup_handler(void *udev, usb_setup_type *setup)
case USB_STD_REQ_SET_INTERFACE:
paudio_hid->alt_setting = setup->wValue;
break;
case USB_STD_REQ_CLEAR_FEATURE:
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;

5
middlewares/usbd_class/audio_hid/audio_hid_desc.c
View File

@@ -52,7 +52,10 @@ static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_desc_buffer[256] ALIGNED_TAIL;
/**
* @brief device descriptor handler structure

5
middlewares/usbd_class/cdc/cdc_class.c
View File

@@ -173,7 +173,12 @@ static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup)
case USB_STD_REQ_SET_INTERFACE:
pcdc->alt_setting = setup->wValue;
break;
case USB_STD_REQ_CLEAR_FEATURE:
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;

5
middlewares/usbd_class/cdc/cdc_desc.c
View File

@@ -54,7 +54,10 @@ static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_desc_buffer[256] ALIGNED_TAIL;
/**
* @brief device descriptor handler structure

10
middlewares/usbd_class/composite_cdc_keyboard/cdc_keyboard_class.c
View File

@@ -349,7 +349,12 @@ static usb_sts_type cdc_class_setup_handler(void *udev, usb_setup_type *setup)
case USB_STD_REQ_SET_INTERFACE:
vcpkybrd->alt_setting = setup->wValue;
break;
case USB_STD_REQ_CLEAR_FEATURE:
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;
@@ -424,7 +429,12 @@ static usb_sts_type keyboard_class_setup_handler(void *udev, usb_setup_type *set
case USB_STD_REQ_SET_INTERFACE:
vcpkybrd->alt_setting = setup->wValue;
break;
case USB_STD_REQ_CLEAR_FEATURE:
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;

5
middlewares/usbd_class/composite_cdc_keyboard/cdc_keyboard_desc.c
View File

@@ -52,7 +52,10 @@ static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_desc_buffer[256] ALIGNED_TAIL;
/**
* @brief device descriptor handler structure

8
middlewares/usbd_class/composite_cdc_msc/cdc_msc_class.c
View File

@@ -228,7 +228,12 @@ static usb_sts_type cdc_class_setup_handler(void *udev, usb_setup_type *setup)
case USB_STD_REQ_SET_INTERFACE:
pcdc->alt_setting = setup->wValue;
break;
case USB_STD_REQ_CLEAR_FEATURE:
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;
@@ -298,7 +303,10 @@ static usb_sts_type msc_class_setup_handler(void *udev, usb_setup_type *setup)
}
bot_scsi_clear_feature(udev, setup->wIndex);
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;

2
middlewares/usbd_class/composite_cdc_msc/cdc_msc_class.h
View File

@@ -231,7 +231,7 @@ typedef struct
uint32_t blk_nbr[MSC_SUPPORT_MAX_LUN];
uint32_t blk_size[MSC_SUPPORT_MAX_LUN];
uint32_t blk_addr;
uint64_t blk_addr;
uint32_t blk_len;
uint32_t data_len;

5
middlewares/usbd_class/composite_cdc_msc/cdc_msc_desc.c
View File

@@ -56,7 +56,10 @@ static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_desc_buffer[256] ALIGNED_TAIL;
/**
* @brief device descriptor handler structure

5
middlewares/usbd_class/custom_hid/custom_hid_class.c
View File

@@ -174,7 +174,12 @@ static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup)
case USB_STD_REQ_SET_INTERFACE:
pcshid->alt_setting = setup->wValue;
break;
case USB_STD_REQ_CLEAR_FEATURE:
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;

5
middlewares/usbd_class/custom_hid/custom_hid_desc.c
View File

@@ -52,7 +52,10 @@ static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_desc_buffer[256] ALIGNED_TAIL;
/**
* @brief custom hid device descriptor handler structure

5
middlewares/usbd_class/hid_iap/hid_iap_class.c
View File

@@ -171,7 +171,12 @@ static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup)
case USB_STD_REQ_SET_INTERFACE:
piap->alt_setting = setup->wValue;
break;
case USB_STD_REQ_CLEAR_FEATURE:
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;

5
middlewares/usbd_class/hid_iap/hid_iap_desc.c
View File

@@ -55,7 +55,10 @@ static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_desc_buffer[256] ALIGNED_TAIL;
/**
* @brief hid device descriptor handler structure

5
middlewares/usbd_class/keyboard/keyboard_class.c
View File

@@ -297,7 +297,12 @@ static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup)
case USB_STD_REQ_SET_INTERFACE:
pkeyboard->alt_setting = setup->wValue;
break;
case USB_STD_REQ_CLEAR_FEATURE:
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;

5
middlewares/usbd_class/keyboard/keyboard_desc.c
View File

@@ -53,7 +53,10 @@ static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_desc_buffer[256] ALIGNED_TAIL;
/**
* @brief keyboard device descriptor handler structure

7
middlewares/usbd_class/mouse/mouse_class.c
View File

@@ -161,6 +161,13 @@ static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup)
case USB_STD_REQ_SET_INTERFACE:
pmouse->alt_setting = setup->wValue;
break;
case USB_STD_REQ_CLEAR_FEATURE:
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;
default:

5
middlewares/usbd_class/mouse/mouse_desc.c
View File

@@ -53,7 +53,10 @@ static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_desc_buffer[256] ALIGNED_TAIL;
/**
* @brief mouse device descriptor handler structure

2
middlewares/usbd_class/msc/msc_bot_scsi.h
View File

@@ -197,7 +197,7 @@ typedef struct
uint32_t blk_nbr[MSC_SUPPORT_MAX_LUN];
uint32_t blk_size[MSC_SUPPORT_MAX_LUN];
uint32_t blk_addr;
uint64_t blk_addr;
uint32_t blk_len;
uint32_t data_len;

3
middlewares/usbd_class/msc/msc_class.c
View File

@@ -165,7 +165,10 @@ static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup)
}
bot_scsi_clear_feature(udev, setup->wIndex);
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;

5
middlewares/usbd_class/msc/msc_desc.c
View File

@@ -54,7 +54,10 @@ static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_desc_buffer[256] ALIGNED_TAIL;
/**
* @brief device descriptor handler structure

37
middlewares/usbd_class/printer/printer_class.c
View File

@@ -163,7 +163,12 @@ static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup)
case USB_STD_REQ_SET_INTERFACE:
pprter->alt_setting = setup->wValue;
break;
case USB_STD_REQ_CLEAR_FEATURE:
break;
case USB_STD_REQ_SET_FEATURE:
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;
@@ -235,6 +240,9 @@ static usb_sts_type class_out_handler(void *udev, uint8_t ept_num)
usbd_core_type *pudev = (usbd_core_type *)udev;
printer_type *pprter = (printer_type *)pudev->class_handler->pdata;
/* get endpoint receive data length */
pprter->g_rxlen = usbd_get_recv_len(pudev, ept_num);
/*set recv flag*/
pprter->g_rx_completed = 1;
@@ -291,6 +299,35 @@ static usb_sts_type class_event_handler(void *udev, usbd_event_type event)
return status;
}
/**
* @brief usb device class rx data process
* @param udev: to the structure of usbd_core_type
* @param recv_data: receive buffer
* @retval receive data len
*/
uint16_t usb_printer_get_rxdata(void *udev, uint8_t *recv_data)
{
uint16_t i_index = 0;
uint16_t tmp_len = 0;
usbd_core_type *pudev = (usbd_core_type *)udev;
printer_type *pprter = (printer_type *)pudev->class_handler->pdata;
if(pprter->g_rx_completed == 0)
{
return 0;
}
pprter->g_rx_completed = 0;
tmp_len = pprter->g_rxlen;
for(i_index = 0; i_index < pprter->g_rxlen; i_index ++)
{
recv_data[i_index] = pprter->g_rx_buff[i_index];
}
usbd_ept_recv(pudev, USBD_PRINTER_BULK_OUT_EPT, pprter->g_rx_buff, USBD_PRINTER_OUT_MAXPACKET_SIZE);
return tmp_len;
}
/**
* @brief usb device class send data
* @param udev: to the structure of usbd_core_type

1
middlewares/usbd_class/printer/printer_class.h
View File

@@ -68,6 +68,7 @@ typedef struct
uint32_t g_printer_port_status;
uint8_t g_rx_buff[USBD_PRINTER_OUT_MAXPACKET_SIZE];
uint8_t g_printer_data[USBD_PRINTER_OUT_MAXPACKET_SIZE];
uint32_t g_rxlen;
__IO uint8_t g_tx_completed;
__IO uint8_t g_rx_completed;
}printer_type;

5
middlewares/usbd_class/printer/printer_desc.c
View File

@@ -54,7 +54,10 @@ static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_desc_buffer[256] ALIGNED_TAIL;
/**
* @brief device descriptor handler structure

4
middlewares/usbh_class/usbh_cdc/usbh_cdc_class.h
View File

@@ -22,8 +22,8 @@
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBH_MSC_CLASS_H
#define __USBH_MSC_CLASS_H
#ifndef __USBH_CDC_CLASS_H
#define __USBH_CDC_CLASS_H
#ifdef __cplusplus
extern "C" {

12
project/at32f415_board/at32f415_board.c
View File

@@ -93,16 +93,24 @@ static __IO uint32_t fac_ms;
PUTCHAR_PROTOTYPE
{
while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET);
usart_data_transmit(PRINT_UART, ch);
usart_data_transmit(PRINT_UART, (uint16_t)ch);
while(usart_flag_get(PRINT_UART, USART_TDC_FLAG) == RESET);
return ch;
}
#if (defined (__GNUC__) && !defined (__clang__)) || (defined (__ICCARM__))
#if defined (__GNUC__) && !defined (__clang__)
int _write(int fd, char *pbuffer, int size)
#elif defined ( __ICCARM__ )
#pragma module_name = "?__write"
int __write(int fd, char *pbuffer, int size)
#endif
{
for(int i = 0; i < size; i ++)
{
__io_putchar(*pbuffer++);
while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET);
usart_data_transmit(PRINT_UART, (uint16_t)(*pbuffer++));
while(usart_flag_get(PRINT_UART, USART_TDC_FLAG) == RESET);
}
return size;

6
project/at_start_f415/examples/adc/current_vref_value_check/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/adc/exint_trigger_partitioned/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/adc/internal_temperature_sensor/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/adc/software_trigger_repeat/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/adc/voltage_monitoring/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/can/communication_mode/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/can/filter/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/can/loopback_mode/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

44
project/at_start_f415/examples/cmp/cycle_by_cycle_control/inc/at32f415_clock.h Normal file
View File

@@ -0,0 +1,44 @@
/**
**************************************************************************
* @file at32f415_clock.h
* @brief header file of clock program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_CLOCK_H
#define __AT32F415_CLOCK_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f415.h"
/* exported functions ------------------------------------------------------- */
void system_clock_config(void);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F415_CLOCK_H */

145
project/at_start_f415/examples/cmp/cycle_by_cycle_control/inc/at32f415_conf.h Normal file
View File

@@ -0,0 +1,145 @@
/**
**************************************************************************
* @file at32f415_conf.h
* @brief at32f415 config header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_CONF_H
#define __AT32F415_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief in the following line adjust the value of high speed exernal crystal (hext)
* used in your application
* tip: to avoid modifying this file each time you need to use different hext, you
* can define the hext value in your toolchain compiler preprocessor.
*/
#if !defined HEXT_VALUE
#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed exernal crystal in hz */
#endif
/**
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED
#define CMP_MODULE_ENABLED
#define TMR_MODULE_ENABLED
#define ERTC_MODULE_ENABLED
#define GPIO_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define USART_MODULE_ENABLED
#define PWC_MODULE_ENABLED
#define CAN_MODULE_ENABLED
#define ADC_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define DMA_MODULE_ENABLED
#define DEBUG_MODULE_ENABLED
#define FLASH_MODULE_ENABLED
#define CRC_MODULE_ENABLED
#define WWDT_MODULE_ENABLED
#define WDT_MODULE_ENABLED
#define EXINT_MODULE_ENABLED
#define SDIO_MODULE_ENABLED
#define USB_MODULE_ENABLED
#define MISC_MODULE_ENABLED
/* includes ------------------------------------------------------------------*/
#ifdef CRM_MODULE_ENABLED
#include "at32f415_crm.h"
#endif
#ifdef CMP_MODULE_ENABLED
#include "at32f415_cmp.h"
#endif
#ifdef TMR_MODULE_ENABLED
#include "at32f415_tmr.h"
#endif
#ifdef ERTC_MODULE_ENABLED
#include "at32f415_ertc.h"
#endif
#ifdef GPIO_MODULE_ENABLED
#include "at32f415_gpio.h"
#endif
#ifdef I2C_MODULE_ENABLED
#include "at32f415_i2c.h"
#endif
#ifdef USART_MODULE_ENABLED
#include "at32f415_usart.h"
#endif
#ifdef PWC_MODULE_ENABLED
#include "at32f415_pwc.h"
#endif
#ifdef CAN_MODULE_ENABLED
#include "at32f415_can.h"
#endif
#ifdef ADC_MODULE_ENABLED
#include "at32f415_adc.h"
#endif
#ifdef SPI_MODULE_ENABLED
#include "at32f415_spi.h"
#endif
#ifdef DMA_MODULE_ENABLED
#include "at32f415_dma.h"
#endif
#ifdef DEBUG_MODULE_ENABLED
#include "at32f415_debug.h"
#endif
#ifdef FLASH_MODULE_ENABLED
#include "at32f415_flash.h"
#endif
#ifdef CRC_MODULE_ENABLED
#include "at32f415_crc.h"
#endif
#ifdef WWDT_MODULE_ENABLED
#include "at32f415_wwdt.h"
#endif
#ifdef WDT_MODULE_ENABLED
#include "at32f415_wdt.h"
#endif
#ifdef EXINT_MODULE_ENABLED
#include "at32f415_exint.h"
#endif
#ifdef SDIO_MODULE_ENABLED
#include "at32f415_sdio.h"
#endif
#ifdef MISC_MODULE_ENABLED
#include "at32f415_misc.h"
#endif
#ifdef USB_MODULE_ENABLED
#include "at32f415_usb.h"
#endif
#ifdef __cplusplus
}
#endif
#endif /* __AT32F415_CONF_H */

56
project/at_start_f415/examples/cmp/cycle_by_cycle_control/inc/at32f415_int.h Normal file
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/**
**************************************************************************
* @file at32f415_int.h
* @brief header file of main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_INT_H
#define __AT32F415_INT_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f415.h"
/* exported types ------------------------------------------------------------*/
/* exported constants --------------------------------------------------------*/
/* exported macro ------------------------------------------------------------*/
/* exported functions ------------------------------------------------------- */
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
#ifdef __cplusplus
}
#endif
#endif

368
project/at_start_f415/examples/cmp/cycle_by_cycle_control/mdk_v5/cycle_by_cycle_control.uvoptx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<oExt>*.obj; *.o</oExt>
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<OPTXL>
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</DebugOpt>
<TargetDriverDllRegistry>
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<Key>UL2CM3</Key>
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</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
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<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
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</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
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<LntExFlags>0</LntExFlags>
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<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
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<FilenameWithoutPath>at32f415_clock.c</FilenameWithoutPath>
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</File>
<File>
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497
project/at_start_f415/examples/cmp/cycle_by_cycle_control/mdk_v5/cycle_by_cycle_control.uvprojx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
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<Header>### uVision Project, (C) Keil Software</Header>
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<Target>
<TargetName>cycle_by_cycle_control</TargetName>
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<TargetCommonOption>
<Device>-AT32F415RCT7</Device>
<Vendor>ArteryTek</Vendor>
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</TargetStatus>
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<OutputName>cycle_by_cycle_control</OutputName>
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<StartAddress>0x8000000</StartAddress>
<Size>0x40000</Size>
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<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
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<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
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<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
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<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
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<Type>0</Type>
<StartAddress>0x0</StartAddress>
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</OCR_RVCT8>
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<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x8000</Size>
</OCR_RVCT9>
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<Type>0</Type>
<StartAddress>0x0</StartAddress>
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</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
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<MiscControls></MiscControls>
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<umfTarg>1</umfTarg>
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<RepFail>1</RepFail>
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<TextAddressRange>0x08000000</TextAddressRange>
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<ScatterFile></ScatterFile>
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13
project/at_start_f415/examples/cmp/cycle_by_cycle_control/readme.txt Normal file
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@@ -0,0 +1,13 @@
/**
**************************************************************************
* @file readme.txt
* @brief readme
**************************************************************************
*/
this example shows how to use the comparator's cycle-by-cycle current control
function, and inernally connected to the tmr1 channel clear. connect the current
sensor to the cmp_in(pa1), the cmp_out(pa0) will output the result. when the
cmp_out is low level, tmr1_ch1(pa8) will output PWM; when the cmp_out is high level,
the PWM of tmr1_ch1 will be cleared. for more detailed information. please refer
to the application note document AN0046.

97
project/at_start_f415/examples/cmp/cycle_by_cycle_control/src/at32f415_clock.c Normal file
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/**
**************************************************************************
* @file at32f415_clock.c
* @brief system clock config program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f415_clock.h"
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000
* - apb2div = 2
* - apb2clk = 72000000
* - apb1div = 2
* - apb1clk = 72000000
* - pll_mult = 36
* - flash_wtcyc = 4 cycle
* @param none
* @retval none
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* config flash psr register */
flash_psr_set(FLASH_WAIT_CYCLE_4);
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */
while(crm_hext_stable_wait() == ERROR)
{
}
/* config pll clock resource */
crm_pll_config(CRM_PLL_SOURCE_HEXT_DIV, CRM_PLL_MULT_36);
/* enable pll */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
/* wait till pll is ready */
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
{
}
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb1_div_set(CRM_APB1_DIV_2);
/* enable auto step mode */
crm_auto_step_mode_enable(TRUE);
/* select pll as system clock source */
crm_sysclk_switch(CRM_SCLK_PLL);
/* wait till pll is used as system clock source */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
{
}
/* disable auto step mode */
crm_auto_step_mode_enable(FALSE);
/* update system_core_clock global variable */
system_core_clock_update();
}

140
project/at_start_f415/examples/cmp/cycle_by_cycle_control/src/at32f415_int.c Normal file
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@@ -0,0 +1,140 @@
/**
**************************************************************************
* @file at32f415_int.c
* @brief main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f415_int.h"
/** @addtogroup AT32F415_periph_examples
* @{
*/
/** @addtogroup 415_CMP_cycle_by_cycle_control
* @{
*/
/**
* @brief this function handles nmi exception.
* @param none
* @retval none
*/
void NMI_Handler(void)
{
}
/**
* @brief this function handles hard fault exception.
* @param none
* @retval none
*/
void HardFault_Handler(void)
{
/* go to infinite loop when hard fault exception occurs */
while(1)
{
}
}
/**
* @brief this function handles memory manage exception.
* @param none
* @retval none
*/
void MemManage_Handler(void)
{
/* go to infinite loop when memory manage exception occurs */
while(1)
{
}
}
/**
* @brief this function handles bus fault exception.
* @param none
* @retval none
*/
void BusFault_Handler(void)
{
/* go to infinite loop when bus fault exception occurs */
while(1)
{
}
}
/**
* @brief this function handles usage fault exception.
* @param none
* @retval none
*/
void UsageFault_Handler(void)
{
/* go to infinite loop when usage fault exception occurs */
while(1)
{
}
}
/**
* @brief this function handles svcall exception.
* @param none
* @retval none
*/
void SVC_Handler(void)
{
}
/**
* @brief this function handles debug monitor exception.
* @param none
* @retval none
*/
void DebugMon_Handler(void)
{
}
/**
* @brief this function handles pendsv_handler exception.
* @param none
* @retval none
*/
void PendSV_Handler(void)
{
}
/**
* @brief this function handles systick handler.
* @param none
* @retval none
*/
void SysTick_Handler(void)
{
}
/**
* @}
*/
/**
* @}
*/

156
project/at_start_f415/examples/cmp/cycle_by_cycle_control/src/main.c Normal file
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@@ -0,0 +1,156 @@
/**
**************************************************************************
* @file main.c
* @brief main program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f415_board.h"
#include "at32f415_clock.h"
/** @addtogroup AT32F415_periph_examples
* @{
*/
/** @addtogroup 415_CMP_cycle_by_cycle_control CMP_cycle_by_cycle_control
* @{
*/
gpio_init_type gpio_init_struct = {0};
/**
* @brief configures cmp
* @param none
* @retval none
*/
void cmp_config(void)
{
cmp_init_type cmp_init_struct;
/* gpioa peripheral clock enable */
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_IOMUX_PERIPH_CLOCK, TRUE);
/* configure pa1: pa1 is used as cmp1 non inveting input */
gpio_init_struct.gpio_pins = GPIO_PINS_1;
gpio_init_struct.gpio_mode = GPIO_MODE_ANALOG;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init(GPIOA, &gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_0;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init(GPIOA, &gpio_init_struct);
gpio_pin_remap_config(TMR1_CH1_CMP_GMUX_10, TRUE);
/* cmp peripheral clock enable */
crm_periph_clock_enable(CRM_CMP_PERIPH_CLOCK, TRUE);
/* cmp1 init: pa1 is used cmp1 inverting input */
cmp_default_para_init(&cmp_init_struct);
cmp_init_struct.cmp_inverting = CMP_INVERTING_VREFINT;
cmp_init_struct.cmp_output = CMP_OUTPUT_TMR1CHCLR;
cmp_init_struct.cmp_polarity = CMP_POL_NON_INVERTING;
cmp_init_struct.cmp_speed = CMP_SPEED_FAST;
cmp_init_struct.cmp_hysteresis = CMP_HYSTERESIS_NONE;
cmp_init(CMP1_SELECTION, &cmp_init_struct);
/* enable cmp1 */
cmp_enable(CMP1_SELECTION, TRUE);
}
/**
* @brief configures tmr1_ch1 as input
* @param none
* @retval none
*/
void tmr1_init(void)
{
tmr_output_config_type tmr_output_structure;
crm_periph_clock_enable(CRM_TMR1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_8;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init(GPIOA, &gpio_init_struct);
nvic_irq_enable(TMR1_CH_IRQn, 0, 1);
/* tmr1 time base configuration */
tmr_base_init(TMR1, 9999, 0);
tmr_cnt_dir_set(TMR1, TMR_COUNT_UP);
tmr_clock_source_div_set(TMR1, TMR_CLOCK_DIV1);
/* channel 4 configuration in pwm mode */
tmr_output_default_para_init(&tmr_output_structure);
tmr_output_structure.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_A;
tmr_output_structure.oc_idle_state = FALSE;
tmr_output_structure.occ_idle_state = FALSE;
tmr_output_structure.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
tmr_output_structure.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
tmr_output_structure.oc_output_state = TRUE;
tmr_output_structure.occ_output_state = FALSE;
tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_1, &tmr_output_structure);
tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_1, 5000);
tmr_output_channel_switch_select(TMR1, TMR_CH_SWITCH_SELECT_CXORAW_OFF);
tmr_output_channel_switch_set(TMR1, TMR_SELECT_CHANNEL_1, TRUE);
/* tmr1 output enable */
tmr_output_enable(TMR1, TRUE);
/* tmr1 counter enable */
tmr_counter_enable(TMR1, TRUE);
}
/**
* @brief main function.
* @param none
* @retval none
*/
int main(void)
{
system_clock_config();
at32_board_init();
/* cmp1 configuration */
cmp_config();
/* tmr1 configuration in input capture mode */
tmr1_init();
while (1)
{
}
}
/**
* @}
*/
/**
* @}
*/

6
project/at_start_f415/examples/cmp/deep_sleep_mode/src/at32f415_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/cmp/output/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/cortex_m4/bit_band/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/cortex_m4/cmsis_dsp/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/cortex_m4/systick_interrupt/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/crc/calculation/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/crm/clock_failure_detection/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/crm/clock_failure_detection/src/main.c
View File

@@ -90,9 +90,9 @@ void clock_failure_detection_handler(void)
/**
* @brief config sclk 144 mhz with hick clock source.
* @note the system clock is configured as follow:
* - system clock = hick / 2 * pll_mult
* - system clock source = pll (hick)
* - hick = 8000000
* system clock (sclk) = hick / 2 * pll_mult
* system clock source = pll (hick)
* - hick = HICK_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/crm/pll_config2/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 150000000
* - ahbdiv = 1
* - ahbclk = 150000000

6
project/at_start_f415/examples/crm/sysclk_switch/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

12
project/at_start_f415/examples/crm/sysclk_switch/src/main.c
View File

@@ -87,9 +87,9 @@ static void switch_system_clock(void)
/**
* @brief config sclk 64 mhz with hick clock source.
* @note the system clock is configured as follow:
* - system clock = hick / 2 * pll_mult
* - system clock source = pll (hick)
* - hick = 8000000
* system clock (sclk) = hick / 2 * pll_mult
* system clock source = pll (hick)
* - hick = HICK_VALUE
* - sclk = 64000000
* - ahbdiv = 1
* - ahbclk = 64000000
@@ -164,9 +164,9 @@ static void sclk_64m_hick_config(void)
/**
* @brief config sclk 96 mhz with hext clock source.
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hick = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 96000000
* - ahbdiv = 1
* - ahbclk = 96000000

6
project/at_start_f415/examples/debug/tmr1/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/dma/data_to_gpio_flexible/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/dma/data_to_gpio_flexible/src/main.c
View File

@@ -102,7 +102,7 @@ int main(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA2_CHANNEL1, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA2_CHANNEL1, DMA_FDT_INT, TRUE);
/* dma2 channel1 interrupt nvic init */

6
project/at_start_f415/examples/dma/flash_to_sram/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/dma/flash_to_sram/src/main.c
View File

@@ -117,7 +117,7 @@ int main(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL1, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
/* dma1 channel1 interrupt nvic init */

6
project/at_start_f415/examples/ertc/bpr_domain/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/ertc/calendar/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/ertc/lick_calibration/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/ertc/tamper/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/ertc/time_stamp/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/ertc/wakeup_timer/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/exint/exint_config/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/exint/exint_software_trigger/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/flash/fap_enable/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/flash/flash_write_read/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

4
project/at_start_f415/examples/flash/flash_write_read/src/flash.c
View File

@@ -33,7 +33,11 @@
* @{
*/
#if defined (AT32F415xC)
#define SECTOR_SIZE 2048 /* this parameter depends on the specific model of the chip */
#else
#define SECTOR_SIZE 1024 /* this parameter depends on the specific model of the chip */
#endif
uint16_t flash_buf[SECTOR_SIZE / 2];

6
project/at_start_f415/examples/gpio/io_toggle/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/gpio/led_toggle/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/gpio/swjtag_remap/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/i2c/communication_dma/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/i2c/communication_int/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/i2c/communication_poll/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/i2c/eeprom/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/i2s/halfduplex_dma/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/i2s/halfduplex_interrupt/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

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