ArteryTek/AT32F415_Firmware_Library
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update version to v2.1.0

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Artery-MCU
2023-08-08 19:30:55 +08:00
parent d7bcb64bf8
commit f49a554036
408 changed files with 224076 additions and 1271 deletions
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2
project/at_start_f415/examples/spi/crc_transfer_polling/readme.txt
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@@ -13,4 +13,4 @@
pb14(miso) <---> pa6(miso)
pb15(mosi) <---> pa7(mosi)
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f415/examples/spi/crc_transfer_polling/src/at32f415_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/spi/fullduplex_polling/readme.txt
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@@ -13,4 +13,4 @@
pb14(miso) <---> pa6(miso)
pb15(mosi) <---> pa7(mosi)
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f415/examples/spi/fullduplex_polling/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/spi/halfduplex_interrupt/readme.txt
View File

@@ -12,4 +12,4 @@
pb13(sck) <---> pa5(sck)
pb14(miso) <---> pa7(mosi)
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f415/examples/spi/halfduplex_interrupt/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/spi/halfduplex_transceiver_switch/readme.txt
View File

@@ -13,4 +13,4 @@
pb13(sck) <---> pa5(sck)
pb14(miso) <---> pa7(mosi)
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f415/examples/spi/halfduplex_transceiver_switch/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/spi/only_receive_mode_polling/readme.txt
View File

@@ -12,4 +12,4 @@
pb13(sck) <---> pa5(sck)
pb15(mosi) <---> pa7(mosi)
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f415/examples/spi/only_receive_mode_polling/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/readme.txt
View File

@@ -14,4 +14,4 @@
pb13(sck) <---> pb3(sck)
pb14(miso) <---> pb5(mosi)
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/spi/w25q_flash/readme.txt
View File

@@ -14,4 +14,4 @@
- mosi <---> pb15
- usart1_tx <---> pa9
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f415/examples/spi/w25q_flash/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000