ArteryTek/AT32F415_Firmware_Library
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update version to v2.1.0

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Artery-MCU
2023-08-08 19:30:55 +08:00
parent d7bcb64bf8
commit f49a554036
408 changed files with 224076 additions and 1271 deletions
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2
project/at_start_f415/examples/exint/exint_config/readme.txt
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@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, shows how to configure
external interrupt lines. exint line (exint line0 pa0) are configured to generate
an interrupt on each rising edge. in the interrupt routine a led2/3/4 is toggled.
for more detailed information. please refer to the application note document AN0104.
for more detailed information. please refer to the application note document AN0104.

6
project/at_start_f415/examples/exint/exint_config/src/at32f415_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/exint/exint_software_trigger/readme.txt
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@@ -10,4 +10,4 @@
software trigger will be generate in tmr1 overflow interrupt.
led2 toggle means tmr1 overflow interrupt respond.
led3 and led4 toggle means exint line 4 interrupt respond.
for more detailed information. please refer to the application note document AN0104.
for more detailed information. please refer to the application note document AN0104.

6
project/at_start_f415/examples/exint/exint_software_trigger/src/at32f415_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000