update version to v2.1.0

project/at_start_f415/examples/crm/clock_failure_detection/readme.txt

@@ -8,4 +8,4 @@
   this demo is based on the at-start board, in this demo, swith sclk to
   pll based hick when hext clock failure occured. pa8 output crm_clkout_pll_div_4
   and led2 fresh per 200 ms.
-  for more detailed information. please refer to the application note document AN0117.
+  for more detailed information. please refer to the application note document AN0117.

project/at_start_f415/examples/crm/clock_failure_detection/src/at32f415_clock.c

@@ -28,9 +28,9 @@
 /**
   * @brief  system clock config program
   * @note   the system clock is configured as follow:
-  *         - system clock        = hext / 2 * pll_mult
-  *         - system clock source = pll (hext)
-  *         - hext                = 8000000
+  *         system clock (sclk)   = hext / 2 * pll_mult
+  *         system clock source   = pll (hext)
+  *         - hext                = HEXT_VALUE
   *         - sclk                = 144000000
   *         - ahbdiv              = 1
   *         - ahbclk              = 144000000

project/at_start_f415/examples/crm/clock_failure_detection/src/main.c

@@ -90,9 +90,9 @@ void clock_failure_detection_handler(void)
 /**
   * @brief  config sclk 144 mhz with hick clock source.
   * @note   the system clock is configured as follow:
-  *         - system clock        = hick / 2 * pll_mult
-  *         - system clock source = pll (hick)
-  *         - hick                = 8000000
+  *         system clock (sclk)   = hick / 2 * pll_mult
+  *         system clock source   = pll (hick)
+  *         - hick                = HICK_VALUE
   *         - sclk                = 144000000
   *         - ahbdiv              = 1
   *         - ahbclk              = 144000000

project/at_start_f415/examples/crm/pll_config2/readme.txt

@@ -8,4 +8,4 @@
   this demo is based on the at-start board, in this demo, 150 mhz sysclk
   configed by crm_pll_config2 function. pa8 output crm_clkout_pll_div_4. 
   led2 fresh per 100 ms.
-  for more detailed information. please refer to the application note document AN0117.
+  for more detailed information. please refer to the application note document AN0117.

project/at_start_f415/examples/crm/pll_config2/src/at32f415_clock.c

@@ -28,9 +28,9 @@
 /**
   * @brief  system clock config program
   * @note   the system clock is configured as follow:
-  *         - system clock        = hext / 2 * pll_mult
-  *         - system clock source = pll (hext)
-  *         - hext                = 8000000
+  *         system clock (sclk)   = hext / 2 * pll_mult
+  *         system clock source   = pll (hext)
+  *         - hext                = HEXT_VALUE
   *         - sclk                = 150000000
   *         - ahbdiv              = 1
   *         - ahbclk              = 150000000

project/at_start_f415/examples/crm/sysclk_switch/readme.txt

@@ -7,4 +7,4 @@
 
   this demo is based on the at-start board, in this demo, swith sclk by pressed
   button. led4 toggle, pa8 output crm_clkout_pll_div_4. led2 fresh per 100 ms.
-  for more detailed information. please refer to the application note document AN0117.
+  for more detailed information. please refer to the application note document AN0117.

project/at_start_f415/examples/crm/sysclk_switch/src/at32f415_clock.c

@@ -28,9 +28,9 @@
 /**
   * @brief  system clock config program
   * @note   the system clock is configured as follow:
-  *         - system clock        = hext / 2 * pll_mult
-  *         - system clock source = pll (hext)
-  *         - hext                = 8000000
+  *         system clock (sclk)   = hext / 2 * pll_mult
+  *         system clock source   = pll (hext)
+  *         - hext                = HEXT_VALUE
   *         - sclk                = 144000000
   *         - ahbdiv              = 1
   *         - ahbclk              = 144000000

project/at_start_f415/examples/crm/sysclk_switch/src/main.c

@@ -87,9 +87,9 @@ static void switch_system_clock(void)
 /**
   * @brief  config sclk 64 mhz with hick clock source.
   * @note   the system clock is configured as follow:
-  *         - system clock        = hick / 2 * pll_mult
-  *         - system clock source = pll (hick)
-  *         - hick                = 8000000
+  *         system clock (sclk)   = hick / 2 * pll_mult
+  *         system clock source   = pll (hick)
+  *         - hick                = HICK_VALUE
   *         - sclk                = 64000000
   *         - ahbdiv              = 1
   *         - ahbclk              = 64000000
@@ -164,9 +164,9 @@ static void sclk_64m_hick_config(void)
 /**
   * @brief  config sclk 96 mhz with hext clock source.
   * @note   the system clock is configured as follow:
-  *         - system clock        = hext / 2 * pll_mult
-  *         - system clock source = pll (hext)
-  *         - hick                = 8000000
+  *         system clock (sclk)   = hext / 2 * pll_mult
+  *         system clock source   = pll (hext)
+  *         - hext                = HEXT_VALUE
   *         - sclk                = 96000000
   *         - ahbdiv              = 1
   *         - ahbclk              = 96000000