ArteryTek/AT32F415_Firmware_Library
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update version to v2.1.0

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Artery-MCU
2023-08-08 19:30:55 +08:00
parent d7bcb64bf8
commit f49a554036
408 changed files with 224076 additions and 1271 deletions
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2
project/at_start_f415/examples/adc/current_vref_value_check/readme.txt
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@@ -9,4 +9,4 @@
the adc1 internal channel17 to check vref value.
the convert data as follow:
- adc1_ordinary_value ---> adc1_channel_17
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/current_vref_value_check/src/at32f415_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/adc/exint_trigger_partitioned/readme.txt
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@@ -17,4 +17,4 @@
trigger source:
- ordinary --> exint line11(pc11)
- preempt --> exint line15(pa15)
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/exint_trigger_partitioned/src/at32f415_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/adc/internal_temperature_sensor/readme.txt
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@@ -9,4 +9,4 @@
the internal_temperature_sensor.
the convert data as follow:
- adc1_ordinary_value ---> adc1_channel_16
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/internal_temperature_sensor/src/at32f415_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/readme.txt
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@@ -11,4 +11,4 @@
- adc1_ordinary_valuetab[0] ---> adc1_channel_4
- adc1_ordinary_valuetab[1] ---> adc1_channel_5
- adc1_ordinary_valuetab[2] ---> adc1_channel_6
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/src/at32f415_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/adc/software_trigger_repeat/readme.txt
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@@ -11,4 +11,4 @@
- adc1_ordinary_valuetab[0] ---> adc1_channel_4
- adc1_ordinary_valuetab[1] ---> adc1_channel_5
- adc1_ordinary_valuetab[2] ---> adc1_channel_6
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/software_trigger_repeat/src/at32f415_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/readme.txt
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@@ -15,4 +15,4 @@
- adc1_preempt_valuetab[n][0] ---> adc1_channel_7
- adc1_preempt_valuetab[n][1] ---> adc1_channel_8
- adc1_preempt_valuetab[n][2] ---> adc1_channel_9
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/src/at32f415_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/adc/voltage_monitoring/readme.txt
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@@ -12,4 +12,4 @@
- adc1_ordinary_valuetab[1] ---> adc1_channel_5
- adc1_ordinary_valuetab[2] ---> adc1_channel_6
the voltage monitoring channel is: adc1_channel_5
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/voltage_monitoring/src/at32f415_clock.c
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@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000