ArteryTek/AT32F415_Firmware_Library
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update version to v2.1.0

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This commit is contained in:
Artery-MCU
2023-08-08 19:30:55 +08:00
parent d7bcb64bf8
commit f49a554036
408 changed files with 224076 additions and 1271 deletions
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12
project/at32f415_board/at32f415_board.c
View File

@@ -93,16 +93,24 @@ static __IO uint32_t fac_ms;
PUTCHAR_PROTOTYPE
{
while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET);
usart_data_transmit(PRINT_UART, ch);
usart_data_transmit(PRINT_UART, (uint16_t)ch);
while(usart_flag_get(PRINT_UART, USART_TDC_FLAG) == RESET);
return ch;
}
#if (defined (__GNUC__) && !defined (__clang__)) || (defined (__ICCARM__))
#if defined (__GNUC__) && !defined (__clang__)
int _write(int fd, char *pbuffer, int size)
#elif defined ( __ICCARM__ )
#pragma module_name = "?__write"
int __write(int fd, char *pbuffer, int size)
#endif
{
for(int i = 0; i < size; i ++)
{
__io_putchar(*pbuffer++);
while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET);
usart_data_transmit(PRINT_UART, (uint16_t)(*pbuffer++));
while(usart_flag_get(PRINT_UART, USART_TDC_FLAG) == RESET);
}
return size;

2
project/at_start_f415/examples/adc/current_vref_value_check/readme.txt
View File

@@ -9,4 +9,4 @@
the adc1 internal channel17 to check vref value.
the convert data as follow:
- adc1_ordinary_value ---> adc1_channel_17
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/current_vref_value_check/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/adc/exint_trigger_partitioned/readme.txt
View File

@@ -17,4 +17,4 @@
trigger source:
- ordinary --> exint line11(pc11)
- preempt --> exint line15(pa15)
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/exint_trigger_partitioned/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/adc/internal_temperature_sensor/readme.txt
View File

@@ -9,4 +9,4 @@
the internal_temperature_sensor.
the convert data as follow:
- adc1_ordinary_value ---> adc1_channel_16
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/internal_temperature_sensor/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/readme.txt
View File

@@ -11,4 +11,4 @@
- adc1_ordinary_valuetab[0] ---> adc1_channel_4
- adc1_ordinary_valuetab[1] ---> adc1_channel_5
- adc1_ordinary_valuetab[2] ---> adc1_channel_6
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/adc/software_trigger_repeat/readme.txt
View File

@@ -11,4 +11,4 @@
- adc1_ordinary_valuetab[0] ---> adc1_channel_4
- adc1_ordinary_valuetab[1] ---> adc1_channel_5
- adc1_ordinary_valuetab[2] ---> adc1_channel_6
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/software_trigger_repeat/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/readme.txt
View File

@@ -15,4 +15,4 @@
- adc1_preempt_valuetab[n][0] ---> adc1_channel_7
- adc1_preempt_valuetab[n][1] ---> adc1_channel_8
- adc1_preempt_valuetab[n][2] ---> adc1_channel_9
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/adc/voltage_monitoring/readme.txt
View File

@@ -12,4 +12,4 @@
- adc1_ordinary_valuetab[1] ---> adc1_channel_5
- adc1_ordinary_valuetab[2] ---> adc1_channel_6
the voltage monitoring channel is: adc1_channel_5
for more detailed information. please refer to the application note document AN0115.
for more detailed information. please refer to the application note document AN0115.

6
project/at_start_f415/examples/adc/voltage_monitoring/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/can/communication_mode/readme.txt
View File

@@ -13,4 +13,4 @@
- can tx ---> pb9
- can rx ---> pb8
for more detailed information. please refer to the application note document AN0095.
for more detailed information. please refer to the application note document AN0095.

6
project/at_start_f415/examples/can/communication_mode/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/can/filter/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/can/loopback_mode/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

44
project/at_start_f415/examples/cmp/cycle_by_cycle_control/inc/at32f415_clock.h Normal file
View File

@@ -0,0 +1,44 @@
/**
**************************************************************************
* @file at32f415_clock.h
* @brief header file of clock program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_CLOCK_H
#define __AT32F415_CLOCK_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f415.h"
/* exported functions ------------------------------------------------------- */
void system_clock_config(void);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F415_CLOCK_H */

145
project/at_start_f415/examples/cmp/cycle_by_cycle_control/inc/at32f415_conf.h Normal file
View File

@@ -0,0 +1,145 @@
/**
**************************************************************************
* @file at32f415_conf.h
* @brief at32f415 config header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_CONF_H
#define __AT32F415_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief in the following line adjust the value of high speed exernal crystal (hext)
* used in your application
* tip: to avoid modifying this file each time you need to use different hext, you
* can define the hext value in your toolchain compiler preprocessor.
*/
#if !defined HEXT_VALUE
#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed exernal crystal in hz */
#endif
/**
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED
#define CMP_MODULE_ENABLED
#define TMR_MODULE_ENABLED
#define ERTC_MODULE_ENABLED
#define GPIO_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define USART_MODULE_ENABLED
#define PWC_MODULE_ENABLED
#define CAN_MODULE_ENABLED
#define ADC_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define DMA_MODULE_ENABLED
#define DEBUG_MODULE_ENABLED
#define FLASH_MODULE_ENABLED
#define CRC_MODULE_ENABLED
#define WWDT_MODULE_ENABLED
#define WDT_MODULE_ENABLED
#define EXINT_MODULE_ENABLED
#define SDIO_MODULE_ENABLED
#define USB_MODULE_ENABLED
#define MISC_MODULE_ENABLED
/* includes ------------------------------------------------------------------*/
#ifdef CRM_MODULE_ENABLED
#include "at32f415_crm.h"
#endif
#ifdef CMP_MODULE_ENABLED
#include "at32f415_cmp.h"
#endif
#ifdef TMR_MODULE_ENABLED
#include "at32f415_tmr.h"
#endif
#ifdef ERTC_MODULE_ENABLED
#include "at32f415_ertc.h"
#endif
#ifdef GPIO_MODULE_ENABLED
#include "at32f415_gpio.h"
#endif
#ifdef I2C_MODULE_ENABLED
#include "at32f415_i2c.h"
#endif
#ifdef USART_MODULE_ENABLED
#include "at32f415_usart.h"
#endif
#ifdef PWC_MODULE_ENABLED
#include "at32f415_pwc.h"
#endif
#ifdef CAN_MODULE_ENABLED
#include "at32f415_can.h"
#endif
#ifdef ADC_MODULE_ENABLED
#include "at32f415_adc.h"
#endif
#ifdef SPI_MODULE_ENABLED
#include "at32f415_spi.h"
#endif
#ifdef DMA_MODULE_ENABLED
#include "at32f415_dma.h"
#endif
#ifdef DEBUG_MODULE_ENABLED
#include "at32f415_debug.h"
#endif
#ifdef FLASH_MODULE_ENABLED
#include "at32f415_flash.h"
#endif
#ifdef CRC_MODULE_ENABLED
#include "at32f415_crc.h"
#endif
#ifdef WWDT_MODULE_ENABLED
#include "at32f415_wwdt.h"
#endif
#ifdef WDT_MODULE_ENABLED
#include "at32f415_wdt.h"
#endif
#ifdef EXINT_MODULE_ENABLED
#include "at32f415_exint.h"
#endif
#ifdef SDIO_MODULE_ENABLED
#include "at32f415_sdio.h"
#endif
#ifdef MISC_MODULE_ENABLED
#include "at32f415_misc.h"
#endif
#ifdef USB_MODULE_ENABLED
#include "at32f415_usb.h"
#endif
#ifdef __cplusplus
}
#endif
#endif /* __AT32F415_CONF_H */

56
project/at_start_f415/examples/cmp/cycle_by_cycle_control/inc/at32f415_int.h Normal file
View File

@@ -0,0 +1,56 @@
/**
**************************************************************************
* @file at32f415_int.h
* @brief header file of main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_INT_H
#define __AT32F415_INT_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f415.h"
/* exported types ------------------------------------------------------------*/
/* exported constants --------------------------------------------------------*/
/* exported macro ------------------------------------------------------------*/
/* exported functions ------------------------------------------------------- */
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
#ifdef __cplusplus
}
#endif
#endif

368
project/at_start_f415/examples/cmp/cycle_by_cycle_control/mdk_v5/cycle_by_cycle_control.uvoptx Normal file
View File

@@ -0,0 +1,368 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>cycle_by_cycle_control</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>0</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>0</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>0</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0AT32F415_256 -FS08000000 -FL040000 -FP0($$Device:-AT32F415RCT7$Flash\AT32F415_256.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
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497
project/at_start_f415/examples/cmp/cycle_by_cycle_control/mdk_v5/cycle_by_cycle_control.uvprojx Normal file
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@@ -0,0 +1,497 @@
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<GroupName>readme</GroupName>
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<FileName>readme.txt</FileName>
<FileType>5</FileType>
<FilePath>..\readme.txt</FilePath>
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<RTE>
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<LayerInfo>
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
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13
project/at_start_f415/examples/cmp/cycle_by_cycle_control/readme.txt Normal file
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@@ -0,0 +1,13 @@
/**
**************************************************************************
* @file readme.txt
* @brief readme
**************************************************************************
*/
this example shows how to use the comparator's cycle-by-cycle current control
function, and inernally connected to the tmr1 channel clear. connect the current
sensor to the cmp_in(pa1), the cmp_out(pa0) will output the result. when the
cmp_out is low level, tmr1_ch1(pa8) will output PWM; when the cmp_out is high level,
the PWM of tmr1_ch1 will be cleared. for more detailed information. please refer
to the application note document AN0046.

97
project/at_start_f415/examples/cmp/cycle_by_cycle_control/src/at32f415_clock.c Normal file
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@@ -0,0 +1,97 @@
/**
**************************************************************************
* @file at32f415_clock.c
* @brief system clock config program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f415_clock.h"
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000
* - apb2div = 2
* - apb2clk = 72000000
* - apb1div = 2
* - apb1clk = 72000000
* - pll_mult = 36
* - flash_wtcyc = 4 cycle
* @param none
* @retval none
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* config flash psr register */
flash_psr_set(FLASH_WAIT_CYCLE_4);
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */
while(crm_hext_stable_wait() == ERROR)
{
}
/* config pll clock resource */
crm_pll_config(CRM_PLL_SOURCE_HEXT_DIV, CRM_PLL_MULT_36);
/* enable pll */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
/* wait till pll is ready */
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
{
}
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb1_div_set(CRM_APB1_DIV_2);
/* enable auto step mode */
crm_auto_step_mode_enable(TRUE);
/* select pll as system clock source */
crm_sysclk_switch(CRM_SCLK_PLL);
/* wait till pll is used as system clock source */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
{
}
/* disable auto step mode */
crm_auto_step_mode_enable(FALSE);
/* update system_core_clock global variable */
system_core_clock_update();
}

140
project/at_start_f415/examples/cmp/cycle_by_cycle_control/src/at32f415_int.c Normal file
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@@ -0,0 +1,140 @@
/**
**************************************************************************
* @file at32f415_int.c
* @brief main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f415_int.h"
/** @addtogroup AT32F415_periph_examples
* @{
*/
/** @addtogroup 415_CMP_cycle_by_cycle_control
* @{
*/
/**
* @brief this function handles nmi exception.
* @param none
* @retval none
*/
void NMI_Handler(void)
{
}
/**
* @brief this function handles hard fault exception.
* @param none
* @retval none
*/
void HardFault_Handler(void)
{
/* go to infinite loop when hard fault exception occurs */
while(1)
{
}
}
/**
* @brief this function handles memory manage exception.
* @param none
* @retval none
*/
void MemManage_Handler(void)
{
/* go to infinite loop when memory manage exception occurs */
while(1)
{
}
}
/**
* @brief this function handles bus fault exception.
* @param none
* @retval none
*/
void BusFault_Handler(void)
{
/* go to infinite loop when bus fault exception occurs */
while(1)
{
}
}
/**
* @brief this function handles usage fault exception.
* @param none
* @retval none
*/
void UsageFault_Handler(void)
{
/* go to infinite loop when usage fault exception occurs */
while(1)
{
}
}
/**
* @brief this function handles svcall exception.
* @param none
* @retval none
*/
void SVC_Handler(void)
{
}
/**
* @brief this function handles debug monitor exception.
* @param none
* @retval none
*/
void DebugMon_Handler(void)
{
}
/**
* @brief this function handles pendsv_handler exception.
* @param none
* @retval none
*/
void PendSV_Handler(void)
{
}
/**
* @brief this function handles systick handler.
* @param none
* @retval none
*/
void SysTick_Handler(void)
{
}
/**
* @}
*/
/**
* @}
*/

156
project/at_start_f415/examples/cmp/cycle_by_cycle_control/src/main.c Normal file
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@@ -0,0 +1,156 @@
/**
**************************************************************************
* @file main.c
* @brief main program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f415_board.h"
#include "at32f415_clock.h"
/** @addtogroup AT32F415_periph_examples
* @{
*/
/** @addtogroup 415_CMP_cycle_by_cycle_control CMP_cycle_by_cycle_control
* @{
*/
gpio_init_type gpio_init_struct = {0};
/**
* @brief configures cmp
* @param none
* @retval none
*/
void cmp_config(void)
{
cmp_init_type cmp_init_struct;
/* gpioa peripheral clock enable */
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_IOMUX_PERIPH_CLOCK, TRUE);
/* configure pa1: pa1 is used as cmp1 non inveting input */
gpio_init_struct.gpio_pins = GPIO_PINS_1;
gpio_init_struct.gpio_mode = GPIO_MODE_ANALOG;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init(GPIOA, &gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_0;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init(GPIOA, &gpio_init_struct);
gpio_pin_remap_config(TMR1_CH1_CMP_GMUX_10, TRUE);
/* cmp peripheral clock enable */
crm_periph_clock_enable(CRM_CMP_PERIPH_CLOCK, TRUE);
/* cmp1 init: pa1 is used cmp1 inverting input */
cmp_default_para_init(&cmp_init_struct);
cmp_init_struct.cmp_inverting = CMP_INVERTING_VREFINT;
cmp_init_struct.cmp_output = CMP_OUTPUT_TMR1CHCLR;
cmp_init_struct.cmp_polarity = CMP_POL_NON_INVERTING;
cmp_init_struct.cmp_speed = CMP_SPEED_FAST;
cmp_init_struct.cmp_hysteresis = CMP_HYSTERESIS_NONE;
cmp_init(CMP1_SELECTION, &cmp_init_struct);
/* enable cmp1 */
cmp_enable(CMP1_SELECTION, TRUE);
}
/**
* @brief configures tmr1_ch1 as input
* @param none
* @retval none
*/
void tmr1_init(void)
{
tmr_output_config_type tmr_output_structure;
crm_periph_clock_enable(CRM_TMR1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_8;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init(GPIOA, &gpio_init_struct);
nvic_irq_enable(TMR1_CH_IRQn, 0, 1);
/* tmr1 time base configuration */
tmr_base_init(TMR1, 9999, 0);
tmr_cnt_dir_set(TMR1, TMR_COUNT_UP);
tmr_clock_source_div_set(TMR1, TMR_CLOCK_DIV1);
/* channel 4 configuration in pwm mode */
tmr_output_default_para_init(&tmr_output_structure);
tmr_output_structure.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_A;
tmr_output_structure.oc_idle_state = FALSE;
tmr_output_structure.occ_idle_state = FALSE;
tmr_output_structure.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
tmr_output_structure.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
tmr_output_structure.oc_output_state = TRUE;
tmr_output_structure.occ_output_state = FALSE;
tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_1, &tmr_output_structure);
tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_1, 5000);
tmr_output_channel_switch_select(TMR1, TMR_CH_SWITCH_SELECT_CXORAW_OFF);
tmr_output_channel_switch_set(TMR1, TMR_SELECT_CHANNEL_1, TRUE);
/* tmr1 output enable */
tmr_output_enable(TMR1, TRUE);
/* tmr1 counter enable */
tmr_counter_enable(TMR1, TRUE);
}
/**
* @brief main function.
* @param none
* @retval none
*/
int main(void)
{
system_clock_config();
at32_board_init();
/* cmp1 configuration */
cmp_config();
/* tmr1 configuration in input capture mode */
tmr1_init();
while (1)
{
}
}
/**
* @}
*/
/**
* @}
*/

6
project/at_start_f415/examples/cmp/deep_sleep_mode/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/cmp/output/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/cortex_m4/bit_band/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, modify the variables
by its bitband address and then read from bitband address. if the variables is
not the expected, led4 blink every 1s, else using bitband make the led2 toggle.
for more detailed information. please refer to the application note document AN0083.
for more detailed information. please refer to the application note document AN0083.

6
project/at_start_f415/examples/cortex_m4/bit_band/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/cortex_m4/cmsis_dsp/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, demonstrates the use the maximum,
minimum, mean, standard deviation, variance and matrix functions to calculate
statistical values of marks obtained in a class.for more detailed information.
please refer to the application note document AN0036.
please refer to the application note document AN0036.

6
project/at_start_f415/examples/cortex_m4/cmsis_dsp/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/cortex_m4/systick_interrupt/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/crc/calculation/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, shows how to use
crc calculation unit to get a crc code of a given buffer of data word(32-bit),
if get a correct crc value led3 will be turn on, else led4 will be turn on.
for more detailed information. please refer to the application note document AN0109.
for more detailed information. please refer to the application note document AN0109.

6
project/at_start_f415/examples/crc/calculation/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/crm/clock_failure_detection/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, swith sclk to
pll based hick when hext clock failure occured. pa8 output crm_clkout_pll_div_4
and led2 fresh per 200 ms.
for more detailed information. please refer to the application note document AN0117.
for more detailed information. please refer to the application note document AN0117.

6
project/at_start_f415/examples/crm/clock_failure_detection/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/crm/clock_failure_detection/src/main.c
View File

@@ -90,9 +90,9 @@ void clock_failure_detection_handler(void)
/**
* @brief config sclk 144 mhz with hick clock source.
* @note the system clock is configured as follow:
* - system clock = hick / 2 * pll_mult
* - system clock source = pll (hick)
* - hick = 8000000
* system clock (sclk) = hick / 2 * pll_mult
* system clock source = pll (hick)
* - hick = HICK_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/crm/pll_config2/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, 150 mhz sysclk
configed by crm_pll_config2 function. pa8 output crm_clkout_pll_div_4.
led2 fresh per 100 ms.
for more detailed information. please refer to the application note document AN0117.
for more detailed information. please refer to the application note document AN0117.

6
project/at_start_f415/examples/crm/pll_config2/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 150000000
* - ahbdiv = 1
* - ahbclk = 150000000

2
project/at_start_f415/examples/crm/sysclk_switch/readme.txt
View File

@@ -7,4 +7,4 @@
this demo is based on the at-start board, in this demo, swith sclk by pressed
button. led4 toggle, pa8 output crm_clkout_pll_div_4. led2 fresh per 100 ms.
for more detailed information. please refer to the application note document AN0117.
for more detailed information. please refer to the application note document AN0117.

6
project/at_start_f415/examples/crm/sysclk_switch/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

12
project/at_start_f415/examples/crm/sysclk_switch/src/main.c
View File

@@ -87,9 +87,9 @@ static void switch_system_clock(void)
/**
* @brief config sclk 64 mhz with hick clock source.
* @note the system clock is configured as follow:
* - system clock = hick / 2 * pll_mult
* - system clock source = pll (hick)
* - hick = 8000000
* system clock (sclk) = hick / 2 * pll_mult
* system clock source = pll (hick)
* - hick = HICK_VALUE
* - sclk = 64000000
* - ahbdiv = 1
* - ahbclk = 64000000
@@ -164,9 +164,9 @@ static void sclk_64m_hick_config(void)
/**
* @brief config sclk 96 mhz with hext clock source.
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hick = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 96000000
* - ahbdiv = 1
* - ahbclk = 96000000

6
project/at_start_f415/examples/debug/tmr1/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/dma/data_to_gpio_flexible/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/dma/data_to_gpio_flexible/src/main.c
View File

@@ -102,7 +102,7 @@ int main(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA2_CHANNEL1, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA2_CHANNEL1, DMA_FDT_INT, TRUE);
/* dma2 channel1 interrupt nvic init */

6
project/at_start_f415/examples/dma/flash_to_sram/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/dma/flash_to_sram/src/main.c
View File

@@ -117,7 +117,7 @@ int main(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL1, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
/* dma1 channel1 interrupt nvic init */

6
project/at_start_f415/examples/ertc/bpr_domain/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/ertc/bpr_domain/src/main.c
View File

@@ -61,7 +61,7 @@ int main(void)
system_clock_config();
/* initial the nvic priority group */
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
/* initialize uart */
uart_print_init(115200);

6
project/at_start_f415/examples/ertc/calendar/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/ertc/calendar/src/main.c
View File

@@ -59,7 +59,7 @@ int main(void)
system_clock_config();
/* initial the nvic priority group */
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
/* at board initial */
at32_board_init();

2
project/at_start_f415/examples/ertc/lick_calibration/readme.txt
View File

@@ -7,4 +7,4 @@
this demo is based on the at-start board, in this demo, shows how to use
timer to calibrate the lick clock. use usart1 to view calibrate information.
for more detailed information. please refer to the application note document AN0047.
for more detailed information. please refer to the application note document AN0047.

6
project/at_start_f415/examples/ertc/lick_calibration/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/ertc/lick_calibration/src/main.c
View File

@@ -54,7 +54,7 @@ int main(void)
system_clock_config();
/* initial the nvic priority group */
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
/* at board initial */
at32_board_init();

2
project/at_start_f415/examples/ertc/tamper/readme.txt
View File

@@ -7,4 +7,4 @@
this demo is based on the at-start board, in this demo, shows how to use the
tamper detection, the rising edge of the pc13 pin triggers an tamper event.
for more detailed information. please refer to the application note document AN0047.
for more detailed information. please refer to the application note document AN0047.

6
project/at_start_f415/examples/ertc/tamper/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/ertc/tamper/src/main.c
View File

@@ -60,7 +60,7 @@ int main(void)
system_clock_config();
/* initial the nvic priority group */
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
/* at board initial */
at32_board_init();

2
project/at_start_f415/examples/ertc/time_stamp/readme.txt
View File

@@ -7,4 +7,4 @@
this demo is based on the at-start board, in this demo, shows how to use
the time stamp, the rising edge of the pc13 pin triggers an time stamp event.
for more detailed information. please refer to the application note document AN0047.
for more detailed information. please refer to the application note document AN0047.

6
project/at_start_f415/examples/ertc/time_stamp/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/ertc/time_stamp/src/main.c
View File

@@ -49,7 +49,7 @@ int main(void)
system_clock_config();
/* initial the nvic priority group */
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
/* at board initial */
at32_board_init();

6
project/at_start_f415/examples/ertc/wakeup_timer/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/ertc/wakeup_timer/src/main.c
View File

@@ -50,7 +50,7 @@ int main(void)
system_clock_config();
/* initial the nvic priority group */
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
/* at board initial */
at32_board_init();

2
project/at_start_f415/examples/exint/exint_config/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, shows how to configure
external interrupt lines. exint line (exint line0 pa0) are configured to generate
an interrupt on each rising edge. in the interrupt routine a led2/3/4 is toggled.
for more detailed information. please refer to the application note document AN0104.
for more detailed information. please refer to the application note document AN0104.

6
project/at_start_f415/examples/exint/exint_config/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/exint/exint_software_trigger/readme.txt
View File

@@ -10,4 +10,4 @@
software trigger will be generate in tmr1 overflow interrupt.
led2 toggle means tmr1 overflow interrupt respond.
led3 and led4 toggle means exint line 4 interrupt respond.
for more detailed information. please refer to the application note document AN0104.
for more detailed information. please refer to the application note document AN0104.

6
project/at_start_f415/examples/exint/exint_software_trigger/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/flash/fap_enable/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/flash/flash_write_read/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

4
project/at_start_f415/examples/flash/flash_write_read/src/flash.c
View File

@@ -33,7 +33,11 @@
* @{
*/
#if defined (AT32F415xC)
#define SECTOR_SIZE 2048 /* this parameter depends on the specific model of the chip */
#else
#define SECTOR_SIZE 1024 /* this parameter depends on the specific model of the chip */
#endif
uint16_t flash_buf[SECTOR_SIZE / 2];

2
project/at_start_f415/examples/gpio/io_toggle/readme.txt
View File

@@ -6,4 +6,4 @@
*/
this demo is based on the at-start board, this demo toggle pa.01 forever,
to describes how to use scr and clr register for max io toggling.
to describes how to use scr and clr register for max io toggling.

6
project/at_start_f415/examples/gpio/io_toggle/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/gpio/led_toggle/readme.txt
View File

@@ -7,4 +7,4 @@
this demo is based on the at-start board, in this demo, configure systick
timer used for delay function.
for more detailed information. please refer to the application note document AN0119.
for more detailed information. please refer to the application note document AN0119.

6
project/at_start_f415/examples/gpio/led_toggle/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/gpio/swjtag_remap/readme.txt
View File

@@ -12,4 +12,4 @@
pb2 is pressed the swj-dp will be disabled. the swj-dp pins are configured
as output push-pull. the pa13(jtms/swdat), pa14(jtck/swclk), pa15(jtdi),
pb3(jtdo) and pb4(jtrst) pins are toggled in an infinite loop.
for more detailed information. please refer to the application note document AN0119.
for more detailed information. please refer to the application note document AN0119.

6
project/at_start_f415/examples/gpio/swjtag_remap/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/i2c/communication_dma/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/i2c/communication_int/readme.txt
View File

@@ -17,4 +17,4 @@
pin used:
1. scl --- pb6
2. sda --- pb7
2. sda --- pb7

6
project/at_start_f415/examples/i2c/communication_int/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/i2c/communication_poll/readme.txt
View File

@@ -17,4 +17,4 @@
pin used:
1. scl --- pb6
2. sda --- pb7
2. sda --- pb7

6
project/at_start_f415/examples/i2c/communication_poll/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/i2c/eeprom/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/i2s/halfduplex_dma/readme.txt
View File

@@ -14,4 +14,4 @@
- pb13 <---> pa5(ck)
- pb15 <---> pa7(sd)
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f415/examples/i2s/halfduplex_dma/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/i2s/halfduplex_interrupt/readme.txt
View File

@@ -14,4 +14,4 @@
- pb13 <---> pa5(ck)
- pb15 <---> pa7(sd)
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f415/examples/i2s/halfduplex_interrupt/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/readme.txt
View File

@@ -15,4 +15,4 @@
- pb13 <---> pa5(ck)
- pb15 <---> pa7(sd)
for more detailed information. please refer to the application note document AN0102.
for more detailed information. please refer to the application note document AN0102.

6
project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, shows how to exit
deepsleep mode by interrupt of rtc alarm.
for more detailed information. please refer to the application note document AN0100.
for more detailed information. please refer to the application note document AN0100.

6
project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/readme.txt
View File

@@ -10,4 +10,4 @@
the rising edge on pc13 will wake up deepsleep mode
for more detailed information. please refer to the application note document AN0100.
for more detailed information. please refer to the application note document AN0100.

6
project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/pwc/power_voltage_monitor/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, shows how to configure
the power voltage monitoring using external interrupt line.
for more detailed information. please refer to the application note document AN0100.
for more detailed information. please refer to the application note document AN0100.

6
project/at_start_f415/examples/pwc/power_voltage_monitor/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/pwc/sleep_tmr2/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

2
project/at_start_f415/examples/pwc/sleep_usart1/readme.txt
View File

@@ -8,4 +8,4 @@
this demo is based on the at-start board, in this demo, shows how to exit
sleep mode by interrupt of usart1 receive data buffer full.
for more detailed information. please refer to the application note document AN0100.
for more detailed information. please refer to the application note document AN0100.

6
project/at_start_f415/examples/pwc/sleep_usart1/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

6
project/at_start_f415/examples/pwc/standby_ertc_alarm/src/at32f415_clock.c
View File

@@ -28,9 +28,9 @@
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* system clock (sclk) = hext / 2 * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 144000000
* - ahbdiv = 1
* - ahbclk = 144000000

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