mirror of
https://github.com/ArteryTek/AT32F415_Firmware_Library.git
synced 2026-05-21 01:12:20 +00:00
update version to v2.1.6
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@@ -810,7 +810,7 @@ typedef struct
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/**
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* @brief crm reserved2 register, offset:0x40~0x34
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*/
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__IO uint32_t reserved2[4];
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__IO uint32_t reserved1[4];
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/**
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* @brief crm otg_extctrl register, offset:0x44
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@@ -829,7 +829,7 @@ typedef struct
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/**
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* @brief crm reserved3 register, offset:0x50~0x48
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*/
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__IO uint32_t reserved3[3];
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__IO uint32_t reserved2[3];
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/**
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* @brief crm misc2 register, offset:0x54
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@@ -207,7 +207,8 @@ typedef enum
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{
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DMA_DIR_PERIPHERAL_TO_MEMORY = 0x0000, /*!< dma data transfer direction:peripheral to memory */
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DMA_DIR_MEMORY_TO_PERIPHERAL = 0x0010, /*!< dma data transfer direction:memory to peripheral */
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DMA_DIR_MEMORY_TO_MEMORY = 0x4000 /*!< dma data transfer direction:memory to memory */
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DMA_DIR_MEMORY_TO_MEMORY = 0x4000 /*!< dma data transfer direction:memory to memory,
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note:if the direction is memory to memory,peripheral_base_addr as source and memory_base_addr as destnation */
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} dma_dir_type;
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/**
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@@ -90,7 +90,7 @@ extern "C" {
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/**
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* @brief compatible with older versions
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*/
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#define ERTC_WAT_CLK_CK_A_16BITS ERTC_WAT_CLK_CK_B_16BITS
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#define ERTC_WAT_CLK_CK_A_16BITS ERTC_WAT_CLK_CK_B_16BITS
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#define ERTC_WAT_CLK_CK_A_17BITS ERTC_WAT_CLK_CK_B_17BITS
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/**
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@@ -578,16 +578,18 @@ can_transmit_status_type can_transmit_status_get(can_type* can_x, can_tx_mailbox
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*/
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void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox)
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{
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uint32_t transmit_cancel_bit = 0;
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transmit_cancel_bit = can_x->tsts & (CAN_TSTS_TM0CT_VAL | CAN_TSTS_TM1CT_VAL | CAN_TSTS_TM2CT_VAL);
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switch (transmit_mailbox)
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{
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case CAN_TX_MAILBOX0:
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can_x->tsts = CAN_TSTS_TM0CT_VAL;
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can_x->tsts = transmit_cancel_bit | CAN_TSTS_TM0CT_VAL;
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break;
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case CAN_TX_MAILBOX1:
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can_x->tsts = CAN_TSTS_TM1CT_VAL;
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can_x->tsts = transmit_cancel_bit | CAN_TSTS_TM1CT_VAL;
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break;
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case CAN_TX_MAILBOX2:
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can_x->tsts = CAN_TSTS_TM2CT_VAL;
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can_x->tsts = transmit_cancel_bit | CAN_TSTS_TM2CT_VAL;
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break;
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default:
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break;
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@@ -1440,7 +1440,7 @@ flag_status ertc_flag_get(uint32_t flag)
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flag_status ertc_interrupt_flag_get(uint32_t flag)
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{
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__IO uint32_t iten = 0;
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switch(flag)
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{
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case ERTC_ALAF_FLAG:
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@@ -1458,7 +1458,7 @@ flag_status ertc_interrupt_flag_get(uint32_t flag)
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case ERTC_TP1F_FLAG:
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iten = ERTC->tamp_bit.tpien;
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break;
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default:
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break;
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}
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@@ -650,11 +650,11 @@ flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag)
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case I2C_ALERTF_FLAG:
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iten = i2c_x->ctrl2_bit.errien;
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break;
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default:
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break;
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}
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reg = flag >> 28;
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flag &= (uint32_t)0x00FFFFFF;
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@@ -699,9 +699,9 @@ flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag)
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* @retval none
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*/
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void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag)
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{
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{
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i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x0000DF00);
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if(flag & I2C_ADDR7F_FLAG)
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{
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UNUSED(i2c_x->sts1);
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@@ -486,6 +486,10 @@ void usb_ept_open(otg_global_type *usbx, usb_ept_info *ept_info)
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mps = USB_EPT0_MPS_8;
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}
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}
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if(ept_info->trans_type == EPT_ISO_TYPE)
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{
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OTG_DEVICE(usbx)->dctl |= 1 << 15;
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}
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/* endpoint direction is in */
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if(ept_info->inout == EPT_DIR_IN)
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{
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@@ -535,11 +539,22 @@ void usb_ept_close(otg_global_type *usbx, usb_ept_info *ept_info)
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if(ept_info->inout == EPT_DIR_IN)
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{
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OTG_DEVICE(usbx)->daintmsk &= ~(1 << ept_info->eptn);
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if(USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.eptena == SET)
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{
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USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.eptdis = TRUE;
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USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.snak = TRUE;
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}
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USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.usbacept = FALSE;
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}
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else
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{
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OTG_DEVICE(usbx)->daintmsk &= ~((1 << ept_info->eptn) << 16);
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if(USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.eptena == SET)
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{
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USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.eptdis = TRUE;
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USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.snak = TRUE;
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}
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USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.usbacept = FALSE;
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}
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}
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@@ -897,7 +912,10 @@ void usb_hc_enable(otg_global_type *usbx,
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{
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otg_hchannel_type *hch = USB_CHL(usbx, chn);
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otg_host_type *usb_host = OTG_HOST(usbx);
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/* clear old interrupt flag */
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hch->hcint = 0xFFFFFFFF;
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switch(type)
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{
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case EPT_CONTROL_TYPE:
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@@ -961,7 +979,7 @@ uint32_t usb_hch_read_interrupt(otg_global_type *usbx)
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*/
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void usb_host_disable(otg_global_type *usbx)
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{
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uint32_t i_index = 0, count = 0;
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uint32_t i_index = 0;
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otg_hchannel_type *hch;
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otg_host_type *usb_host = OTG_HOST(usbx);
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@@ -972,22 +990,10 @@ void usb_host_disable(otg_global_type *usbx)
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for(i_index = 0; i_index < 16; i_index ++)
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{
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hch = USB_CHL(usbx, i_index);
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hch->hcchar_bit.chdis = TRUE;
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hch->hcchar_bit.chena = FALSE;
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hch->hcchar_bit.eptdir = 0;
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}
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for(i_index = 0; i_index < 16; i_index ++)
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{
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hch = USB_CHL(usbx, i_index);
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hch->hcchar_bit.chdis = TRUE;
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hch->hcchar_bit.chena = TRUE;
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hch->hcchar_bit.eptdir = 0;
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do
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if(hch->hcchar_bit.chena == TRUE)
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{
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if(count ++ > 1000)
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break;
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}while(hch->hcchar_bit.chena);
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hch->hcchar_bit.chdis = TRUE;
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}
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}
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usb_host->haint = 0xFFFFFFFF;
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usbx->gintsts = 0xFFFFFFFF;
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@@ -1017,7 +1023,8 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn)
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if((usbx->gnptxsts_bit.nptxqspcavail) == 0)
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{
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usb_chh->hcchar_bit.chena = FALSE;
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usb_chh->hcchar_bit.chena = TRUE;
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if(usb_chh->hcchar_bit.chena != TRUE)
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usb_chh->hcchar_bit.chena = TRUE;
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do
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{
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if(count ++ > 1000)
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@@ -1026,7 +1033,8 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn)
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}
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else
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{
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usb_chh->hcchar_bit.chena = TRUE;
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if(usb_chh->hcchar_bit.chena != TRUE)
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usb_chh->hcchar_bit.chena = TRUE;
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}
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}
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else
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@@ -1035,7 +1043,8 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn)
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if((usb_host->hptxsts_bit.ptxqspcavil) == 0)
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{
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usb_chh->hcchar_bit.chena = FALSE;
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usb_chh->hcchar_bit.chena = TRUE;
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if(usb_chh->hcchar_bit.chena != TRUE)
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usb_chh->hcchar_bit.chena = TRUE;
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do
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{
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if(count ++ > 1000)
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@@ -1044,7 +1053,8 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn)
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}
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else
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{
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usb_chh->hcchar_bit.chena = TRUE;
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if(usb_chh->hcchar_bit.chena != TRUE)
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usb_chh->hcchar_bit.chena = TRUE;
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}
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}
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}
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