diff --git a/AT32F415_periph_lib_V2.0.8.chm b/AT32F415_periph_lib_V2.0.9.chm similarity index 62% rename from AT32F415_periph_lib_V2.0.8.chm rename to AT32F415_periph_lib_V2.0.9.chm index 89e5e2e..807098b 100644 Binary files a/AT32F415_periph_lib_V2.0.8.chm and b/AT32F415_periph_lib_V2.0.9.chm differ diff --git a/document/AT32F415固件库BSP&Pack应用指南.pdf b/document/AT32F415固件库BSP&Pack应用指南.pdf index eb41025..5b96371 100644 Binary files a/document/AT32F415固件库BSP&Pack应用指南.pdf and b/document/AT32F415固件库BSP&Pack应用指南.pdf differ diff --git a/document/ReleaseNotes_AT32F415_Firmware_Library.pdf b/document/ReleaseNotes_AT32F415_Firmware_Library.pdf index 7f7f002..dc7b25a 100644 Binary files a/document/ReleaseNotes_AT32F415_Firmware_Library.pdf and b/document/ReleaseNotes_AT32F415_Firmware_Library.pdf differ diff --git a/libraries/cmsis/cm4/device_support/at32f415.h b/libraries/cmsis/cm4/device_support/at32f415.h index 1175898..8ebfbc6 100644 --- a/libraries/cmsis/cm4/device_support/at32f415.h +++ b/libraries/cmsis/cm4/device_support/at32f415.h @@ -104,7 +104,7 @@ extern "C" { */ #define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ #define __AT32F415_LIBRARY_VERSION_MIDDLE (0x00) /*!< [23:16] middle version */ -#define __AT32F415_LIBRARY_VERSION_MINOR (0x08) /*!< [15:8] minor version */ +#define __AT32F415_LIBRARY_VERSION_MINOR (0x09) /*!< [15:8] minor version */ #define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24) | \ (__AT32F415_LIBRARY_VERSION_MIDDLE << 16) | \ diff --git a/libraries/cmsis/cm4/device_support/at32f415_conf_template.h b/libraries/cmsis/cm4/device_support/at32f415_conf_template.h index e3a1b45..16b4123 100644 --- a/libraries/cmsis/cm4/device_support/at32f415_conf_template.h +++ b/libraries/cmsis/cm4/device_support/at32f415_conf_template.h @@ -45,8 +45,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/libraries/drivers/inc/at32f415_flash.h b/libraries/drivers/inc/at32f415_flash.h index f2fb74b..1f53ba6 100644 --- a/libraries/drivers/inc/at32f415_flash.h +++ b/libraries/drivers/inc/at32f415_flash.h @@ -139,7 +139,7 @@ extern "C" { * - FLASH_WAIT_CYCLE_3 * - FLASH_WAIT_CYCLE_4 */ -#define flash_psr_set(wtcyc) (FLASH->psr = (uint32_t)(0x150 | wtcyc)) +#define flash_psr_set(wtcyc) (FLASH->psr = (uint32_t)(0x10 | wtcyc)) /** @defgroup FLASH_exported_types * @{ diff --git a/libraries/drivers/inc/at32f415_tmr.h b/libraries/drivers/inc/at32f415_tmr.h index e19f349..4df297c 100644 --- a/libraries/drivers/inc/at32f415_tmr.h +++ b/libraries/drivers/inc/at32f415_tmr.h @@ -236,7 +236,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** diff --git a/libraries/drivers/src/at32f415_ertc.c b/libraries/drivers/src/at32f415_ertc.c index 324bb9b..72678a5 100644 --- a/libraries/drivers/src/at32f415_ertc.c +++ b/libraries/drivers/src/at32f415_ertc.c @@ -320,7 +320,7 @@ error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t we return ERROR; } - /* Set the ertc_DR register */ + /* set the ertc_date register */ ERTC->date = reg.date; /* exit init mode */ @@ -1470,13 +1470,7 @@ void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data) reg = ERTC_BASE + 0x50 + (dt * 4); - /* disable write protection */ - ertc_write_protect_disable(); - *(__IO uint32_t *)reg = data; - - /* enable write protection */ - ertc_write_protect_enable(); } /** diff --git a/middlewares/usb_drivers/src/usbd_sdr.c b/middlewares/usb_drivers/src/usbd_sdr.c index b3690bd..3635599 100644 --- a/middlewares/usb_drivers/src/usbd_sdr.c +++ b/middlewares/usb_drivers/src/usbd_sdr.c @@ -156,6 +156,7 @@ static usb_sts_type usbd_set_address(usbd_core_type *udev) else { udev->device_addr = dev_addr; + usbd_set_device_addr(udev, udev->device_addr); if(dev_addr != 0) { diff --git a/middlewares/usb_drivers/src/usbh_ctrl.c b/middlewares/usb_drivers/src/usbh_ctrl.c index 31c71dc..644f220 100644 --- a/middlewares/usb_drivers/src/usbh_ctrl.c +++ b/middlewares/usb_drivers/src/usbh_ctrl.c @@ -159,6 +159,7 @@ usb_sts_type usbh_ctrl_setup_wait_handler(usbh_core_type *uhost, uint32_t *timeo uhost->ctrl.state = CONTROL_STATUS_IN; } } + uhost->ctrl.timer = uhost->timer; status = USB_OK; } else if(urb_state == URB_ERROR || urb_state == URB_NOTREADY) @@ -279,15 +280,13 @@ usb_sts_type usbh_ctrl_data_out_wait_handler(usbh_core_type *uhost, uint32_t tim { uhost->ctrl.state = CONTROL_DATA_OUT; } - else + + /* wait nak timeout 5s*/ + if((uhost->timer - uhost->ctrl.timer > CTRL_TIMEOUT) && (urb_state == URB_NOTREADY)) { - /* wait nak timeout 5s*/ - if(uhost->timer - uhost->ctrl.timer > CTRL_TIMEOUT) - { - uhost->ctrl.state = CONTROL_ERROR; - uhost->ctrl.sts = CTRL_XACTERR; - status = USB_ERROR; - } + uhost->ctrl.state = CONTROL_ERROR; + uhost->ctrl.sts = CTRL_XACTERR; + status = USB_ERROR; } return status; } @@ -388,15 +387,12 @@ usb_sts_type usbh_ctrl_status_out_wait_handler(usbh_core_type *uhost, uint32_t t { uhost->ctrl.state = CONTROL_STATUS_OUT; } - else + /* wait nak timeout 5s*/ + if((uhost->timer - uhost->ctrl.timer > CTRL_TIMEOUT) && (urb_state == URB_NOTREADY)) { - /* wait nak timeout 5s*/ - if(uhost->timer - uhost->ctrl.timer > CTRL_TIMEOUT) - { - uhost->ctrl.state = CONTROL_ERROR; - uhost->ctrl.sts = CTRL_XACTERR; - status = USB_ERROR; - } + uhost->ctrl.state = CONTROL_ERROR; + uhost->ctrl.sts = CTRL_XACTERR; + status = USB_ERROR; } return status; } @@ -468,7 +464,6 @@ usb_sts_type usbh_ctrl_transfer_loop(usbh_core_type *uhost) case CONTROL_DATA_IN: usbh_ctrl_data_in_handler(uhost); - uhost->ctrl.timer = uhost->timer; break; case CONTROL_DATA_IN_WAIT: @@ -477,7 +472,6 @@ usb_sts_type usbh_ctrl_transfer_loop(usbh_core_type *uhost) case CONTROL_DATA_OUT: usbh_ctrl_data_out_handler(uhost); - uhost->ctrl.timer = uhost->timer; break; case CONTROL_DATA_OUT_WAIT: @@ -486,7 +480,6 @@ usb_sts_type usbh_ctrl_transfer_loop(usbh_core_type *uhost) case CONTROL_STATUS_IN: usbh_ctrl_status_in_handler(uhost); - uhost->ctrl.timer = uhost->timer; break; case CONTROL_STATUS_IN_WAIT: @@ -495,7 +488,6 @@ usb_sts_type usbh_ctrl_transfer_loop(usbh_core_type *uhost) case CONTROL_STATUS_OUT: usbh_ctrl_status_out_handler(uhost); - uhost->ctrl.timer = uhost->timer; break; case CONTROL_STATUS_OUT_WAIT: diff --git a/project/at_start_f415/examples/adc/current_vref_value_check/inc/at32f415_conf.h b/project/at_start_f415/examples/adc/current_vref_value_check/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/adc/current_vref_value_check/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/adc/current_vref_value_check/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvoptx b/project/at_start_f415/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvoptx index e51a538..c68c72a 100644 --- a/project/at_start_f415/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvoptx +++ b/project/at_start_f415/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvprojx b/project/at_start_f415/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvprojx index 05801ed..768e9f2 100644 --- a/project/at_start_f415/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvprojx +++ b/project/at_start_f415/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/adc/current_vref_value_check/src/at32f415_clock.c b/project/at_start_f415/examples/adc/current_vref_value_check/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/adc/current_vref_value_check/src/at32f415_clock.c +++ b/project/at_start_f415/examples/adc/current_vref_value_check/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/adc/exint_trigger_partitioned/inc/at32f415_conf.h b/project/at_start_f415/examples/adc/exint_trigger_partitioned/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/adc/exint_trigger_partitioned/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/adc/exint_trigger_partitioned/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvoptx b/project/at_start_f415/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvoptx index 9f0d4ec..726cda5 100644 --- a/project/at_start_f415/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvoptx +++ b/project/at_start_f415/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvprojx b/project/at_start_f415/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvprojx index fc41984..3534e1f 100644 --- a/project/at_start_f415/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvprojx +++ b/project/at_start_f415/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/adc/exint_trigger_partitioned/src/at32f415_clock.c b/project/at_start_f415/examples/adc/exint_trigger_partitioned/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/adc/exint_trigger_partitioned/src/at32f415_clock.c +++ b/project/at_start_f415/examples/adc/exint_trigger_partitioned/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/adc/internal_temperature_sensor/inc/at32f415_conf.h b/project/at_start_f415/examples/adc/internal_temperature_sensor/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/adc/internal_temperature_sensor/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/adc/internal_temperature_sensor/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvoptx b/project/at_start_f415/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvoptx index ad6c0b6..8ada025 100644 --- a/project/at_start_f415/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvoptx +++ b/project/at_start_f415/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvprojx b/project/at_start_f415/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvprojx index ca24b12..24fa915 100644 --- a/project/at_start_f415/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvprojx +++ b/project/at_start_f415/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/adc/internal_temperature_sensor/src/at32f415_clock.c b/project/at_start_f415/examples/adc/internal_temperature_sensor/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/adc/internal_temperature_sensor/src/at32f415_clock.c +++ b/project/at_start_f415/examples/adc/internal_temperature_sensor/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/inc/at32f415_conf.h b/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvoptx b/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvoptx index b2a0cb7..51cc1f3 100644 --- a/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvoptx +++ b/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvprojx b/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvprojx index ae33c5d..126ff53 100644 --- a/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvprojx +++ b/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/src/at32f415_clock.c b/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/src/at32f415_clock.c +++ b/project/at_start_f415/examples/adc/repeat_conversion_loop_transfer/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/adc/software_trigger_repeat/inc/at32f415_conf.h b/project/at_start_f415/examples/adc/software_trigger_repeat/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/adc/software_trigger_repeat/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/adc/software_trigger_repeat/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvoptx b/project/at_start_f415/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvoptx index 0c0f5f3..3afdb9c 100644 --- a/project/at_start_f415/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvoptx +++ b/project/at_start_f415/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvprojx b/project/at_start_f415/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvprojx index 37ed7f3..09873bc 100644 --- a/project/at_start_f415/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvprojx +++ b/project/at_start_f415/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/adc/software_trigger_repeat/src/at32f415_clock.c b/project/at_start_f415/examples/adc/software_trigger_repeat/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/adc/software_trigger_repeat/src/at32f415_clock.c +++ b/project/at_start_f415/examples/adc/software_trigger_repeat/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/inc/at32f415_conf.h b/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvoptx b/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvoptx index 84620c7..215f6c1 100644 --- a/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvoptx +++ b/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvprojx b/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvprojx index ae1f869..c1edd25 100644 --- a/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvprojx +++ b/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/src/at32f415_clock.c b/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/src/at32f415_clock.c +++ b/project/at_start_f415/examples/adc/tmr_trigger_automatic_preempted/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/adc/voltage_monitoring/inc/at32f415_conf.h b/project/at_start_f415/examples/adc/voltage_monitoring/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/adc/voltage_monitoring/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/adc/voltage_monitoring/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvoptx b/project/at_start_f415/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvoptx index e7ec49f..88f5556 100644 --- a/project/at_start_f415/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvoptx +++ b/project/at_start_f415/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvprojx b/project/at_start_f415/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvprojx index 2df7254..7fd3475 100644 --- a/project/at_start_f415/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvprojx +++ b/project/at_start_f415/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/adc/voltage_monitoring/src/at32f415_clock.c b/project/at_start_f415/examples/adc/voltage_monitoring/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/adc/voltage_monitoring/src/at32f415_clock.c +++ b/project/at_start_f415/examples/adc/voltage_monitoring/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/can/communication_mode/inc/at32f415_conf.h b/project/at_start_f415/examples/can/communication_mode/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/can/communication_mode/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/can/communication_mode/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/can/communication_mode/mdk_v5/communication_mode.uvoptx b/project/at_start_f415/examples/can/communication_mode/mdk_v5/communication_mode.uvoptx index e773982..148d964 100644 --- a/project/at_start_f415/examples/can/communication_mode/mdk_v5/communication_mode.uvoptx +++ b/project/at_start_f415/examples/can/communication_mode/mdk_v5/communication_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/can/communication_mode/mdk_v5/communication_mode.uvprojx b/project/at_start_f415/examples/can/communication_mode/mdk_v5/communication_mode.uvprojx index 60e688e..5f067bc 100644 --- a/project/at_start_f415/examples/can/communication_mode/mdk_v5/communication_mode.uvprojx +++ b/project/at_start_f415/examples/can/communication_mode/mdk_v5/communication_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/can/communication_mode/src/at32f415_clock.c b/project/at_start_f415/examples/can/communication_mode/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/can/communication_mode/src/at32f415_clock.c +++ b/project/at_start_f415/examples/can/communication_mode/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/can/filter/inc/at32f415_conf.h b/project/at_start_f415/examples/can/filter/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/can/filter/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/can/filter/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/can/filter/mdk_v5/filter.uvoptx b/project/at_start_f415/examples/can/filter/mdk_v5/filter.uvoptx index b470f6f..c19fbe6 100644 --- a/project/at_start_f415/examples/can/filter/mdk_v5/filter.uvoptx +++ b/project/at_start_f415/examples/can/filter/mdk_v5/filter.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/can/filter/mdk_v5/filter.uvprojx b/project/at_start_f415/examples/can/filter/mdk_v5/filter.uvprojx index ab44fdd..f265a56 100644 --- a/project/at_start_f415/examples/can/filter/mdk_v5/filter.uvprojx +++ b/project/at_start_f415/examples/can/filter/mdk_v5/filter.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/can/filter/src/at32f415_clock.c b/project/at_start_f415/examples/can/filter/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/can/filter/src/at32f415_clock.c +++ b/project/at_start_f415/examples/can/filter/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/can/loopback_mode/inc/at32f415_conf.h b/project/at_start_f415/examples/can/loopback_mode/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/can/loopback_mode/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/can/loopback_mode/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/can/loopback_mode/mdk_v5/loopback_mode.uvoptx b/project/at_start_f415/examples/can/loopback_mode/mdk_v5/loopback_mode.uvoptx index 708b897..a9f5bad 100644 --- a/project/at_start_f415/examples/can/loopback_mode/mdk_v5/loopback_mode.uvoptx +++ b/project/at_start_f415/examples/can/loopback_mode/mdk_v5/loopback_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/can/loopback_mode/mdk_v5/loopback_mode.uvprojx b/project/at_start_f415/examples/can/loopback_mode/mdk_v5/loopback_mode.uvprojx index b9d2bd8..3672eb8 100644 --- a/project/at_start_f415/examples/can/loopback_mode/mdk_v5/loopback_mode.uvprojx +++ b/project/at_start_f415/examples/can/loopback_mode/mdk_v5/loopback_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/can/loopback_mode/src/at32f415_clock.c b/project/at_start_f415/examples/can/loopback_mode/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/can/loopback_mode/src/at32f415_clock.c +++ b/project/at_start_f415/examples/can/loopback_mode/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/cmp/deep_sleep_mode/inc/at32f415_conf.h b/project/at_start_f415/examples/cmp/deep_sleep_mode/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/cmp/deep_sleep_mode/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/cmp/deep_sleep_mode/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/cmp/deep_sleep_mode/mdk_v5/deep_sleep_mode.uvoptx b/project/at_start_f415/examples/cmp/deep_sleep_mode/mdk_v5/deep_sleep_mode.uvoptx index 5d7509e..3f2d4b0 100644 --- a/project/at_start_f415/examples/cmp/deep_sleep_mode/mdk_v5/deep_sleep_mode.uvoptx +++ b/project/at_start_f415/examples/cmp/deep_sleep_mode/mdk_v5/deep_sleep_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/cmp/deep_sleep_mode/mdk_v5/deep_sleep_mode.uvprojx b/project/at_start_f415/examples/cmp/deep_sleep_mode/mdk_v5/deep_sleep_mode.uvprojx index 19899b4..e8a2551 100644 --- a/project/at_start_f415/examples/cmp/deep_sleep_mode/mdk_v5/deep_sleep_mode.uvprojx +++ b/project/at_start_f415/examples/cmp/deep_sleep_mode/mdk_v5/deep_sleep_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/cmp/deep_sleep_mode/src/at32f415_clock.c b/project/at_start_f415/examples/cmp/deep_sleep_mode/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/cmp/deep_sleep_mode/src/at32f415_clock.c +++ b/project/at_start_f415/examples/cmp/deep_sleep_mode/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/cmp/output/inc/at32f415_conf.h b/project/at_start_f415/examples/cmp/output/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/cmp/output/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/cmp/output/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/cmp/output/mdk_v5/output.uvoptx b/project/at_start_f415/examples/cmp/output/mdk_v5/output.uvoptx index 9de2dc8..29b3114 100644 --- a/project/at_start_f415/examples/cmp/output/mdk_v5/output.uvoptx +++ b/project/at_start_f415/examples/cmp/output/mdk_v5/output.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/cmp/output/mdk_v5/output.uvprojx b/project/at_start_f415/examples/cmp/output/mdk_v5/output.uvprojx index b30f647..3368fbf 100644 --- a/project/at_start_f415/examples/cmp/output/mdk_v5/output.uvprojx +++ b/project/at_start_f415/examples/cmp/output/mdk_v5/output.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/cmp/output/src/at32f415_clock.c b/project/at_start_f415/examples/cmp/output/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/cmp/output/src/at32f415_clock.c +++ b/project/at_start_f415/examples/cmp/output/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/cortex_m4/bit_band/inc/at32f415_conf.h b/project/at_start_f415/examples/cortex_m4/bit_band/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/cortex_m4/bit_band/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/cortex_m4/bit_band/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvoptx b/project/at_start_f415/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvoptx index 6c02a5e..1a8bf21 100644 --- a/project/at_start_f415/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvoptx +++ b/project/at_start_f415/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvprojx b/project/at_start_f415/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvprojx index 1264cfe..d4b9800 100644 --- a/project/at_start_f415/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvprojx +++ b/project/at_start_f415/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/cortex_m4/bit_band/src/at32f415_clock.c b/project/at_start_f415/examples/cortex_m4/bit_band/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/cortex_m4/bit_band/src/at32f415_clock.c +++ b/project/at_start_f415/examples/cortex_m4/bit_band/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/cortex_m4/cmsis_dsp/inc/at32f415_conf.h b/project/at_start_f415/examples/cortex_m4/cmsis_dsp/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/cortex_m4/cmsis_dsp/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/cortex_m4/cmsis_dsp/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvoptx b/project/at_start_f415/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvoptx index 316dbfb..db50ac8 100644 --- a/project/at_start_f415/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvoptx +++ b/project/at_start_f415/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvprojx b/project/at_start_f415/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvprojx index d279084..7874922 100644 --- a/project/at_start_f415/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvprojx +++ b/project/at_start_f415/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -543,6 +543,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/cortex_m4/cmsis_dsp/src/at32f415_clock.c b/project/at_start_f415/examples/cortex_m4/cmsis_dsp/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/cortex_m4/cmsis_dsp/src/at32f415_clock.c +++ b/project/at_start_f415/examples/cortex_m4/cmsis_dsp/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/cortex_m4/systick_interrupt/inc/at32f415_conf.h b/project/at_start_f415/examples/cortex_m4/systick_interrupt/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/cortex_m4/systick_interrupt/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/cortex_m4/systick_interrupt/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvoptx b/project/at_start_f415/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvoptx index af7e010..510ed36 100644 --- a/project/at_start_f415/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvoptx +++ b/project/at_start_f415/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvprojx b/project/at_start_f415/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvprojx index f689933..a2f89bc 100644 --- a/project/at_start_f415/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvprojx +++ b/project/at_start_f415/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/cortex_m4/systick_interrupt/src/at32f415_clock.c b/project/at_start_f415/examples/cortex_m4/systick_interrupt/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/cortex_m4/systick_interrupt/src/at32f415_clock.c +++ b/project/at_start_f415/examples/cortex_m4/systick_interrupt/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/crc/calculation/inc/at32f415_conf.h b/project/at_start_f415/examples/crc/calculation/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/crc/calculation/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/crc/calculation/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/crc/calculation/mdk_v5/calculation.uvoptx b/project/at_start_f415/examples/crc/calculation/mdk_v5/calculation.uvoptx index 310756d..70d6f4e 100644 --- a/project/at_start_f415/examples/crc/calculation/mdk_v5/calculation.uvoptx +++ b/project/at_start_f415/examples/crc/calculation/mdk_v5/calculation.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/crc/calculation/mdk_v5/calculation.uvprojx b/project/at_start_f415/examples/crc/calculation/mdk_v5/calculation.uvprojx index d768627..78d7185 100644 --- a/project/at_start_f415/examples/crc/calculation/mdk_v5/calculation.uvprojx +++ b/project/at_start_f415/examples/crc/calculation/mdk_v5/calculation.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/crc/calculation/src/at32f415_clock.c b/project/at_start_f415/examples/crc/calculation/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/crc/calculation/src/at32f415_clock.c +++ b/project/at_start_f415/examples/crc/calculation/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/crm/clock_failure_detection/inc/at32f415_conf.h b/project/at_start_f415/examples/crm/clock_failure_detection/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/crm/clock_failure_detection/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/crm/clock_failure_detection/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvoptx b/project/at_start_f415/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvoptx index fab9933..8f201ae 100644 --- a/project/at_start_f415/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvoptx +++ b/project/at_start_f415/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvprojx b/project/at_start_f415/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvprojx index 4a89acb..690fff2 100644 --- a/project/at_start_f415/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvprojx +++ b/project/at_start_f415/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/crm/clock_failure_detection/src/at32f415_clock.c b/project/at_start_f415/examples/crm/clock_failure_detection/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/crm/clock_failure_detection/src/at32f415_clock.c +++ b/project/at_start_f415/examples/crm/clock_failure_detection/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/crm/clock_failure_detection/src/main.c b/project/at_start_f415/examples/crm/clock_failure_detection/src/main.c index 70ed9ba..224318e 100644 --- a/project/at_start_f415/examples/crm/clock_failure_detection/src/main.c +++ b/project/at_start_f415/examples/crm/clock_failure_detection/src/main.c @@ -107,12 +107,12 @@ void clock_failure_detection_handler(void) */ static void sclk_144m_hick_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); /* wait till hick is ready */ diff --git a/project/at_start_f415/examples/crm/pll_config2/inc/at32f415_conf.h b/project/at_start_f415/examples/crm/pll_config2/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/crm/pll_config2/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/crm/pll_config2/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/crm/pll_config2/mdk_v5/pll_config2.uvoptx b/project/at_start_f415/examples/crm/pll_config2/mdk_v5/pll_config2.uvoptx index b284ad7..cccc3bc 100644 --- a/project/at_start_f415/examples/crm/pll_config2/mdk_v5/pll_config2.uvoptx +++ b/project/at_start_f415/examples/crm/pll_config2/mdk_v5/pll_config2.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/crm/pll_config2/mdk_v5/pll_config2.uvprojx b/project/at_start_f415/examples/crm/pll_config2/mdk_v5/pll_config2.uvprojx index 04a9117..ab0a54f 100644 --- a/project/at_start_f415/examples/crm/pll_config2/mdk_v5/pll_config2.uvprojx +++ b/project/at_start_f415/examples/crm/pll_config2/mdk_v5/pll_config2.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/crm/pll_config2/src/at32f415_clock.c b/project/at_start_f415/examples/crm/pll_config2/src/at32f415_clock.c index fef1ec8..0dbd504 100644 --- a/project/at_start_f415/examples/crm/pll_config2/src/at32f415_clock.c +++ b/project/at_start_f415/examples/crm/pll_config2/src/at32f415_clock.c @@ -47,12 +47,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/crm/sysclk_switch/inc/at32f415_conf.h b/project/at_start_f415/examples/crm/sysclk_switch/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/crm/sysclk_switch/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/crm/sysclk_switch/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvoptx b/project/at_start_f415/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvoptx index 01862ce..e74521c 100644 --- a/project/at_start_f415/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvoptx +++ b/project/at_start_f415/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvprojx b/project/at_start_f415/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvprojx index 91d6729..fc1edea 100644 --- a/project/at_start_f415/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvprojx +++ b/project/at_start_f415/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/crm/sysclk_switch/src/at32f415_clock.c b/project/at_start_f415/examples/crm/sysclk_switch/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/crm/sysclk_switch/src/at32f415_clock.c +++ b/project/at_start_f415/examples/crm/sysclk_switch/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/crm/sysclk_switch/src/main.c b/project/at_start_f415/examples/crm/sysclk_switch/src/main.c index c7498c3..e7ca3c3 100644 --- a/project/at_start_f415/examples/crm/sysclk_switch/src/main.c +++ b/project/at_start_f415/examples/crm/sysclk_switch/src/main.c @@ -104,12 +104,12 @@ static void switch_system_clock(void) */ static void sclk_64m_hick_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_1); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_1); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); /* wait till hick is ready */ @@ -181,12 +181,12 @@ static void sclk_64m_hick_config(void) */ static void sclk_96m_hext_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_2); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_2); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/debug/tmr1/inc/at32f415_conf.h b/project/at_start_f415/examples/debug/tmr1/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/debug/tmr1/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/debug/tmr1/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/debug/tmr1/mdk_v5/tmr1.uvoptx b/project/at_start_f415/examples/debug/tmr1/mdk_v5/tmr1.uvoptx index c8878a0..f7057e6 100644 --- a/project/at_start_f415/examples/debug/tmr1/mdk_v5/tmr1.uvoptx +++ b/project/at_start_f415/examples/debug/tmr1/mdk_v5/tmr1.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/debug/tmr1/mdk_v5/tmr1.uvprojx b/project/at_start_f415/examples/debug/tmr1/mdk_v5/tmr1.uvprojx index 3fce662..9d233fe 100644 --- a/project/at_start_f415/examples/debug/tmr1/mdk_v5/tmr1.uvprojx +++ b/project/at_start_f415/examples/debug/tmr1/mdk_v5/tmr1.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/debug/tmr1/src/at32f415_clock.c b/project/at_start_f415/examples/debug/tmr1/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/debug/tmr1/src/at32f415_clock.c +++ b/project/at_start_f415/examples/debug/tmr1/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/dma/data_to_gpio_flexible/inc/at32f415_conf.h b/project/at_start_f415/examples/dma/data_to_gpio_flexible/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/dma/data_to_gpio_flexible/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/dma/data_to_gpio_flexible/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/dma/data_to_gpio_flexible/mdk_v5/data_to_gpio_flexible.uvoptx b/project/at_start_f415/examples/dma/data_to_gpio_flexible/mdk_v5/data_to_gpio_flexible.uvoptx index 097bc3b..8f4b003 100644 --- a/project/at_start_f415/examples/dma/data_to_gpio_flexible/mdk_v5/data_to_gpio_flexible.uvoptx +++ b/project/at_start_f415/examples/dma/data_to_gpio_flexible/mdk_v5/data_to_gpio_flexible.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/dma/data_to_gpio_flexible/mdk_v5/data_to_gpio_flexible.uvprojx b/project/at_start_f415/examples/dma/data_to_gpio_flexible/mdk_v5/data_to_gpio_flexible.uvprojx index 8c46a04..d6aaeed 100644 --- a/project/at_start_f415/examples/dma/data_to_gpio_flexible/mdk_v5/data_to_gpio_flexible.uvprojx +++ b/project/at_start_f415/examples/dma/data_to_gpio_flexible/mdk_v5/data_to_gpio_flexible.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/dma/data_to_gpio_flexible/src/at32f415_clock.c b/project/at_start_f415/examples/dma/data_to_gpio_flexible/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/dma/data_to_gpio_flexible/src/at32f415_clock.c +++ b/project/at_start_f415/examples/dma/data_to_gpio_flexible/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/dma/flash_to_sram/inc/at32f415_conf.h b/project/at_start_f415/examples/dma/flash_to_sram/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/dma/flash_to_sram/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/dma/flash_to_sram/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx b/project/at_start_f415/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx index 1165723..df899dd 100644 --- a/project/at_start_f415/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx +++ b/project/at_start_f415/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx b/project/at_start_f415/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx index d9efbe3..363a538 100644 --- a/project/at_start_f415/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx +++ b/project/at_start_f415/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/dma/flash_to_sram/src/at32f415_clock.c b/project/at_start_f415/examples/dma/flash_to_sram/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/dma/flash_to_sram/src/at32f415_clock.c +++ b/project/at_start_f415/examples/dma/flash_to_sram/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/ertc/bpr_domain/inc/at32f415_conf.h b/project/at_start_f415/examples/ertc/bpr_domain/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/ertc/bpr_domain/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/ertc/bpr_domain/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvoptx b/project/at_start_f415/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvoptx index 05b7b53..5f8b50e 100644 --- a/project/at_start_f415/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvoptx +++ b/project/at_start_f415/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvprojx b/project/at_start_f415/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvprojx index e5111cb..39f977a 100644 --- a/project/at_start_f415/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvprojx +++ b/project/at_start_f415/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/ertc/bpr_domain/src/at32f415_clock.c b/project/at_start_f415/examples/ertc/bpr_domain/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/ertc/bpr_domain/src/at32f415_clock.c +++ b/project/at_start_f415/examples/ertc/bpr_domain/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/ertc/calendar/inc/at32f415_conf.h b/project/at_start_f415/examples/ertc/calendar/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/ertc/calendar/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/ertc/calendar/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/ertc/calendar/mdk_v5/calendar.uvoptx b/project/at_start_f415/examples/ertc/calendar/mdk_v5/calendar.uvoptx index 643f810..dfaf6f0 100644 --- a/project/at_start_f415/examples/ertc/calendar/mdk_v5/calendar.uvoptx +++ b/project/at_start_f415/examples/ertc/calendar/mdk_v5/calendar.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/ertc/calendar/mdk_v5/calendar.uvprojx b/project/at_start_f415/examples/ertc/calendar/mdk_v5/calendar.uvprojx index 027ccef..eb639a3 100644 --- a/project/at_start_f415/examples/ertc/calendar/mdk_v5/calendar.uvprojx +++ b/project/at_start_f415/examples/ertc/calendar/mdk_v5/calendar.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/ertc/calendar/src/at32f415_clock.c b/project/at_start_f415/examples/ertc/calendar/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/ertc/calendar/src/at32f415_clock.c +++ b/project/at_start_f415/examples/ertc/calendar/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/ertc/lick_calibration/inc/at32f415_conf.h b/project/at_start_f415/examples/ertc/lick_calibration/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/ertc/lick_calibration/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/ertc/lick_calibration/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvoptx b/project/at_start_f415/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvoptx index 6a22c81..8c8e7ed 100644 --- a/project/at_start_f415/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvoptx +++ b/project/at_start_f415/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvprojx b/project/at_start_f415/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvprojx index c1253fb..66c3ea4 100644 --- a/project/at_start_f415/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvprojx +++ b/project/at_start_f415/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/ertc/lick_calibration/src/at32f415_clock.c b/project/at_start_f415/examples/ertc/lick_calibration/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/ertc/lick_calibration/src/at32f415_clock.c +++ b/project/at_start_f415/examples/ertc/lick_calibration/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/ertc/tamper/inc/at32f415_conf.h b/project/at_start_f415/examples/ertc/tamper/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/ertc/tamper/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/ertc/tamper/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/ertc/tamper/mdk_v5/tamper.uvoptx b/project/at_start_f415/examples/ertc/tamper/mdk_v5/tamper.uvoptx index 6eacdb1..eb70759 100644 --- a/project/at_start_f415/examples/ertc/tamper/mdk_v5/tamper.uvoptx +++ b/project/at_start_f415/examples/ertc/tamper/mdk_v5/tamper.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/ertc/tamper/mdk_v5/tamper.uvprojx b/project/at_start_f415/examples/ertc/tamper/mdk_v5/tamper.uvprojx index 2908358..c936203 100644 --- a/project/at_start_f415/examples/ertc/tamper/mdk_v5/tamper.uvprojx +++ b/project/at_start_f415/examples/ertc/tamper/mdk_v5/tamper.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/ertc/tamper/src/at32f415_clock.c b/project/at_start_f415/examples/ertc/tamper/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/ertc/tamper/src/at32f415_clock.c +++ b/project/at_start_f415/examples/ertc/tamper/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/ertc/time_stamp/inc/at32f415_conf.h b/project/at_start_f415/examples/ertc/time_stamp/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/ertc/time_stamp/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/ertc/time_stamp/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/ertc/time_stamp/mdk_v5/time_stamp.uvoptx b/project/at_start_f415/examples/ertc/time_stamp/mdk_v5/time_stamp.uvoptx index b97ce5b..2faab37 100644 --- a/project/at_start_f415/examples/ertc/time_stamp/mdk_v5/time_stamp.uvoptx +++ b/project/at_start_f415/examples/ertc/time_stamp/mdk_v5/time_stamp.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/ertc/time_stamp/mdk_v5/time_stamp.uvprojx b/project/at_start_f415/examples/ertc/time_stamp/mdk_v5/time_stamp.uvprojx index bd6534f..b96f3f5 100644 --- a/project/at_start_f415/examples/ertc/time_stamp/mdk_v5/time_stamp.uvprojx +++ b/project/at_start_f415/examples/ertc/time_stamp/mdk_v5/time_stamp.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/ertc/time_stamp/src/at32f415_clock.c b/project/at_start_f415/examples/ertc/time_stamp/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/ertc/time_stamp/src/at32f415_clock.c +++ b/project/at_start_f415/examples/ertc/time_stamp/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/ertc/wakeup_timer/inc/at32f415_conf.h b/project/at_start_f415/examples/ertc/wakeup_timer/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/ertc/wakeup_timer/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/ertc/wakeup_timer/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvoptx b/project/at_start_f415/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvoptx index 59ff682..02a78db 100644 --- a/project/at_start_f415/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvoptx +++ b/project/at_start_f415/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvprojx b/project/at_start_f415/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvprojx index 2038461..874b00c 100644 --- a/project/at_start_f415/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvprojx +++ b/project/at_start_f415/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/ertc/wakeup_timer/src/at32f415_clock.c b/project/at_start_f415/examples/ertc/wakeup_timer/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/ertc/wakeup_timer/src/at32f415_clock.c +++ b/project/at_start_f415/examples/ertc/wakeup_timer/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/exint/exint_config/inc/at32f415_conf.h b/project/at_start_f415/examples/exint/exint_config/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/exint/exint_config/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/exint/exint_config/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/exint/exint_config/mdk_v5/exint_config.uvoptx b/project/at_start_f415/examples/exint/exint_config/mdk_v5/exint_config.uvoptx index 13e8b52..35cf2d6 100644 --- a/project/at_start_f415/examples/exint/exint_config/mdk_v5/exint_config.uvoptx +++ b/project/at_start_f415/examples/exint/exint_config/mdk_v5/exint_config.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/exint/exint_config/mdk_v5/exint_config.uvprojx b/project/at_start_f415/examples/exint/exint_config/mdk_v5/exint_config.uvprojx index 9cbce7a..c9bf746 100644 --- a/project/at_start_f415/examples/exint/exint_config/mdk_v5/exint_config.uvprojx +++ b/project/at_start_f415/examples/exint/exint_config/mdk_v5/exint_config.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/exint/exint_config/src/at32f415_clock.c b/project/at_start_f415/examples/exint/exint_config/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/exint/exint_config/src/at32f415_clock.c +++ b/project/at_start_f415/examples/exint/exint_config/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/exint/exint_software_trigger/inc/at32f415_conf.h b/project/at_start_f415/examples/exint/exint_software_trigger/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/exint/exint_software_trigger/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/exint/exint_software_trigger/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvoptx b/project/at_start_f415/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvoptx index 3fc8194..828d7a6 100644 --- a/project/at_start_f415/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvoptx +++ b/project/at_start_f415/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvprojx b/project/at_start_f415/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvprojx index c979faa..9019998 100644 --- a/project/at_start_f415/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvprojx +++ b/project/at_start_f415/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/exint/exint_software_trigger/src/at32f415_clock.c b/project/at_start_f415/examples/exint/exint_software_trigger/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/exint/exint_software_trigger/src/at32f415_clock.c +++ b/project/at_start_f415/examples/exint/exint_software_trigger/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/flash/fap_enable/inc/at32f415_conf.h b/project/at_start_f415/examples/flash/fap_enable/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/flash/fap_enable/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/flash/fap_enable/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/flash/fap_enable/mdk_v5/fap_enable.uvoptx b/project/at_start_f415/examples/flash/fap_enable/mdk_v5/fap_enable.uvoptx index 65669cd..b56e2d4 100644 --- a/project/at_start_f415/examples/flash/fap_enable/mdk_v5/fap_enable.uvoptx +++ b/project/at_start_f415/examples/flash/fap_enable/mdk_v5/fap_enable.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/flash/fap_enable/mdk_v5/fap_enable.uvprojx b/project/at_start_f415/examples/flash/fap_enable/mdk_v5/fap_enable.uvprojx index 7a515f0..920d4ad 100644 --- a/project/at_start_f415/examples/flash/fap_enable/mdk_v5/fap_enable.uvprojx +++ b/project/at_start_f415/examples/flash/fap_enable/mdk_v5/fap_enable.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ fap_enable + + + + + 0 1 diff --git a/project/at_start_f415/examples/flash/fap_enable/src/at32f415_clock.c b/project/at_start_f415/examples/flash/fap_enable/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/flash/fap_enable/src/at32f415_clock.c +++ b/project/at_start_f415/examples/flash/fap_enable/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/flash/flash_write_read/inc/at32f415_conf.h b/project/at_start_f415/examples/flash/flash_write_read/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/flash/flash_write_read/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/flash/flash_write_read/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvoptx b/project/at_start_f415/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvoptx index 62f7fa5..6f97921 100644 --- a/project/at_start_f415/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvoptx +++ b/project/at_start_f415/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvprojx b/project/at_start_f415/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvprojx index d2dfb0b..657c81f 100644 --- a/project/at_start_f415/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvprojx +++ b/project/at_start_f415/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/flash/flash_write_read/src/at32f415_clock.c b/project/at_start_f415/examples/flash/flash_write_read/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/flash/flash_write_read/src/at32f415_clock.c +++ b/project/at_start_f415/examples/flash/flash_write_read/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/gpio/io_toggle/inc/at32f415_conf.h b/project/at_start_f415/examples/gpio/io_toggle/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/gpio/io_toggle/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/gpio/io_toggle/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/gpio/io_toggle/mdk_v5/io_toggle.uvoptx b/project/at_start_f415/examples/gpio/io_toggle/mdk_v5/io_toggle.uvoptx index 16206db..1fb1544 100644 --- a/project/at_start_f415/examples/gpio/io_toggle/mdk_v5/io_toggle.uvoptx +++ b/project/at_start_f415/examples/gpio/io_toggle/mdk_v5/io_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/gpio/io_toggle/mdk_v5/io_toggle.uvprojx b/project/at_start_f415/examples/gpio/io_toggle/mdk_v5/io_toggle.uvprojx index a91a718..5051394 100644 --- a/project/at_start_f415/examples/gpio/io_toggle/mdk_v5/io_toggle.uvprojx +++ b/project/at_start_f415/examples/gpio/io_toggle/mdk_v5/io_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/gpio/io_toggle/src/at32f415_clock.c b/project/at_start_f415/examples/gpio/io_toggle/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/gpio/io_toggle/src/at32f415_clock.c +++ b/project/at_start_f415/examples/gpio/io_toggle/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/gpio/led_toggle/inc/at32f415_conf.h b/project/at_start_f415/examples/gpio/led_toggle/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/gpio/led_toggle/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/gpio/led_toggle/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/gpio/led_toggle/mdk_v5/led_toggle.uvoptx b/project/at_start_f415/examples/gpio/led_toggle/mdk_v5/led_toggle.uvoptx index 08bd747..1b4db6a 100644 --- a/project/at_start_f415/examples/gpio/led_toggle/mdk_v5/led_toggle.uvoptx +++ b/project/at_start_f415/examples/gpio/led_toggle/mdk_v5/led_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/gpio/led_toggle/mdk_v5/led_toggle.uvprojx b/project/at_start_f415/examples/gpio/led_toggle/mdk_v5/led_toggle.uvprojx index bfc192e..d356b5b 100644 --- a/project/at_start_f415/examples/gpio/led_toggle/mdk_v5/led_toggle.uvprojx +++ b/project/at_start_f415/examples/gpio/led_toggle/mdk_v5/led_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/gpio/led_toggle/src/at32f415_clock.c b/project/at_start_f415/examples/gpio/led_toggle/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/gpio/led_toggle/src/at32f415_clock.c +++ b/project/at_start_f415/examples/gpio/led_toggle/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/gpio/swjtag_remap/inc/at32f415_conf.h b/project/at_start_f415/examples/gpio/swjtag_remap/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/gpio/swjtag_remap/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/gpio/swjtag_remap/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/gpio/swjtag_remap/mdk_v5/swjtag_remap.uvoptx b/project/at_start_f415/examples/gpio/swjtag_remap/mdk_v5/swjtag_remap.uvoptx index a284fb1..ada99a6 100644 --- a/project/at_start_f415/examples/gpio/swjtag_remap/mdk_v5/swjtag_remap.uvoptx +++ b/project/at_start_f415/examples/gpio/swjtag_remap/mdk_v5/swjtag_remap.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/gpio/swjtag_remap/mdk_v5/swjtag_remap.uvprojx b/project/at_start_f415/examples/gpio/swjtag_remap/mdk_v5/swjtag_remap.uvprojx index d12e036..f7ba43a 100644 --- a/project/at_start_f415/examples/gpio/swjtag_remap/mdk_v5/swjtag_remap.uvprojx +++ b/project/at_start_f415/examples/gpio/swjtag_remap/mdk_v5/swjtag_remap.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/gpio/swjtag_remap/src/at32f415_clock.c b/project/at_start_f415/examples/gpio/swjtag_remap/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/gpio/swjtag_remap/src/at32f415_clock.c +++ b/project/at_start_f415/examples/gpio/swjtag_remap/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/i2c/communication_dma/inc/at32f415_conf.h b/project/at_start_f415/examples/i2c/communication_dma/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/i2c/communication_dma/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/i2c/communication_dma/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/i2c/communication_dma/mdk_v5/communication_dma.uvoptx b/project/at_start_f415/examples/i2c/communication_dma/mdk_v5/communication_dma.uvoptx index f3cd534..9a15e4f 100644 --- a/project/at_start_f415/examples/i2c/communication_dma/mdk_v5/communication_dma.uvoptx +++ b/project/at_start_f415/examples/i2c/communication_dma/mdk_v5/communication_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/i2c/communication_dma/mdk_v5/communication_dma.uvprojx b/project/at_start_f415/examples/i2c/communication_dma/mdk_v5/communication_dma.uvprojx index 22da2ca..b86cbf7 100644 --- a/project/at_start_f415/examples/i2c/communication_dma/mdk_v5/communication_dma.uvprojx +++ b/project/at_start_f415/examples/i2c/communication_dma/mdk_v5/communication_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/i2c/communication_dma/src/at32f415_clock.c b/project/at_start_f415/examples/i2c/communication_dma/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/i2c/communication_dma/src/at32f415_clock.c +++ b/project/at_start_f415/examples/i2c/communication_dma/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/i2c/communication_int/inc/at32f415_conf.h b/project/at_start_f415/examples/i2c/communication_int/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/i2c/communication_int/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/i2c/communication_int/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/i2c/communication_int/mdk_v5/communication_int.uvoptx b/project/at_start_f415/examples/i2c/communication_int/mdk_v5/communication_int.uvoptx index e3ad1d1..da50c3c 100644 --- a/project/at_start_f415/examples/i2c/communication_int/mdk_v5/communication_int.uvoptx +++ b/project/at_start_f415/examples/i2c/communication_int/mdk_v5/communication_int.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/i2c/communication_int/mdk_v5/communication_int.uvprojx b/project/at_start_f415/examples/i2c/communication_int/mdk_v5/communication_int.uvprojx index 6598a44..5ff1b10 100644 --- a/project/at_start_f415/examples/i2c/communication_int/mdk_v5/communication_int.uvprojx +++ b/project/at_start_f415/examples/i2c/communication_int/mdk_v5/communication_int.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/i2c/communication_int/src/at32f415_clock.c b/project/at_start_f415/examples/i2c/communication_int/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/i2c/communication_int/src/at32f415_clock.c +++ b/project/at_start_f415/examples/i2c/communication_int/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/i2c/communication_poll/inc/at32f415_conf.h b/project/at_start_f415/examples/i2c/communication_poll/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/i2c/communication_poll/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/i2c/communication_poll/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/i2c/communication_poll/mdk_v5/communication_poll.uvoptx b/project/at_start_f415/examples/i2c/communication_poll/mdk_v5/communication_poll.uvoptx index 37d5512..1a06117 100644 --- a/project/at_start_f415/examples/i2c/communication_poll/mdk_v5/communication_poll.uvoptx +++ b/project/at_start_f415/examples/i2c/communication_poll/mdk_v5/communication_poll.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/i2c/communication_poll/mdk_v5/communication_poll.uvprojx b/project/at_start_f415/examples/i2c/communication_poll/mdk_v5/communication_poll.uvprojx index 633b7cb..72a0ec2 100644 --- a/project/at_start_f415/examples/i2c/communication_poll/mdk_v5/communication_poll.uvprojx +++ b/project/at_start_f415/examples/i2c/communication_poll/mdk_v5/communication_poll.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/i2c/communication_poll/src/at32f415_clock.c b/project/at_start_f415/examples/i2c/communication_poll/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/i2c/communication_poll/src/at32f415_clock.c +++ b/project/at_start_f415/examples/i2c/communication_poll/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/i2c/eeprom/inc/at32f415_conf.h b/project/at_start_f415/examples/i2c/eeprom/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/i2c/eeprom/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/i2c/eeprom/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/i2c/eeprom/mdk_v5/eeprom.uvoptx b/project/at_start_f415/examples/i2c/eeprom/mdk_v5/eeprom.uvoptx index 5897b8a..c2e11ea 100644 --- a/project/at_start_f415/examples/i2c/eeprom/mdk_v5/eeprom.uvoptx +++ b/project/at_start_f415/examples/i2c/eeprom/mdk_v5/eeprom.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/i2c/eeprom/mdk_v5/eeprom.uvprojx b/project/at_start_f415/examples/i2c/eeprom/mdk_v5/eeprom.uvprojx index 8c54116..4b4f3bf 100644 --- a/project/at_start_f415/examples/i2c/eeprom/mdk_v5/eeprom.uvprojx +++ b/project/at_start_f415/examples/i2c/eeprom/mdk_v5/eeprom.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/i2c/eeprom/src/at32f415_clock.c b/project/at_start_f415/examples/i2c/eeprom/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/i2c/eeprom/src/at32f415_clock.c +++ b/project/at_start_f415/examples/i2c/eeprom/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/i2s/halfduplex_dma/inc/at32f415_conf.h b/project/at_start_f415/examples/i2s/halfduplex_dma/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/i2s/halfduplex_dma/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/i2s/halfduplex_dma/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvoptx b/project/at_start_f415/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvoptx index 13ff814..6e816a0 100644 --- a/project/at_start_f415/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvoptx +++ b/project/at_start_f415/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvprojx b/project/at_start_f415/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvprojx index 39f18b1..333d143 100644 --- a/project/at_start_f415/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvprojx +++ b/project/at_start_f415/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -479,4 +479,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/i2s/halfduplex_dma/src/at32f415_clock.c b/project/at_start_f415/examples/i2s/halfduplex_dma/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/i2s/halfduplex_dma/src/at32f415_clock.c +++ b/project/at_start_f415/examples/i2s/halfduplex_dma/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/i2s/halfduplex_interrupt/inc/at32f415_conf.h b/project/at_start_f415/examples/i2s/halfduplex_interrupt/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/i2s/halfduplex_interrupt/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/i2s/halfduplex_interrupt/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx b/project/at_start_f415/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx index 88276d8..e407ef8 100644 --- a/project/at_start_f415/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx +++ b/project/at_start_f415/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx b/project/at_start_f415/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx index 07f7926..94024fe 100644 --- a/project/at_start_f415/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx +++ b/project/at_start_f415/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/i2s/halfduplex_interrupt/src/at32f415_clock.c b/project/at_start_f415/examples/i2s/halfduplex_interrupt/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/i2s/halfduplex_interrupt/src/at32f415_clock.c +++ b/project/at_start_f415/examples/i2s/halfduplex_interrupt/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/inc/at32f415_conf.h b/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvoptx b/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvoptx index 7e17d1e..53c8f04 100644 --- a/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvoptx +++ b/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvprojx b/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvprojx index 20760b2..781ac0c 100644 --- a/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvprojx +++ b/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f415_clock.c b/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f415_clock.c +++ b/project/at_start_f415/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/inc/at32f415_conf.h b/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvoptx b/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvoptx index 58ea6a6..15c12d5 100644 --- a/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvoptx +++ b/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvprojx b/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvprojx index 3083bc2..0deebd4 100644 --- a/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvprojx +++ b/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/src/at32f415_clock.c b/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/src/at32f415_clock.c +++ b/project/at_start_f415/examples/pwc/deepsleep_ertc_alarm/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/inc/at32f415_conf.h b/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvoptx b/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvoptx index 44170f8..3e7dda1 100644 --- a/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvoptx +++ b/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvprojx b/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvprojx index 0969cbd..98dc043 100644 --- a/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvprojx +++ b/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/src/at32f415_clock.c b/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/src/at32f415_clock.c +++ b/project/at_start_f415/examples/pwc/deepsleep_ertc_tamper/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/pwc/power_voltage_monitor/inc/at32f415_conf.h b/project/at_start_f415/examples/pwc/power_voltage_monitor/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/pwc/power_voltage_monitor/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/pwc/power_voltage_monitor/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvoptx b/project/at_start_f415/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvoptx index 18059c5..181af9c 100644 --- a/project/at_start_f415/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvoptx +++ b/project/at_start_f415/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvprojx b/project/at_start_f415/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvprojx index 12f832d..0b23cf0 100644 --- a/project/at_start_f415/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvprojx +++ b/project/at_start_f415/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/pwc/power_voltage_monitor/src/at32f415_clock.c b/project/at_start_f415/examples/pwc/power_voltage_monitor/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/pwc/power_voltage_monitor/src/at32f415_clock.c +++ b/project/at_start_f415/examples/pwc/power_voltage_monitor/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/pwc/sleep_tmr2/inc/at32f415_conf.h b/project/at_start_f415/examples/pwc/sleep_tmr2/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/pwc/sleep_tmr2/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/pwc/sleep_tmr2/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvoptx b/project/at_start_f415/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvoptx index faa0150..efb98a1 100644 --- a/project/at_start_f415/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvoptx +++ b/project/at_start_f415/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvprojx b/project/at_start_f415/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvprojx index a421920..583917a 100644 --- a/project/at_start_f415/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvprojx +++ b/project/at_start_f415/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/pwc/sleep_tmr2/src/at32f415_clock.c b/project/at_start_f415/examples/pwc/sleep_tmr2/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/pwc/sleep_tmr2/src/at32f415_clock.c +++ b/project/at_start_f415/examples/pwc/sleep_tmr2/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/pwc/sleep_usart1/inc/at32f415_conf.h b/project/at_start_f415/examples/pwc/sleep_usart1/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/pwc/sleep_usart1/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/pwc/sleep_usart1/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvoptx b/project/at_start_f415/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvoptx index d26eb20..f0f51a6 100644 --- a/project/at_start_f415/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvoptx +++ b/project/at_start_f415/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvprojx b/project/at_start_f415/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvprojx index b3a853e..489fcb5 100644 --- a/project/at_start_f415/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvprojx +++ b/project/at_start_f415/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/pwc/sleep_usart1/src/at32f415_clock.c b/project/at_start_f415/examples/pwc/sleep_usart1/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/pwc/sleep_usart1/src/at32f415_clock.c +++ b/project/at_start_f415/examples/pwc/sleep_usart1/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/pwc/standby_ertc_alarm/inc/at32f415_conf.h b/project/at_start_f415/examples/pwc/standby_ertc_alarm/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/pwc/standby_ertc_alarm/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/pwc/standby_ertc_alarm/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvoptx b/project/at_start_f415/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvoptx index 8167cbf..b73e596 100644 --- a/project/at_start_f415/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvoptx +++ b/project/at_start_f415/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvprojx b/project/at_start_f415/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvprojx index 48b0006..1da0657 100644 --- a/project/at_start_f415/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvprojx +++ b/project/at_start_f415/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/pwc/standby_ertc_alarm/src/at32f415_clock.c b/project/at_start_f415/examples/pwc/standby_ertc_alarm/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/pwc/standby_ertc_alarm/src/at32f415_clock.c +++ b/project/at_start_f415/examples/pwc/standby_ertc_alarm/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/pwc/standby_wakeup_pin/inc/at32f415_conf.h b/project/at_start_f415/examples/pwc/standby_wakeup_pin/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/pwc/standby_wakeup_pin/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/pwc/standby_wakeup_pin/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvoptx b/project/at_start_f415/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvoptx index 3de89fb..9261ac2 100644 --- a/project/at_start_f415/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvoptx +++ b/project/at_start_f415/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvprojx b/project/at_start_f415/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvprojx index d3ea346..cd6af3c 100644 --- a/project/at_start_f415/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvprojx +++ b/project/at_start_f415/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvprojx @@ -10,13 +10,13 @@ standby_wakeup_pin 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC + 5060750::V5.06 update 6 (build 750)::.\ARMCC 0 -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/pwc/standby_wakeup_pin/src/at32f415_clock.c b/project/at_start_f415/examples/pwc/standby_wakeup_pin/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/pwc/standby_wakeup_pin/src/at32f415_clock.c +++ b/project/at_start_f415/examples/pwc/standby_wakeup_pin/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/pwc/standby_wakeup_pin/src/main.c b/project/at_start_f415/examples/pwc/standby_wakeup_pin/src/main.c index 94c5ccb..146400a 100644 --- a/project/at_start_f415/examples/pwc/standby_wakeup_pin/src/main.c +++ b/project/at_start_f415/examples/pwc/standby_wakeup_pin/src/main.c @@ -75,6 +75,8 @@ int main(void) } at32_led_on(LED4); + + /*delay to check led status*/ delay_ms(1000); /* enable wakeup pin - pa0 */ diff --git a/project/at_start_f415/examples/sdio/sd_mmc_card/inc/at32f415_conf.h b/project/at_start_f415/examples/sdio/sd_mmc_card/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/sdio/sd_mmc_card/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/sdio/sd_mmc_card/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvoptx b/project/at_start_f415/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvoptx index 23924ff..4953c9b 100644 --- a/project/at_start_f415/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvoptx +++ b/project/at_start_f415/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvprojx b/project/at_start_f415/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvprojx index b3c42b7..591f3ea 100644 --- a/project/at_start_f415/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvprojx +++ b/project/at_start_f415/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/sdio/sd_mmc_card/src/at32f415_clock.c b/project/at_start_f415/examples/sdio/sd_mmc_card/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/sdio/sd_mmc_card/src/at32f415_clock.c +++ b/project/at_start_f415/examples/sdio/sd_mmc_card/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/sdio/sdio_fatfs/inc/at32f415_conf.h b/project/at_start_f415/examples/sdio/sdio_fatfs/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/sdio/sdio_fatfs/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/sdio/sdio_fatfs/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvoptx b/project/at_start_f415/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvoptx index 2848c7b..aea2727 100644 --- a/project/at_start_f415/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvoptx +++ b/project/at_start_f415/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvprojx b/project/at_start_f415/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvprojx index a553678..8503288 100644 --- a/project/at_start_f415/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvprojx +++ b/project/at_start_f415/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -611,4 +611,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/sdio/sdio_fatfs/src/at32f415_clock.c b/project/at_start_f415/examples/sdio/sdio_fatfs/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/sdio/sdio_fatfs/src/at32f415_clock.c +++ b/project/at_start_f415/examples/sdio/sdio_fatfs/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/spi/crc_transfer_polling/inc/at32f415_conf.h b/project/at_start_f415/examples/spi/crc_transfer_polling/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/spi/crc_transfer_polling/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/spi/crc_transfer_polling/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvoptx b/project/at_start_f415/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvoptx index 7219d50..f7c1165 100644 --- a/project/at_start_f415/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvoptx +++ b/project/at_start_f415/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvprojx b/project/at_start_f415/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvprojx index f180038..8f6240e 100644 --- a/project/at_start_f415/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvprojx +++ b/project/at_start_f415/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/spi/crc_transfer_polling/src/at32f415_clock.c b/project/at_start_f415/examples/spi/crc_transfer_polling/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/spi/crc_transfer_polling/src/at32f415_clock.c +++ b/project/at_start_f415/examples/spi/crc_transfer_polling/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/spi/fullduplex_polling/inc/at32f415_conf.h b/project/at_start_f415/examples/spi/fullduplex_polling/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/spi/fullduplex_polling/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/spi/fullduplex_polling/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvoptx b/project/at_start_f415/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvoptx index 3ba0d16..645f373 100644 --- a/project/at_start_f415/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvoptx +++ b/project/at_start_f415/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvprojx b/project/at_start_f415/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvprojx index 6ba4bf3..2dcd8c0 100644 --- a/project/at_start_f415/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvprojx +++ b/project/at_start_f415/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/spi/fullduplex_polling/src/at32f415_clock.c b/project/at_start_f415/examples/spi/fullduplex_polling/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/spi/fullduplex_polling/src/at32f415_clock.c +++ b/project/at_start_f415/examples/spi/fullduplex_polling/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/spi/halfduplex_interrupt/inc/at32f415_conf.h b/project/at_start_f415/examples/spi/halfduplex_interrupt/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/spi/halfduplex_interrupt/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/spi/halfduplex_interrupt/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx b/project/at_start_f415/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx index 88276d8..e407ef8 100644 --- a/project/at_start_f415/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx +++ b/project/at_start_f415/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx b/project/at_start_f415/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx index 07f7926..94024fe 100644 --- a/project/at_start_f415/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx +++ b/project/at_start_f415/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/spi/halfduplex_interrupt/src/at32f415_clock.c b/project/at_start_f415/examples/spi/halfduplex_interrupt/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/spi/halfduplex_interrupt/src/at32f415_clock.c +++ b/project/at_start_f415/examples/spi/halfduplex_interrupt/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/inc/at32f415_conf.h b/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvoptx b/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvoptx index 3fd2923..faa930f 100644 --- a/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvoptx +++ b/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvprojx b/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvprojx index 8308414..35505c1 100644 --- a/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvprojx +++ b/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/src/at32f415_clock.c b/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/src/at32f415_clock.c +++ b/project/at_start_f415/examples/spi/halfduplex_transceiver_switch/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/spi/only_receive_mode_polling/inc/at32f415_conf.h b/project/at_start_f415/examples/spi/only_receive_mode_polling/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/spi/only_receive_mode_polling/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/spi/only_receive_mode_polling/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvoptx b/project/at_start_f415/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvoptx index 1bd8f8e..c176039 100644 --- a/project/at_start_f415/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvoptx +++ b/project/at_start_f415/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvprojx b/project/at_start_f415/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvprojx index c6c97bf..266d41e 100644 --- a/project/at_start_f415/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvprojx +++ b/project/at_start_f415/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/spi/only_receive_mode_polling/src/at32f415_clock.c b/project/at_start_f415/examples/spi/only_receive_mode_polling/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/spi/only_receive_mode_polling/src/at32f415_clock.c +++ b/project/at_start_f415/examples/spi/only_receive_mode_polling/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/inc/at32f415_conf.h b/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvoptx b/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvoptx index 2a24344..2939bb4 100644 --- a/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvoptx +++ b/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvprojx b/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvprojx index feed593..4978cdc 100644 --- a/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvprojx +++ b/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/src/at32f415_clock.c b/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/src/at32f415_clock.c +++ b/project/at_start_f415/examples/spi/use_jtagpin_hardwarecs_dma/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/spi/w25q_flash/inc/at32f415_conf.h b/project/at_start_f415/examples/spi/w25q_flash/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/spi/w25q_flash/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/spi/w25q_flash/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvoptx b/project/at_start_f415/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvoptx index 8fab196..c909382 100644 --- a/project/at_start_f415/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvoptx +++ b/project/at_start_f415/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvprojx b/project/at_start_f415/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvprojx index c96149b..9ba4ac4 100644 --- a/project/at_start_f415/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvprojx +++ b/project/at_start_f415/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/spi/w25q_flash/src/at32f415_clock.c b/project/at_start_f415/examples/spi/w25q_flash/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/spi/w25q_flash/src/at32f415_clock.c +++ b/project/at_start_f415/examples/spi/w25q_flash/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/6_steps/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/6_steps/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/6_steps/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/6_steps/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/6_steps/mdk_v5/6_steps.uvoptx b/project/at_start_f415/examples/tmr/6_steps/mdk_v5/6_steps.uvoptx index a1bc52b..9a6556c 100644 --- a/project/at_start_f415/examples/tmr/6_steps/mdk_v5/6_steps.uvoptx +++ b/project/at_start_f415/examples/tmr/6_steps/mdk_v5/6_steps.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/6_steps/mdk_v5/6_steps.uvprojx b/project/at_start_f415/examples/tmr/6_steps/mdk_v5/6_steps.uvprojx index 67b196f..625410c 100644 --- a/project/at_start_f415/examples/tmr/6_steps/mdk_v5/6_steps.uvprojx +++ b/project/at_start_f415/examples/tmr/6_steps/mdk_v5/6_steps.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/6_steps/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/6_steps/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/6_steps/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/6_steps/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/7_pwm_output/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/7_pwm_output/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/7_pwm_output/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/7_pwm_output/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvoptx b/project/at_start_f415/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvoptx index b9d9771..5383ffe 100644 --- a/project/at_start_f415/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvoptx +++ b/project/at_start_f415/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvprojx b/project/at_start_f415/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvprojx index 156e71e..8551708 100644 --- a/project/at_start_f415/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvprojx +++ b/project/at_start_f415/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/7_pwm_output/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/7_pwm_output/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/7_pwm_output/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/7_pwm_output/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/cascade_synchro/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/cascade_synchro/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/cascade_synchro/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/cascade_synchro/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvoptx b/project/at_start_f415/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvoptx index d1d4d67..8a8c3db 100644 --- a/project/at_start_f415/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvoptx +++ b/project/at_start_f415/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvprojx b/project/at_start_f415/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvprojx index 3611455..ed2e67f 100644 --- a/project/at_start_f415/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvprojx +++ b/project/at_start_f415/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/cascade_synchro/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/cascade_synchro/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/cascade_synchro/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/cascade_synchro/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/complementary_signals/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/complementary_signals/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/complementary_signals/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/complementary_signals/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvoptx b/project/at_start_f415/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvoptx index fb6ded3..e97cbd5 100644 --- a/project/at_start_f415/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvoptx +++ b/project/at_start_f415/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvprojx b/project/at_start_f415/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvprojx index 96d127a..59fde93 100644 --- a/project/at_start_f415/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvprojx +++ b/project/at_start_f415/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/complementary_signals/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/complementary_signals/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/complementary_signals/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/complementary_signals/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/dma/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/dma/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/dma/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/dma/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/dma/mdk_v5/dma.uvoptx b/project/at_start_f415/examples/tmr/dma/mdk_v5/dma.uvoptx index c8718fe..12dbdb0 100644 --- a/project/at_start_f415/examples/tmr/dma/mdk_v5/dma.uvoptx +++ b/project/at_start_f415/examples/tmr/dma/mdk_v5/dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/dma/mdk_v5/dma.uvprojx b/project/at_start_f415/examples/tmr/dma/mdk_v5/dma.uvprojx index 86fc725..99b81ed 100644 --- a/project/at_start_f415/examples/tmr/dma/mdk_v5/dma.uvprojx +++ b/project/at_start_f415/examples/tmr/dma/mdk_v5/dma.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/dma/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/dma/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/dma/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/dma/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/dma_burst/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/dma_burst/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/dma_burst/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/dma_burst/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/dma_burst/mdk_v5/dma_burst.uvoptx b/project/at_start_f415/examples/tmr/dma_burst/mdk_v5/dma_burst.uvoptx index a350bae..2d30a9a 100644 --- a/project/at_start_f415/examples/tmr/dma_burst/mdk_v5/dma_burst.uvoptx +++ b/project/at_start_f415/examples/tmr/dma_burst/mdk_v5/dma_burst.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/dma_burst/mdk_v5/dma_burst.uvprojx b/project/at_start_f415/examples/tmr/dma_burst/mdk_v5/dma_burst.uvprojx index 09a3a1f..22f48d9 100644 --- a/project/at_start_f415/examples/tmr/dma_burst/mdk_v5/dma_burst.uvprojx +++ b/project/at_start_f415/examples/tmr/dma_burst/mdk_v5/dma_burst.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/dma_burst/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/dma_burst/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/dma_burst/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/dma_burst/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/encoder_tmr2/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/encoder_tmr2/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/encoder_tmr2/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/encoder_tmr2/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvoptx b/project/at_start_f415/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvoptx index faa5275..9f98732 100644 --- a/project/at_start_f415/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvoptx +++ b/project/at_start_f415/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvprojx b/project/at_start_f415/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvprojx index 5079250..711de5b 100644 --- a/project/at_start_f415/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvprojx +++ b/project/at_start_f415/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/encoder_tmr2/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/encoder_tmr2/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/encoder_tmr2/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/encoder_tmr2/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/external_clock/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/external_clock/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/external_clock/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/external_clock/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/external_clock/mdk_v5/external_clock.uvoptx b/project/at_start_f415/examples/tmr/external_clock/mdk_v5/external_clock.uvoptx index 4b95c50..27c6bb5 100644 --- a/project/at_start_f415/examples/tmr/external_clock/mdk_v5/external_clock.uvoptx +++ b/project/at_start_f415/examples/tmr/external_clock/mdk_v5/external_clock.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/external_clock/mdk_v5/external_clock.uvprojx b/project/at_start_f415/examples/tmr/external_clock/mdk_v5/external_clock.uvprojx index e67c22e..fc5b420 100644 --- a/project/at_start_f415/examples/tmr/external_clock/mdk_v5/external_clock.uvprojx +++ b/project/at_start_f415/examples/tmr/external_clock/mdk_v5/external_clock.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/external_clock/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/external_clock/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/external_clock/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/external_clock/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/hall_xor_tmr2/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/hall_xor_tmr2/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/hall_xor_tmr2/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/hall_xor_tmr2/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvoptx b/project/at_start_f415/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvoptx index 23379cb..009ccc5 100644 --- a/project/at_start_f415/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvoptx +++ b/project/at_start_f415/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvprojx b/project/at_start_f415/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvprojx index 7099cae..0e39e5a 100644 --- a/project/at_start_f415/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvprojx +++ b/project/at_start_f415/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/hall_xor_tmr2/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/hall_xor_tmr2/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/hall_xor_tmr2/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/hall_xor_tmr2/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/hang_mode/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/hang_mode/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/hang_mode/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/hang_mode/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/hang_mode/mdk_v5/hang_mode.uvoptx b/project/at_start_f415/examples/tmr/hang_mode/mdk_v5/hang_mode.uvoptx index 3aba012..820563e 100644 --- a/project/at_start_f415/examples/tmr/hang_mode/mdk_v5/hang_mode.uvoptx +++ b/project/at_start_f415/examples/tmr/hang_mode/mdk_v5/hang_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/hang_mode/mdk_v5/hang_mode.uvprojx b/project/at_start_f415/examples/tmr/hang_mode/mdk_v5/hang_mode.uvprojx index 950aa05..567072a 100644 --- a/project/at_start_f415/examples/tmr/hang_mode/mdk_v5/hang_mode.uvprojx +++ b/project/at_start_f415/examples/tmr/hang_mode/mdk_v5/hang_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/hang_mode/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/hang_mode/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/hang_mode/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/hang_mode/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/input_capture/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/input_capture/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/input_capture/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/input_capture/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/input_capture/mdk_v5/input_capture.uvoptx b/project/at_start_f415/examples/tmr/input_capture/mdk_v5/input_capture.uvoptx index 079047e..0bb0819 100644 --- a/project/at_start_f415/examples/tmr/input_capture/mdk_v5/input_capture.uvoptx +++ b/project/at_start_f415/examples/tmr/input_capture/mdk_v5/input_capture.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/input_capture/mdk_v5/input_capture.uvprojx b/project/at_start_f415/examples/tmr/input_capture/mdk_v5/input_capture.uvprojx index 5781e51..cad99e5 100644 --- a/project/at_start_f415/examples/tmr/input_capture/mdk_v5/input_capture.uvprojx +++ b/project/at_start_f415/examples/tmr/input_capture/mdk_v5/input_capture.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/input_capture/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/input_capture/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/input_capture/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/input_capture/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/oc_high/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/oc_high/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/oc_high/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/oc_high/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/oc_high/mdk_v5/oc_high.uvoptx b/project/at_start_f415/examples/tmr/oc_high/mdk_v5/oc_high.uvoptx index ec88850..d63f87a 100644 --- a/project/at_start_f415/examples/tmr/oc_high/mdk_v5/oc_high.uvoptx +++ b/project/at_start_f415/examples/tmr/oc_high/mdk_v5/oc_high.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/oc_high/mdk_v5/oc_high.uvprojx b/project/at_start_f415/examples/tmr/oc_high/mdk_v5/oc_high.uvprojx index 4c477e2..844cdde 100644 --- a/project/at_start_f415/examples/tmr/oc_high/mdk_v5/oc_high.uvprojx +++ b/project/at_start_f415/examples/tmr/oc_high/mdk_v5/oc_high.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/oc_high/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/oc_high/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/oc_high/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/oc_high/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/oc_low/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/oc_low/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/oc_low/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/oc_low/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/oc_low/mdk_v5/oc_low.uvoptx b/project/at_start_f415/examples/tmr/oc_low/mdk_v5/oc_low.uvoptx index 65a0d2c..960c618 100644 --- a/project/at_start_f415/examples/tmr/oc_low/mdk_v5/oc_low.uvoptx +++ b/project/at_start_f415/examples/tmr/oc_low/mdk_v5/oc_low.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/oc_low/mdk_v5/oc_low.uvprojx b/project/at_start_f415/examples/tmr/oc_low/mdk_v5/oc_low.uvprojx index 7ca498e..942bd86 100644 --- a/project/at_start_f415/examples/tmr/oc_low/mdk_v5/oc_low.uvprojx +++ b/project/at_start_f415/examples/tmr/oc_low/mdk_v5/oc_low.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/oc_low/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/oc_low/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/oc_low/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/oc_low/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/oc_toggle_tmr3/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/oc_toggle_tmr3/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/oc_toggle_tmr3/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/oc_toggle_tmr3/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvoptx b/project/at_start_f415/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvoptx index 66a8ff5..f6ff0dc 100644 --- a/project/at_start_f415/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvoptx +++ b/project/at_start_f415/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvprojx b/project/at_start_f415/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvprojx index 15ac79e..f4bf6cb 100644 --- a/project/at_start_f415/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvprojx +++ b/project/at_start_f415/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/oc_toggle_tmr3/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/oc_toggle_tmr3/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/oc_toggle_tmr3/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/oc_toggle_tmr3/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/oc_toggle_tmr9/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/oc_toggle_tmr9/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/oc_toggle_tmr9/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/oc_toggle_tmr9/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvoptx b/project/at_start_f415/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvoptx index 833662c..d97e108 100644 --- a/project/at_start_f415/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvoptx +++ b/project/at_start_f415/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvprojx b/project/at_start_f415/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvprojx index 114468e..2f430fd 100644 --- a/project/at_start_f415/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvprojx +++ b/project/at_start_f415/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/oc_toggle_tmr9/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/oc_toggle_tmr9/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/oc_toggle_tmr9/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/oc_toggle_tmr9/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/one_cycle/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/one_cycle/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/one_cycle/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/one_cycle/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/one_cycle/mdk_v5/one_cycle.uvoptx b/project/at_start_f415/examples/tmr/one_cycle/mdk_v5/one_cycle.uvoptx index 4a7396b..52e0027 100644 --- a/project/at_start_f415/examples/tmr/one_cycle/mdk_v5/one_cycle.uvoptx +++ b/project/at_start_f415/examples/tmr/one_cycle/mdk_v5/one_cycle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/one_cycle/mdk_v5/one_cycle.uvprojx b/project/at_start_f415/examples/tmr/one_cycle/mdk_v5/one_cycle.uvprojx index bcd0b0a..f36935d 100644 --- a/project/at_start_f415/examples/tmr/one_cycle/mdk_v5/one_cycle.uvprojx +++ b/project/at_start_f415/examples/tmr/one_cycle/mdk_v5/one_cycle.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/one_cycle/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/one_cycle/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/one_cycle/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/one_cycle/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/parallel_synchro/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/parallel_synchro/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/parallel_synchro/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/parallel_synchro/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvoptx b/project/at_start_f415/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvoptx index c29740b..5171676 100644 --- a/project/at_start_f415/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvoptx +++ b/project/at_start_f415/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvprojx b/project/at_start_f415/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvprojx index 8787f36..5f81f1d 100644 --- a/project/at_start_f415/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvprojx +++ b/project/at_start_f415/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/parallel_synchro/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/parallel_synchro/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/parallel_synchro/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/parallel_synchro/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/pwm_input/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/pwm_input/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/pwm_input/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/pwm_input/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/pwm_input/mdk_v5/pwm_input.uvoptx b/project/at_start_f415/examples/tmr/pwm_input/mdk_v5/pwm_input.uvoptx index e04c5fd..aa4c53a 100644 --- a/project/at_start_f415/examples/tmr/pwm_input/mdk_v5/pwm_input.uvoptx +++ b/project/at_start_f415/examples/tmr/pwm_input/mdk_v5/pwm_input.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/pwm_input/mdk_v5/pwm_input.uvprojx b/project/at_start_f415/examples/tmr/pwm_input/mdk_v5/pwm_input.uvprojx index 9dde596..539b418 100644 --- a/project/at_start_f415/examples/tmr/pwm_input/mdk_v5/pwm_input.uvprojx +++ b/project/at_start_f415/examples/tmr/pwm_input/mdk_v5/pwm_input.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/pwm_input/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/pwm_input/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/pwm_input/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/pwm_input/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/pwm_input_dma/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/pwm_input_dma/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/pwm_input_dma/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/pwm_input_dma/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvoptx b/project/at_start_f415/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvoptx index 8d8b271..7a85f11 100644 --- a/project/at_start_f415/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvoptx +++ b/project/at_start_f415/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvprojx b/project/at_start_f415/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvprojx index f742724..9497284 100644 --- a/project/at_start_f415/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvprojx +++ b/project/at_start_f415/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/pwm_input_dma/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/pwm_input_dma/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/pwm_input_dma/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/pwm_input_dma/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/pwm_output_simulate/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/pwm_output_simulate/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/pwm_output_simulate/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/pwm_output_simulate/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvoptx b/project/at_start_f415/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvoptx index e7485d0..7318f6a 100644 --- a/project/at_start_f415/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvoptx +++ b/project/at_start_f415/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvprojx b/project/at_start_f415/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvprojx index aefd3c4..081194c 100644 --- a/project/at_start_f415/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvprojx +++ b/project/at_start_f415/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/pwm_output_simulate/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/pwm_output_simulate/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/pwm_output_simulate/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/pwm_output_simulate/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/pwm_output_tmr10/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/pwm_output_tmr10/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/pwm_output_tmr10/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/pwm_output_tmr10/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvoptx b/project/at_start_f415/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvoptx index dfcc2fe..d981b35 100644 --- a/project/at_start_f415/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvoptx +++ b/project/at_start_f415/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvprojx b/project/at_start_f415/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvprojx index ab52443..159a504 100644 --- a/project/at_start_f415/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvprojx +++ b/project/at_start_f415/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/pwm_output_tmr10/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/pwm_output_tmr10/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/pwm_output_tmr10/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/pwm_output_tmr10/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/pwm_output_tmr3/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/pwm_output_tmr3/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/pwm_output_tmr3/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/pwm_output_tmr3/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvoptx b/project/at_start_f415/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvoptx index 3198bf4..b6c2850 100644 --- a/project/at_start_f415/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvoptx +++ b/project/at_start_f415/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvprojx b/project/at_start_f415/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvprojx index bddfb77..a94e767 100644 --- a/project/at_start_f415/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvprojx +++ b/project/at_start_f415/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/pwm_output_tmr3/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/pwm_output_tmr3/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/pwm_output_tmr3/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/pwm_output_tmr3/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/timer_base/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/timer_base/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/timer_base/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/timer_base/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/timer_base/mdk_v5/timer_base.uvoptx b/project/at_start_f415/examples/tmr/timer_base/mdk_v5/timer_base.uvoptx index 5751400..144d0af 100644 --- a/project/at_start_f415/examples/tmr/timer_base/mdk_v5/timer_base.uvoptx +++ b/project/at_start_f415/examples/tmr/timer_base/mdk_v5/timer_base.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/timer_base/mdk_v5/timer_base.uvprojx b/project/at_start_f415/examples/tmr/timer_base/mdk_v5/timer_base.uvprojx index e6ceec4..5c1b616 100644 --- a/project/at_start_f415/examples/tmr/timer_base/mdk_v5/timer_base.uvprojx +++ b/project/at_start_f415/examples/tmr/timer_base/mdk_v5/timer_base.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/timer_base/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/timer_base/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/timer_base/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/timer_base/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/tmr1_synchro/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/tmr1_synchro/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/tmr1_synchro/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/tmr1_synchro/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvoptx b/project/at_start_f415/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvoptx index a7b1634..785462a 100644 --- a/project/at_start_f415/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvoptx +++ b/project/at_start_f415/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvprojx b/project/at_start_f415/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvprojx index a667fa2..ab93d44 100644 --- a/project/at_start_f415/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvprojx +++ b/project/at_start_f415/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/tmr1_synchro/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/tmr1_synchro/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/tmr1_synchro/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/tmr1_synchro/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/tmr/tmr2_32bit/inc/at32f415_conf.h b/project/at_start_f415/examples/tmr/tmr2_32bit/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/tmr/tmr2_32bit/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/tmr/tmr2_32bit/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvoptx b/project/at_start_f415/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvoptx index c6d7939..7b7c26f 100644 --- a/project/at_start_f415/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvoptx +++ b/project/at_start_f415/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvprojx b/project/at_start_f415/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvprojx index 622bfeb..ab8fc86 100644 --- a/project/at_start_f415/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvprojx +++ b/project/at_start_f415/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/tmr/tmr2_32bit/src/at32f415_clock.c b/project/at_start_f415/examples/tmr/tmr2_32bit/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/tmr/tmr2_32bit/src/at32f415_clock.c +++ b/project/at_start_f415/examples/tmr/tmr2_32bit/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usart/half_duplex/inc/at32f415_conf.h b/project/at_start_f415/examples/usart/half_duplex/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usart/half_duplex/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usart/half_duplex/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usart/half_duplex/mdk_v5/half_duplex.uvoptx b/project/at_start_f415/examples/usart/half_duplex/mdk_v5/half_duplex.uvoptx index 1655f90..4eb8442 100644 --- a/project/at_start_f415/examples/usart/half_duplex/mdk_v5/half_duplex.uvoptx +++ b/project/at_start_f415/examples/usart/half_duplex/mdk_v5/half_duplex.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usart/half_duplex/mdk_v5/half_duplex.uvprojx b/project/at_start_f415/examples/usart/half_duplex/mdk_v5/half_duplex.uvprojx index 448aac9..968937b 100644 --- a/project/at_start_f415/examples/usart/half_duplex/mdk_v5/half_duplex.uvprojx +++ b/project/at_start_f415/examples/usart/half_duplex/mdk_v5/half_duplex.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/usart/half_duplex/src/at32f415_clock.c b/project/at_start_f415/examples/usart/half_duplex/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usart/half_duplex/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usart/half_duplex/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usart/hw_flow_control/inc/at32f415_conf.h b/project/at_start_f415/examples/usart/hw_flow_control/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usart/hw_flow_control/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usart/hw_flow_control/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvoptx b/project/at_start_f415/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvoptx index 4cb2444..a620f0a 100644 --- a/project/at_start_f415/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvoptx +++ b/project/at_start_f415/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvprojx b/project/at_start_f415/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvprojx index 47e4120..9301e9a 100644 --- a/project/at_start_f415/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvprojx +++ b/project/at_start_f415/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usart/hw_flow_control/src/at32f415_clock.c b/project/at_start_f415/examples/usart/hw_flow_control/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usart/hw_flow_control/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usart/hw_flow_control/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usart/idle_detection/inc/at32f415_conf.h b/project/at_start_f415/examples/usart/idle_detection/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usart/idle_detection/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usart/idle_detection/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usart/idle_detection/mdk_v5/idle_detection.uvoptx b/project/at_start_f415/examples/usart/idle_detection/mdk_v5/idle_detection.uvoptx index bda0f8c..72c5242 100644 --- a/project/at_start_f415/examples/usart/idle_detection/mdk_v5/idle_detection.uvoptx +++ b/project/at_start_f415/examples/usart/idle_detection/mdk_v5/idle_detection.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usart/idle_detection/mdk_v5/idle_detection.uvprojx b/project/at_start_f415/examples/usart/idle_detection/mdk_v5/idle_detection.uvprojx index e650007..59d6423 100644 --- a/project/at_start_f415/examples/usart/idle_detection/mdk_v5/idle_detection.uvprojx +++ b/project/at_start_f415/examples/usart/idle_detection/mdk_v5/idle_detection.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/usart/idle_detection/src/at32f415_clock.c b/project/at_start_f415/examples/usart/idle_detection/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usart/idle_detection/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usart/idle_detection/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usart/interrupt/inc/at32f415_conf.h b/project/at_start_f415/examples/usart/interrupt/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usart/interrupt/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usart/interrupt/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usart/interrupt/mdk_v5/interrupt.uvoptx b/project/at_start_f415/examples/usart/interrupt/mdk_v5/interrupt.uvoptx index 444a528..7552436 100644 --- a/project/at_start_f415/examples/usart/interrupt/mdk_v5/interrupt.uvoptx +++ b/project/at_start_f415/examples/usart/interrupt/mdk_v5/interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usart/interrupt/mdk_v5/interrupt.uvprojx b/project/at_start_f415/examples/usart/interrupt/mdk_v5/interrupt.uvprojx index 7197f05..11411d6 100644 --- a/project/at_start_f415/examples/usart/interrupt/mdk_v5/interrupt.uvprojx +++ b/project/at_start_f415/examples/usart/interrupt/mdk_v5/interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/usart/interrupt/src/at32f415_clock.c b/project/at_start_f415/examples/usart/interrupt/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usart/interrupt/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usart/interrupt/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usart/irda/inc/at32f415_conf.h b/project/at_start_f415/examples/usart/irda/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usart/irda/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usart/irda/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usart/irda/mdk_v5/irda.uvoptx b/project/at_start_f415/examples/usart/irda/mdk_v5/irda.uvoptx index 17e37d7..2196378 100644 --- a/project/at_start_f415/examples/usart/irda/mdk_v5/irda.uvoptx +++ b/project/at_start_f415/examples/usart/irda/mdk_v5/irda.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usart/irda/mdk_v5/irda.uvprojx b/project/at_start_f415/examples/usart/irda/mdk_v5/irda.uvprojx index 8cda4d3..2aac45e 100644 --- a/project/at_start_f415/examples/usart/irda/mdk_v5/irda.uvprojx +++ b/project/at_start_f415/examples/usart/irda/mdk_v5/irda.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -928,6 +928,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/usart/irda/src/at32f415_clock.c b/project/at_start_f415/examples/usart/irda/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usart/irda/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usart/irda/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usart/polling/inc/at32f415_conf.h b/project/at_start_f415/examples/usart/polling/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usart/polling/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usart/polling/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usart/polling/mdk_v5/polling.uvoptx b/project/at_start_f415/examples/usart/polling/mdk_v5/polling.uvoptx index 7dfd401..50d491c 100644 --- a/project/at_start_f415/examples/usart/polling/mdk_v5/polling.uvoptx +++ b/project/at_start_f415/examples/usart/polling/mdk_v5/polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usart/polling/mdk_v5/polling.uvprojx b/project/at_start_f415/examples/usart/polling/mdk_v5/polling.uvprojx index c9f30a5..a278a2f 100644 --- a/project/at_start_f415/examples/usart/polling/mdk_v5/polling.uvprojx +++ b/project/at_start_f415/examples/usart/polling/mdk_v5/polling.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/usart/polling/src/at32f415_clock.c b/project/at_start_f415/examples/usart/polling/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usart/polling/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usart/polling/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usart/printf/inc/at32f415_conf.h b/project/at_start_f415/examples/usart/printf/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usart/printf/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usart/printf/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usart/printf/mdk_v5/printf.uvoptx b/project/at_start_f415/examples/usart/printf/mdk_v5/printf.uvoptx index c07af42..983dd71 100644 --- a/project/at_start_f415/examples/usart/printf/mdk_v5/printf.uvoptx +++ b/project/at_start_f415/examples/usart/printf/mdk_v5/printf.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usart/printf/mdk_v5/printf.uvprojx b/project/at_start_f415/examples/usart/printf/mdk_v5/printf.uvprojx index 29bef02..f620bdd 100644 --- a/project/at_start_f415/examples/usart/printf/mdk_v5/printf.uvprojx +++ b/project/at_start_f415/examples/usart/printf/mdk_v5/printf.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/usart/printf/src/at32f415_clock.c b/project/at_start_f415/examples/usart/printf/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usart/printf/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usart/printf/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usart/receiver_mute/inc/at32f415_conf.h b/project/at_start_f415/examples/usart/receiver_mute/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usart/receiver_mute/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usart/receiver_mute/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvoptx b/project/at_start_f415/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvoptx index d0b1f9e..ed15866 100644 --- a/project/at_start_f415/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvoptx +++ b/project/at_start_f415/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvprojx b/project/at_start_f415/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvprojx index ca4b746..7f5b89b 100644 --- a/project/at_start_f415/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvprojx +++ b/project/at_start_f415/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usart/receiver_mute/src/at32f415_clock.c b/project/at_start_f415/examples/usart/receiver_mute/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usart/receiver_mute/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usart/receiver_mute/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usart/rs485/inc/at32f415_conf.h b/project/at_start_f415/examples/usart/rs485/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usart/rs485/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usart/rs485/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usart/rs485/mdk_v5/rs485.uvoptx b/project/at_start_f415/examples/usart/rs485/mdk_v5/rs485.uvoptx index 87641f5..73d61f1 100644 --- a/project/at_start_f415/examples/usart/rs485/mdk_v5/rs485.uvoptx +++ b/project/at_start_f415/examples/usart/rs485/mdk_v5/rs485.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usart/rs485/mdk_v5/rs485.uvprojx b/project/at_start_f415/examples/usart/rs485/mdk_v5/rs485.uvprojx index 5069dbd..d780863 100644 --- a/project/at_start_f415/examples/usart/rs485/mdk_v5/rs485.uvprojx +++ b/project/at_start_f415/examples/usart/rs485/mdk_v5/rs485.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usart/rs485/src/at32f415_clock.c b/project/at_start_f415/examples/usart/rs485/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usart/rs485/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usart/rs485/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usart/smartcard/inc/at32f415_conf.h b/project/at_start_f415/examples/usart/smartcard/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usart/smartcard/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usart/smartcard/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usart/smartcard/mdk_v5/smartcard.uvoptx b/project/at_start_f415/examples/usart/smartcard/mdk_v5/smartcard.uvoptx index 097f00d..9f8a708 100644 --- a/project/at_start_f415/examples/usart/smartcard/mdk_v5/smartcard.uvoptx +++ b/project/at_start_f415/examples/usart/smartcard/mdk_v5/smartcard.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usart/smartcard/mdk_v5/smartcard.uvprojx b/project/at_start_f415/examples/usart/smartcard/mdk_v5/smartcard.uvprojx index 67171b8..7704e91 100644 --- a/project/at_start_f415/examples/usart/smartcard/mdk_v5/smartcard.uvprojx +++ b/project/at_start_f415/examples/usart/smartcard/mdk_v5/smartcard.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/usart/smartcard/src/at32f415_clock.c b/project/at_start_f415/examples/usart/smartcard/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usart/smartcard/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usart/smartcard/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usart/synchronous/inc/at32f415_conf.h b/project/at_start_f415/examples/usart/synchronous/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usart/synchronous/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usart/synchronous/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usart/synchronous/mdk_v5/synchronous.uvoptx b/project/at_start_f415/examples/usart/synchronous/mdk_v5/synchronous.uvoptx index 8979cc9..0132156 100644 --- a/project/at_start_f415/examples/usart/synchronous/mdk_v5/synchronous.uvoptx +++ b/project/at_start_f415/examples/usart/synchronous/mdk_v5/synchronous.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usart/synchronous/mdk_v5/synchronous.uvprojx b/project/at_start_f415/examples/usart/synchronous/mdk_v5/synchronous.uvprojx index 9e6bc48..7d307c5 100644 --- a/project/at_start_f415/examples/usart/synchronous/mdk_v5/synchronous.uvprojx +++ b/project/at_start_f415/examples/usart/synchronous/mdk_v5/synchronous.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/usart/synchronous/src/at32f415_clock.c b/project/at_start_f415/examples/usart/synchronous/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usart/synchronous/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usart/synchronous/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/inc/at32f415_conf.h b/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvoptx b/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvoptx index bb12546..da578bc 100644 --- a/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvoptx +++ b/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvprojx b/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvprojx index 06123e5..d525e64 100644 --- a/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvprojx +++ b/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/src/at32f415_clock.c b/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usart/transfer_by_dma_interrupt/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usart/transfer_by_dma_polling/inc/at32f415_conf.h b/project/at_start_f415/examples/usart/transfer_by_dma_polling/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usart/transfer_by_dma_polling/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usart/transfer_by_dma_polling/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvoptx b/project/at_start_f415/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvoptx index b76cf3c..dce015c 100644 --- a/project/at_start_f415/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvoptx +++ b/project/at_start_f415/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvprojx b/project/at_start_f415/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvprojx index 3ecefdf..b698672 100644 --- a/project/at_start_f415/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvprojx +++ b/project/at_start_f415/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/usart/transfer_by_dma_polling/src/at32f415_clock.c b/project/at_start_f415/examples/usart/transfer_by_dma_polling/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usart/transfer_by_dma_polling/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usart/transfer_by_dma_polling/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_device/audio/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_device/audio/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_device/audio/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_device/audio/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_device/audio/mdk_v5/audio.uvoptx b/project/at_start_f415/examples/usb_device/audio/mdk_v5/audio.uvoptx index 1d7a82c..cb65f83 100644 --- a/project/at_start_f415/examples/usb_device/audio/mdk_v5/audio.uvoptx +++ b/project/at_start_f415/examples/usb_device/audio/mdk_v5/audio.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_device/audio/mdk_v5/audio.uvprojx b/project/at_start_f415/examples/usb_device/audio/mdk_v5/audio.uvprojx index 440fb77..675de64 100644 --- a/project/at_start_f415/examples/usb_device/audio/mdk_v5/audio.uvprojx +++ b/project/at_start_f415/examples/usb_device/audio/mdk_v5/audio.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -544,4 +544,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usb_device/audio/src/at32f415_clock.c b/project/at_start_f415/examples/usb_device/audio/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_device/audio/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_device/audio/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_device/composite_audio_hid/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_device/composite_audio_hid/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_device/composite_audio_hid/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_device/composite_audio_hid/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvoptx b/project/at_start_f415/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvoptx index 796f532..3657fbf 100644 --- a/project/at_start_f415/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvoptx +++ b/project/at_start_f415/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvprojx b/project/at_start_f415/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvprojx index 13a0b2a..eb08045 100644 --- a/project/at_start_f415/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvprojx +++ b/project/at_start_f415/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -544,4 +544,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usb_device/composite_audio_hid/src/at32f415_clock.c b/project/at_start_f415/examples/usb_device/composite_audio_hid/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_device/composite_audio_hid/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_device/composite_audio_hid/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvoptx b/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvoptx index f87a2c8..2a63fd8 100644 --- a/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvoptx +++ b/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvprojx b/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvprojx index a32cdd7..df42c49 100644 --- a/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvprojx +++ b/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -524,4 +524,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/src/at32f415_clock.c b/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_device/composite_vcp_keyboard/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_device/composite_vcp_msc/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_device/composite_vcp_msc/inc/at32f415_conf.h index f4429b4..a03b751 100644 --- a/project/at_start_f415/examples/usb_device/composite_vcp_msc/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_device/composite_vcp_msc/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvoptx b/project/at_start_f415/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvoptx index 80abfae..9ff48bc 100644 --- a/project/at_start_f415/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvoptx +++ b/project/at_start_f415/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvprojx b/project/at_start_f415/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvprojx index 8865b8a..bb955a5 100644 --- a/project/at_start_f415/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvprojx +++ b/project/at_start_f415/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -534,4 +534,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usb_device/custom_hid/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_device/custom_hid/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_device/custom_hid/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_device/custom_hid/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvoptx b/project/at_start_f415/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvoptx index 3478adf..898314a 100644 --- a/project/at_start_f415/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvoptx +++ b/project/at_start_f415/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvprojx b/project/at_start_f415/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvprojx index cc4553c..cb394fb 100644 --- a/project/at_start_f415/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvprojx +++ b/project/at_start_f415/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -524,4 +524,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usb_device/custom_hid/src/at32f415_clock.c b/project/at_start_f415/examples/usb_device/custom_hid/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_device/custom_hid/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_device/custom_hid/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_device/keyboard/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_device/keyboard/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_device/keyboard/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_device/keyboard/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_device/keyboard/mdk_v5/keyboard.uvoptx b/project/at_start_f415/examples/usb_device/keyboard/mdk_v5/keyboard.uvoptx index 78d8828..ff5d851 100644 --- a/project/at_start_f415/examples/usb_device/keyboard/mdk_v5/keyboard.uvoptx +++ b/project/at_start_f415/examples/usb_device/keyboard/mdk_v5/keyboard.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_device/keyboard/mdk_v5/keyboard.uvprojx b/project/at_start_f415/examples/usb_device/keyboard/mdk_v5/keyboard.uvprojx index 2f082d1..3d7b5ea 100644 --- a/project/at_start_f415/examples/usb_device/keyboard/mdk_v5/keyboard.uvprojx +++ b/project/at_start_f415/examples/usb_device/keyboard/mdk_v5/keyboard.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -524,4 +524,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usb_device/keyboard/src/at32f415_clock.c b/project/at_start_f415/examples/usb_device/keyboard/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_device/keyboard/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_device/keyboard/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_device/mouse/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_device/mouse/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_device/mouse/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_device/mouse/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_device/mouse/mdk_v5/mouse.uvoptx b/project/at_start_f415/examples/usb_device/mouse/mdk_v5/mouse.uvoptx index 3e51b3f..ad18767 100644 --- a/project/at_start_f415/examples/usb_device/mouse/mdk_v5/mouse.uvoptx +++ b/project/at_start_f415/examples/usb_device/mouse/mdk_v5/mouse.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_device/mouse/mdk_v5/mouse.uvprojx b/project/at_start_f415/examples/usb_device/mouse/mdk_v5/mouse.uvprojx index 0ca6b74..f3c3363 100644 --- a/project/at_start_f415/examples/usb_device/mouse/mdk_v5/mouse.uvprojx +++ b/project/at_start_f415/examples/usb_device/mouse/mdk_v5/mouse.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -529,4 +529,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usb_device/mouse/src/at32f415_clock.c b/project/at_start_f415/examples/usb_device/mouse/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_device/mouse/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_device/mouse/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_device/msc/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_device/msc/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_device/msc/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_device/msc/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_device/msc/mdk_v5/msc.uvoptx b/project/at_start_f415/examples/usb_device/msc/mdk_v5/msc.uvoptx index c738672..199c0cc 100644 --- a/project/at_start_f415/examples/usb_device/msc/mdk_v5/msc.uvoptx +++ b/project/at_start_f415/examples/usb_device/msc/mdk_v5/msc.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_device/msc/mdk_v5/msc.uvprojx b/project/at_start_f415/examples/usb_device/msc/mdk_v5/msc.uvprojx index 8a536c9..8b589b3 100644 --- a/project/at_start_f415/examples/usb_device/msc/mdk_v5/msc.uvprojx +++ b/project/at_start_f415/examples/usb_device/msc/mdk_v5/msc.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -539,4 +539,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usb_device/msc/src/at32f415_clock.c b/project/at_start_f415/examples/usb_device/msc/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_device/msc/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_device/msc/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_device/printer/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_device/printer/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_device/printer/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_device/printer/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_device/printer/mdk_v5/printer.uvoptx b/project/at_start_f415/examples/usb_device/printer/mdk_v5/printer.uvoptx index e18b0fa..6b64563 100644 --- a/project/at_start_f415/examples/usb_device/printer/mdk_v5/printer.uvoptx +++ b/project/at_start_f415/examples/usb_device/printer/mdk_v5/printer.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_device/printer/mdk_v5/printer.uvprojx b/project/at_start_f415/examples/usb_device/printer/mdk_v5/printer.uvprojx index 44d3e07..e6b38f3 100644 --- a/project/at_start_f415/examples/usb_device/printer/mdk_v5/printer.uvprojx +++ b/project/at_start_f415/examples/usb_device/printer/mdk_v5/printer.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -524,4 +524,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usb_device/printer/src/at32f415_clock.c b/project/at_start_f415/examples/usb_device/printer/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_device/printer/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_device/printer/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_device/vcp_loopback/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_device/vcp_loopback/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_device/vcp_loopback/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_device/vcp_loopback/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvoptx b/project/at_start_f415/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvoptx index 09fc68c..96d8bf4 100644 --- a/project/at_start_f415/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvoptx +++ b/project/at_start_f415/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvprojx b/project/at_start_f415/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvprojx index 6e16023..f540cf7 100644 --- a/project/at_start_f415/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvprojx +++ b/project/at_start_f415/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -534,4 +534,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usb_device/vcp_loopback/src/at32f415_clock.c b/project/at_start_f415/examples/usb_device/vcp_loopback/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_device/vcp_loopback/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_device/vcp_loopback/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_device/virtual_comport/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_device/virtual_comport/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_device/virtual_comport/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_device/virtual_comport/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvoptx b/project/at_start_f415/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvoptx index 3ebdde4..61b0968 100644 --- a/project/at_start_f415/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvoptx +++ b/project/at_start_f415/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvprojx b/project/at_start_f415/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvprojx index c44d52e..c88a6fc 100644 --- a/project/at_start_f415/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvprojx +++ b/project/at_start_f415/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -538,6 +538,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/usb_device/virtual_comport/src/at32f415_clock.c b/project/at_start_f415/examples/usb_device/virtual_comport/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_device/virtual_comport/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_device/virtual_comport/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_device/virtual_msc_iap/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_device/virtual_msc_iap/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_device/virtual_msc_iap/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_device/virtual_msc_iap/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvoptx b/project/at_start_f415/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvoptx index 9649d3c..62ca3fc 100644 --- a/project/at_start_f415/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvoptx +++ b/project/at_start_f415/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvprojx b/project/at_start_f415/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvprojx index 664a9da..ac9c25b 100644 --- a/project/at_start_f415/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvprojx +++ b/project/at_start_f415/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -549,4 +549,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usb_device/virtual_msc_iap/src/at32f415_clock.c b/project/at_start_f415/examples/usb_device/virtual_msc_iap/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_device/virtual_msc_iap/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_device/virtual_msc_iap/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_host/cdc_demo/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_host/cdc_demo/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_host/cdc_demo/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_host/cdc_demo/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_host/cdc_demo/mdk_v5/cdc.uvoptx b/project/at_start_f415/examples/usb_host/cdc_demo/mdk_v5/cdc.uvoptx index ae47729..b525903 100644 --- a/project/at_start_f415/examples/usb_host/cdc_demo/mdk_v5/cdc.uvoptx +++ b/project/at_start_f415/examples/usb_host/cdc_demo/mdk_v5/cdc.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_host/cdc_demo/mdk_v5/cdc.uvprojx b/project/at_start_f415/examples/usb_host/cdc_demo/mdk_v5/cdc.uvprojx index 1fd018d..cbf6ba6 100644 --- a/project/at_start_f415/examples/usb_host/cdc_demo/mdk_v5/cdc.uvprojx +++ b/project/at_start_f415/examples/usb_host/cdc_demo/mdk_v5/cdc.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -533,6 +533,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/usb_host/cdc_demo/src/at32f415_clock.c b/project/at_start_f415/examples/usb_host/cdc_demo/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_host/cdc_demo/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_host/cdc_demo/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_host/hid_demo/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_host/hid_demo/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_host/hid_demo/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_host/hid_demo/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvoptx b/project/at_start_f415/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvoptx index a096599..7b10355 100644 --- a/project/at_start_f415/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvoptx +++ b/project/at_start_f415/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvprojx b/project/at_start_f415/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvprojx index aa94f9e..ca831da 100644 --- a/project/at_start_f415/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvprojx +++ b/project/at_start_f415/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -534,4 +534,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usb_host/hid_demo/src/at32f415_clock.c b/project/at_start_f415/examples/usb_host/hid_demo/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_host/hid_demo/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_host/hid_demo/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/usb_host/msc_only_fat32/inc/at32f415_conf.h b/project/at_start_f415/examples/usb_host/msc_only_fat32/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/usb_host/msc_only_fat32/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/usb_host/msc_only_fat32/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvoptx b/project/at_start_f415/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvoptx index b2fad13..09212d4 100644 --- a/project/at_start_f415/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvoptx +++ b/project/at_start_f415/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvprojx b/project/at_start_f415/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvprojx index 71eb85a..5761ea2 100644 --- a/project/at_start_f415/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvprojx +++ b/project/at_start_f415/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -549,4 +549,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f415/examples/usb_host/msc_only_fat32/src/at32f415_clock.c b/project/at_start_f415/examples/usb_host/msc_only_fat32/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/usb_host/msc_only_fat32/src/at32f415_clock.c +++ b/project/at_start_f415/examples/usb_host/msc_only_fat32/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/wdt/wdt_reset/inc/at32f415_conf.h b/project/at_start_f415/examples/wdt/wdt_reset/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/wdt/wdt_reset/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/wdt/wdt_reset/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/wdt/wdt_reset/mdk_v5/wdt_rest.uvoptx b/project/at_start_f415/examples/wdt/wdt_reset/mdk_v5/wdt_rest.uvoptx index 4dfda89..4e75deb 100644 --- a/project/at_start_f415/examples/wdt/wdt_reset/mdk_v5/wdt_rest.uvoptx +++ b/project/at_start_f415/examples/wdt/wdt_reset/mdk_v5/wdt_rest.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/wdt/wdt_reset/mdk_v5/wdt_rest.uvprojx b/project/at_start_f415/examples/wdt/wdt_reset/mdk_v5/wdt_rest.uvprojx index bb8ebe6..d2cf063 100644 --- a/project/at_start_f415/examples/wdt/wdt_reset/mdk_v5/wdt_rest.uvprojx +++ b/project/at_start_f415/examples/wdt/wdt_reset/mdk_v5/wdt_rest.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/wdt/wdt_reset/src/at32f415_clock.c b/project/at_start_f415/examples/wdt/wdt_reset/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/wdt/wdt_reset/src/at32f415_clock.c +++ b/project/at_start_f415/examples/wdt/wdt_reset/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/wdt/wdt_standby/inc/at32f415_conf.h b/project/at_start_f415/examples/wdt/wdt_standby/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/wdt/wdt_standby/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/wdt/wdt_standby/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvoptx b/project/at_start_f415/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvoptx index 2562a5e..4d1e7c1 100644 --- a/project/at_start_f415/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvoptx +++ b/project/at_start_f415/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvprojx b/project/at_start_f415/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvprojx index 5566520..4e70434 100644 --- a/project/at_start_f415/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvprojx +++ b/project/at_start_f415/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/wdt/wdt_standby/src/at32f415_clock.c b/project/at_start_f415/examples/wdt/wdt_standby/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/wdt/wdt_standby/src/at32f415_clock.c +++ b/project/at_start_f415/examples/wdt/wdt_standby/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/examples/wwdt/wwdt_reset/inc/at32f415_conf.h b/project/at_start_f415/examples/wwdt/wwdt_reset/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/project/at_start_f415/examples/wwdt/wwdt_reset/inc/at32f415_conf.h +++ b/project/at_start_f415/examples/wwdt/wwdt_reset/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvoptx b/project/at_start_f415/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvoptx index 95c7979..ff3c8f5 100644 --- a/project/at_start_f415/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvoptx +++ b/project/at_start_f415/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvprojx b/project/at_start_f415/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvprojx index f8fcf3e..4568000 100644 --- a/project/at_start_f415/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvprojx +++ b/project/at_start_f415/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/examples/wwdt/wwdt_reset/src/at32f415_clock.c b/project/at_start_f415/examples/wwdt/wwdt_reset/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/project/at_start_f415/examples/wwdt/wwdt_reset/src/at32f415_clock.c +++ b/project/at_start_f415/examples/wwdt/wwdt_reset/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415/templates/inc/at32f415_conf.h b/project/at_start_f415/templates/inc/at32f415_conf.h index 5b31a7b..daaa0a9 100644 --- a/project/at_start_f415/templates/inc/at32f415_conf.h +++ b/project/at_start_f415/templates/inc/at32f415_conf.h @@ -52,8 +52,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f415/templates/mdk_v5/template.uvoptx b/project/at_start_f415/templates/mdk_v5/template.uvoptx index c9bee83..030171a 100644 --- a/project/at_start_f415/templates/mdk_v5/template.uvoptx +++ b/project/at_start_f415/templates/mdk_v5/template.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f415/templates/mdk_v5/template.uvprojx b/project/at_start_f415/templates/mdk_v5/template.uvprojx index dcbb6e1..0f551fa 100644 --- a/project/at_start_f415/templates/mdk_v5/template.uvprojx +++ b/project/at_start_f415/templates/mdk_v5/template.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -558,6 +558,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f415/templates/src/at32f415_clock.c b/project/at_start_f415/templates/src/at32f415_clock.c index 29172d8..5f33c9b 100644 --- a/project/at_start_f415/templates/src/at32f415_clock.c +++ b/project/at_start_f415/templates/src/at32f415_clock.c @@ -53,12 +53,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f415_Example_list.htm b/project/at_start_f415_Example_list.htm index a539b1f..ca418ac 100644 --- a/project/at_start_f415_Example_list.htm +++ b/project/at_start_f415_Example_list.htm @@ -13,17 +13,19 @@ {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4;} @font-face - {font-family:Calibri; - panose-1:2 15 5 2 2 2 4 3 2 4;} + {font-family:; + panose-1:2 1 6 0 3 1 1 1 1 1;} @font-face {font-family:; panose-1:2 1 6 9 6 1 1 1 1 1;} @font-face - {font-family:"\@"; - panose-1:2 1 6 9 6 1 1 1 1 1;} + {font-family:"\@";} @font-face {font-family:"\@"; panose-1:2 1 6 0 3 1 1 1 1 1;} +@font-face + {font-family:"\@"; + panose-1:2 1 6 0 3 1 1 1 1 1;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {margin:0cm; @@ -31,9 +33,9 @@ text-align:justify; text-justify:inter-ideograph; font-size:10.5pt; - font-family:"Calibri","sans-serif";} + font-family:;} .MsoChpDefault - {font-family:"Calibri","sans-serif";} + {font-family:;} /* Page Definitions */ @page WordSection1 {size:595.3pt 841.9pt; diff --git a/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/iar_v8.2/read_write_boot_memory.eww b/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/iar_v8.2/read_write_boot_memory.eww index 0d7d6e7..479dfba 100644 --- a/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/iar_v8.2/read_write_boot_memory.eww +++ b/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/iar_v8.2/read_write_boot_memory.eww @@ -3,17 +3,4 @@ $WS_DIR$\read_write_boot_memory.ewp - - - all - - read_write_boot_memory - at_start_f403a - - - read_write_boot_memory - at_start_f407 - - - diff --git a/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/inc/at32f415_conf.h b/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/inc/at32f415_conf.h +++ b/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/mdk_v5/read_write_boot_memory.uvoptx b/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/mdk_v5/read_write_boot_memory.uvoptx index 61cabc7..77f9e19 100644 --- a/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/mdk_v5/read_write_boot_memory.uvoptx +++ b/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/mdk_v5/read_write_boot_memory.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/mdk_v5/read_write_boot_memory.uvprojx b/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/mdk_v5/read_write_boot_memory.uvprojx index 17098ec..c5ed657 100644 --- a/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/mdk_v5/read_write_boot_memory.uvprojx +++ b/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/mdk_v5/read_write_boot_memory.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/src/at32f415_clock.c b/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/src/at32f415_clock.c +++ b/utilities/at32f415_boot_memory_ap_demo/read_write_boot_memory/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/iar_v8.2/run_in_boot_memory.ewt b/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/iar_v8.2/run_in_boot_memory.ewt index 810aac9..ab0ddf4 100644 --- a/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/iar_v8.2/run_in_boot_memory.ewt +++ b/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/iar_v8.2/run_in_boot_memory.ewt @@ -2,7 +2,7 @@ 3 - boot_memmory_ap_demo + run_in_boot_memory ARM diff --git a/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/iar_v8.2/run_in_boot_memory.eww b/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/iar_v8.2/run_in_boot_memory.eww index ef4d176..12ec2a5 100644 --- a/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/iar_v8.2/run_in_boot_memory.eww +++ b/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/iar_v8.2/run_in_boot_memory.eww @@ -3,17 +3,4 @@ $WS_DIR$\run_in_boot_memory.ewp - - - all - - run_in_boot_memory - at_start_f403a - - - run_in_boot_memory - at_start_f407 - - - diff --git a/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/inc/at32f415_conf.h b/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/inc/at32f415_conf.h +++ b/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/mdk_v5/run_in_boot_memory.uvoptx b/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/mdk_v5/run_in_boot_memory.uvoptx index 8331236..bbc40b0 100644 --- a/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/mdk_v5/run_in_boot_memory.uvoptx +++ b/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/mdk_v5/run_in_boot_memory.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/mdk_v5/run_in_boot_memory.uvprojx b/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/mdk_v5/run_in_boot_memory.uvprojx index 70a3ac2..424d9e9 100644 --- a/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/mdk_v5/run_in_boot_memory.uvprojx +++ b/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/mdk_v5/run_in_boot_memory.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -525,4 +525,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/src/at32f415_clock.c b/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/src/at32f415_clock.c +++ b/utilities/at32f415_boot_memory_ap_demo/run_in_boot_memory/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f415_freertos_demo/iar_v8.2/freertos_demo.eww b/utilities/at32f415_freertos_demo/iar_v8.2/freertos_demo.eww index 8f3b681..27f473d 100644 --- a/utilities/at32f415_freertos_demo/iar_v8.2/freertos_demo.eww +++ b/utilities/at32f415_freertos_demo/iar_v8.2/freertos_demo.eww @@ -3,17 +3,4 @@ $WS_DIR$\freertos_demo.ewp - - - all - - freertos_demo - at_start_f403a - - - freertos_demo - at_start_f407 - - - diff --git a/utilities/at32f415_freertos_demo/inc/at32f415_conf.h b/utilities/at32f415_freertos_demo/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/utilities/at32f415_freertos_demo/inc/at32f415_conf.h +++ b/utilities/at32f415_freertos_demo/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f415_freertos_demo/mdk_v5/freertos_demo.uvoptx b/utilities/at32f415_freertos_demo/mdk_v5/freertos_demo.uvoptx index baf4aaa..f03762e 100644 --- a/utilities/at32f415_freertos_demo/mdk_v5/freertos_demo.uvoptx +++ b/utilities/at32f415_freertos_demo/mdk_v5/freertos_demo.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 @@ -22,7 +22,7 @@ - freertos_demo + freertos_demo_ac5 0x4 ARM-ADS @@ -169,6 +169,147 @@ + + freertos_demo_ac6 + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 0 + + 0 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + -1 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + user 0 @@ -211,6 +352,18 @@ 0 0 + + 1 + 4 + 1 + 0 + 0 + 0 + ..\src\include_port.c + include_port.c + 0 + 0 + @@ -221,7 +374,7 @@ 0 2 - 4 + 5 1 0 0 @@ -241,7 +394,7 @@ 0 3 - 5 + 6 1 0 0 @@ -253,7 +406,7 @@ 3 - 6 + 7 1 0 0 @@ -265,7 +418,7 @@ 3 - 7 + 8 1 0 0 @@ -277,7 +430,7 @@ 3 - 8 + 9 1 0 0 @@ -289,7 +442,7 @@ 3 - 9 + 10 1 0 0 @@ -301,7 +454,7 @@ 3 - 10 + 11 1 0 0 @@ -313,7 +466,7 @@ 3 - 11 + 12 1 0 0 @@ -325,7 +478,7 @@ 3 - 12 + 13 1 0 0 @@ -337,7 +490,7 @@ 3 - 13 + 14 1 0 0 @@ -349,7 +502,7 @@ 3 - 14 + 15 1 0 0 @@ -361,7 +514,7 @@ 3 - 15 + 16 1 0 0 @@ -373,7 +526,7 @@ 3 - 16 + 17 1 0 0 @@ -385,7 +538,7 @@ 3 - 17 + 18 1 0 0 @@ -397,7 +550,7 @@ 3 - 18 + 19 1 0 0 @@ -409,7 +562,7 @@ 3 - 19 + 20 1 0 0 @@ -421,7 +574,7 @@ 3 - 20 + 21 1 0 0 @@ -433,7 +586,7 @@ 3 - 21 + 22 1 0 0 @@ -445,7 +598,7 @@ 3 - 22 + 23 1 0 0 @@ -457,7 +610,7 @@ 3 - 23 + 24 1 0 0 @@ -469,7 +622,7 @@ 3 - 24 + 25 1 0 0 @@ -481,7 +634,7 @@ 3 - 25 + 26 1 0 0 @@ -501,7 +654,7 @@ 0 4 - 26 + 27 1 0 0 @@ -513,7 +666,7 @@ 4 - 27 + 28 2 0 0 @@ -533,7 +686,7 @@ 0 5 - 28 + 29 1 0 0 @@ -545,7 +698,7 @@ 5 - 29 + 30 1 0 0 @@ -557,7 +710,7 @@ 5 - 30 + 31 1 0 0 @@ -569,7 +722,7 @@ 5 - 31 + 32 1 0 0 @@ -581,7 +734,7 @@ 5 - 32 + 33 1 0 0 @@ -593,7 +746,7 @@ 5 - 33 + 34 1 0 0 @@ -605,7 +758,7 @@ 5 - 34 + 35 1 0 0 @@ -617,7 +770,7 @@ 5 - 35 + 36 1 0 0 @@ -627,18 +780,6 @@ 0 0 - - 5 - 36 - 1 - 0 - 0 - 0 - ..\..\..\middlewares\freertos\source\portable\rvds\ARM_CM3\port.c - port.c - 0 - 0 - diff --git a/utilities/at32f415_freertos_demo/mdk_v5/freertos_demo.uvprojx b/utilities/at32f415_freertos_demo/mdk_v5/freertos_demo.uvprojx index 94764d6..6f39ae5 100644 --- a/utilities/at32f415_freertos_demo/mdk_v5/freertos_demo.uvprojx +++ b/utilities/at32f415_freertos_demo/mdk_v5/freertos_demo.uvprojx @@ -7,16 +7,16 @@ - freertos_demo + freertos_demo_ac5 0x4 ARM-ADS - 5060061::V5.06 update 1 (build 61)::ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC 0 -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -48,7 +48,7 @@ 1 .\objects\ - freertos_demo + freertos_demo_ac5 1 0 1 @@ -327,8 +327,8 @@ 0 0 0 - 1 - 1 + 3 + 3 1 1 0 @@ -397,6 +397,11 @@ 1 ..\src\main.c + + include_port.c + 1 + ..\src\include_port.c + @@ -577,10 +582,595 @@ 1 ..\..\..\middlewares\freertos\source\portable\memmang\heap_4.c + + + + readme + - port.c + readme.txt + 5 + ..\readme.txt + + + + + + + freertos_demo_ac6 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + -AT32F415RCT7 + ArteryTek + ArteryTek.AT32F415_DFP.2.0.6 + IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0AT32F415_256 -FS08000000 -FL0100000 -FP0($$Device:-AT32F415RCT7$Flash\AT32F415_256.FLM)) + 0 + $$Device:-AT32F415RCT7$Device\Include\at32f415.h + + + + + + + + + + $$Device:-AT32F415RCT7$SVD\AT32F415xx_v2.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\objects\ + freertos_demo_ac6 + 1 + 0 + 1 + 1 + 1 + .\listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + AT32F415RCT7,USE_STDPERIPH_DRIVER,AT_START_F415_V1 + + ..\inc;..\..\..\libraries\drivers\inc;..\..\..\project\at32f415_board;..\..\..\libraries\cmsis\cm4\device_support;..\..\..\libraries\cmsis\cm4\core_support;..\..\..\middlewares\freertos\source\include;..\..\..\middlewares\freertos\source\portable\memmang;..\..\..\middlewares\freertos\source\portable\GCC\ARM_CM3 + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + user + + + at32f415_clock.c 1 - ..\..\..\middlewares\freertos\source\portable\rvds\ARM_CM3\port.c + ..\src\at32f415_clock.c + + + at32f415_int.c + 1 + ..\src\at32f415_int.c + + + main.c + 1 + ..\src\main.c + + + include_port.c + 1 + ..\src\include_port.c + + + + + bsp + + + at32f415_board.c + 1 + ..\..\..\project\at32f415_board\at32f415_board.c + + + + + firmware + + + at32f415_adc.c + 1 + ..\..\..\libraries\drivers\src\at32f415_adc.c + + + at32f415_can.c + 1 + ..\..\..\libraries\drivers\src\at32f415_can.c + + + at32f415_cmp.c + 1 + ..\..\..\libraries\drivers\src\at32f415_cmp.c + + + at32f415_crc.c + 1 + ..\..\..\libraries\drivers\src\at32f415_crc.c + + + at32f415_crm.c + 1 + ..\..\..\libraries\drivers\src\at32f415_crm.c + + + at32f415_debug.c + 1 + ..\..\..\libraries\drivers\src\at32f415_debug.c + + + at32f415_dma.c + 1 + ..\..\..\libraries\drivers\src\at32f415_dma.c + + + at32f415_ertc.c + 1 + ..\..\..\libraries\drivers\src\at32f415_ertc.c + + + at32f415_exint.c + 1 + ..\..\..\libraries\drivers\src\at32f415_exint.c + + + at32f415_flash.c + 1 + ..\..\..\libraries\drivers\src\at32f415_flash.c + + + at32f415_gpio.c + 1 + ..\..\..\libraries\drivers\src\at32f415_gpio.c + + + at32f415_i2c.c + 1 + ..\..\..\libraries\drivers\src\at32f415_i2c.c + + + at32f415_misc.c + 1 + ..\..\..\libraries\drivers\src\at32f415_misc.c + + + at32f415_pwc.c + 1 + ..\..\..\libraries\drivers\src\at32f415_pwc.c + + + at32f415_sdio.c + 1 + ..\..\..\libraries\drivers\src\at32f415_sdio.c + + + at32f415_spi.c + 1 + ..\..\..\libraries\drivers\src\at32f415_spi.c + + + at32f415_tmr.c + 1 + ..\..\..\libraries\drivers\src\at32f415_tmr.c + + + at32f415_usart.c + 1 + ..\..\..\libraries\drivers\src\at32f415_usart.c + + + at32f415_usb.c + 1 + ..\..\..\libraries\drivers\src\at32f415_usb.c + + + at32f415_wdt.c + 1 + ..\..\..\libraries\drivers\src\at32f415_wdt.c + + + at32f415_wwdt.c + 1 + ..\..\..\libraries\drivers\src\at32f415_wwdt.c + + + + + cmsis + + + system_at32f415.c + 1 + ..\..\..\libraries\cmsis\cm4\device_support\system_at32f415.c + + + startup_at32f415.s + 2 + ..\..\..\libraries\cmsis\cm4\device_support\startup\mdk\startup_at32f415.s + + + + + freertos + + + croutine.c + 1 + ..\..\..\middlewares\freertos\source\croutine.c + + + event_groups.c + 1 + ..\..\..\middlewares\freertos\source\event_groups.c + + + list.c + 1 + ..\..\..\middlewares\freertos\source\list.c + + + queue.c + 1 + ..\..\..\middlewares\freertos\source\queue.c + + + stream_buffer.c + 1 + ..\..\..\middlewares\freertos\source\stream_buffer.c + + + tasks.c + 1 + ..\..\..\middlewares\freertos\source\tasks.c + + + timers.c + 1 + ..\..\..\middlewares\freertos\source\timers.c + + + heap_4.c + 1 + ..\..\..\middlewares\freertos\source\portable\memmang\heap_4.c @@ -604,4 +1194,19 @@ + + + + freertos_demo + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f415_freertos_demo/src/at32f415_clock.c b/utilities/at32f415_freertos_demo/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/utilities/at32f415_freertos_demo/src/at32f415_clock.c +++ b/utilities/at32f415_freertos_demo/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f415_freertos_demo/src/include_port.c b/utilities/at32f415_freertos_demo/src/include_port.c new file mode 100644 index 0000000..d23a5d4 --- /dev/null +++ b/utilities/at32f415_freertos_demo/src/include_port.c @@ -0,0 +1,50 @@ +/** + ************************************************************************** + * @file include_port.c + * @brief include_port program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/** @addtogroup UTILITIES_examples + * @{ + */ + +/** @addtogroup FreeRTOS_demo + * @{ + */ + +/* support ac5 and ac6 compiler */ +#if (__ARMCC_VERSION > 6000000) + +#include "..\..\..\middlewares\freertos\source\portable\GCC\ARM_CM3\port.c" + +#else + +#include "..\..\..\middlewares\freertos\source\portable\rvds\ARM_CM3\port.c" + +#endif + +/** + * @} + */ + +/** + * @} + */ diff --git a/utilities/at32f415_gen_random_number_demo/iar_v8.2/gen_ramdom_number.eww b/utilities/at32f415_gen_random_number_demo/iar_v8.2/gen_ramdom_number.eww index 4b30601..9f21a92 100644 --- a/utilities/at32f415_gen_random_number_demo/iar_v8.2/gen_ramdom_number.eww +++ b/utilities/at32f415_gen_random_number_demo/iar_v8.2/gen_ramdom_number.eww @@ -3,17 +3,4 @@ $WS_DIR$\gen_ramdom_number.ewp - - - all - - gen_ramdom_number - at_start_f403a - - - gen_ramdom_number - at_start_f407 - - - diff --git a/utilities/at32f415_gen_random_number_demo/inc/at32f415_conf.h b/utilities/at32f415_gen_random_number_demo/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/utilities/at32f415_gen_random_number_demo/inc/at32f415_conf.h +++ b/utilities/at32f415_gen_random_number_demo/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f415_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvoptx b/utilities/at32f415_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvoptx index 41807e4..1541ecd 100644 --- a/utilities/at32f415_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvoptx +++ b/utilities/at32f415_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f415_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvprojx b/utilities/at32f415_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvprojx index 86aa9e4..9378bb2 100644 --- a/utilities/at32f415_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvprojx +++ b/utilities/at32f415_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f415_gen_random_number_demo/src/at32f415_clock.c b/utilities/at32f415_gen_random_number_demo/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/utilities/at32f415_gen_random_number_demo/src/at32f415_clock.c +++ b/utilities/at32f415_gen_random_number_demo/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f415_slib_demo/project_l0/iar_v8.2/project_l0.ewt b/utilities/at32f415_slib_demo/project_l0/iar_v8.2/project_l0.ewt index 7fc37c9..7baa6ea 100644 --- a/utilities/at32f415_slib_demo/project_l0/iar_v8.2/project_l0.ewt +++ b/utilities/at32f415_slib_demo/project_l0/iar_v8.2/project_l0.ewt @@ -2,7 +2,7 @@ 3 - at_start_f403a + project_l0 ARM @@ -1185,1190 +1185,6 @@ - - at_start_f407 - - ARM - - 0 - - C-STAT - 261 - - 261 - - 0 - - 1 - 600 - 0 - 2 - 0 - 1 - 100 - - - 1.5.2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RuntimeChecking - 0 - - 2 - 1 - 0 - - - - - - - - - - - - - - - - - - - - bsp diff --git a/utilities/at32f415_slib_demo/project_l0/iar_v8.2/project_l0.eww b/utilities/at32f415_slib_demo/project_l0/iar_v8.2/project_l0.eww index 9b28de9..4e312f1 100644 --- a/utilities/at32f415_slib_demo/project_l0/iar_v8.2/project_l0.eww +++ b/utilities/at32f415_slib_demo/project_l0/iar_v8.2/project_l0.eww @@ -3,17 +3,4 @@ $WS_DIR$\project_l0.ewp - - - all - - project_l0 - at_start_f403a - - - project_l0 - at_start_f407 - - - diff --git a/utilities/at32f415_slib_demo/project_l0/inc/at32f415_conf.h b/utilities/at32f415_slib_demo/project_l0/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/utilities/at32f415_slib_demo/project_l0/inc/at32f415_conf.h +++ b/utilities/at32f415_slib_demo/project_l0/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f415_slib_demo/project_l0/mdk_v5/project_l0.uvoptx b/utilities/at32f415_slib_demo/project_l0/mdk_v5/project_l0.uvoptx index fcae358..64e5ebe 100644 --- a/utilities/at32f415_slib_demo/project_l0/mdk_v5/project_l0.uvoptx +++ b/utilities/at32f415_slib_demo/project_l0/mdk_v5/project_l0.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f415_slib_demo/project_l0/mdk_v5/project_l0.uvprojx b/utilities/at32f415_slib_demo/project_l0/mdk_v5/project_l0.uvprojx index 6e320ff..6eabd2a 100644 --- a/utilities/at32f415_slib_demo/project_l0/mdk_v5/project_l0.uvprojx +++ b/utilities/at32f415_slib_demo/project_l0/mdk_v5/project_l0.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IROM(0x08000000,0x100000) IRAM(0x20000000,0x38000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -662,4 +662,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f415_slib_demo/project_l0/src/at32f415_clock.c b/utilities/at32f415_slib_demo/project_l0/src/at32f415_clock.c index 151fab5..6485c06 100644 --- a/utilities/at32f415_slib_demo/project_l0/src/at32f415_clock.c +++ b/utilities/at32f415_slib_demo/project_l0/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f415_slib_demo/project_l1/iar_v8.2/project_l1.ewt b/utilities/at32f415_slib_demo/project_l1/iar_v8.2/project_l1.ewt index f571dc9..f803876 100644 --- a/utilities/at32f415_slib_demo/project_l1/iar_v8.2/project_l1.ewt +++ b/utilities/at32f415_slib_demo/project_l1/iar_v8.2/project_l1.ewt @@ -2,7 +2,7 @@ 3 - at_start_f403a + project_l1 ARM @@ -1185,1190 +1185,6 @@ - - at_start_f407 - - ARM - - 0 - - C-STAT - 261 - - 261 - - 0 - - 1 - 600 - 0 - 2 - 0 - 1 - 100 - - - 1.5.2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RuntimeChecking - 0 - - 2 - 1 - 0 - - - - - - - - - - - - - - - - - - - - bsp diff --git a/utilities/at32f415_slib_demo/project_l1/iar_v8.2/project_l1.eww b/utilities/at32f415_slib_demo/project_l1/iar_v8.2/project_l1.eww index 3785971..361f7c5 100644 --- a/utilities/at32f415_slib_demo/project_l1/iar_v8.2/project_l1.eww +++ b/utilities/at32f415_slib_demo/project_l1/iar_v8.2/project_l1.eww @@ -3,17 +3,4 @@ $WS_DIR$\project_l1.ewp - - - all - - project_l1 - at_start_f403a - - - project_l1 - at_start_f407 - - - diff --git a/utilities/at32f415_slib_demo/project_l1/inc/at32f415_conf.h b/utilities/at32f415_slib_demo/project_l1/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/utilities/at32f415_slib_demo/project_l1/inc/at32f415_conf.h +++ b/utilities/at32f415_slib_demo/project_l1/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f415_slib_demo/project_l1/mdk_v5/project_l1.uvoptx b/utilities/at32f415_slib_demo/project_l1/mdk_v5/project_l1.uvoptx index 1f03a6f..956ec20 100644 --- a/utilities/at32f415_slib_demo/project_l1/mdk_v5/project_l1.uvoptx +++ b/utilities/at32f415_slib_demo/project_l1/mdk_v5/project_l1.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f415_slib_demo/project_l1/mdk_v5/project_l1.uvprojx b/utilities/at32f415_slib_demo/project_l1/mdk_v5/project_l1.uvprojx index e9b9e63..dccc86f 100644 --- a/utilities/at32f415_slib_demo/project_l1/mdk_v5/project_l1.uvprojx +++ b/utilities/at32f415_slib_demo/project_l1/mdk_v5/project_l1.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IROM(0x08000000,0x100000) IRAM(0x20000000,0x38000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -494,4 +494,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f415_slib_demo/project_l1/src/at32f415_clock.c b/utilities/at32f415_slib_demo/project_l1/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/utilities/at32f415_slib_demo/project_l1/src/at32f415_clock.c +++ b/utilities/at32f415_slib_demo/project_l1/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.ewt b/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.ewt index d24a057..740d68d 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.ewt +++ b/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.ewt @@ -2,1191 +2,7 @@ 3 - at_start_f403a - - ARM - - 1 - - C-STAT - 261 - - 261 - - 0 - - 1 - 600 - 0 - 2 - 0 - 1 - 100 - - - 1.5.2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RuntimeChecking - 0 - - 2 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - at_start_f407 + app_led3_toggle ARM diff --git a/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.eww b/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.eww index 1efb72e..7b2d3d7 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.eww +++ b/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.eww @@ -3,17 +3,4 @@ $WS_DIR$\app_led3_toggle.ewp - - - all - - app_led3_toggle - at_start_f403a - - - app_led3_toggle - at_start_f407 - - - diff --git a/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/inc/at32f415_conf.h b/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/inc/at32f415_conf.h +++ b/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx b/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx index 842c06f..5644c24 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx +++ b/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx b/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx index a417aad..1d82224 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx +++ b/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IROM(0x08000000,0x100000) IRAM(0x20000000,0x38000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -494,4 +494,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/src/at32f415_clock.c b/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/src/at32f415_clock.c +++ b/utilities/at32f415_usart_iap_demo/source_code/app_led3_toggle/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/inc/at32f415_conf.h b/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/inc/at32f415_conf.h +++ b/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx b/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx index 2e245d2..5ca829e 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx +++ b/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx b/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx index eed1327..bf0ff22 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx +++ b/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IROM(0x08000000,0x100000) IRAM(0x20000000,0x38000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -494,4 +494,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/src/at32f415_clock.c b/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/src/at32f415_clock.c +++ b/utilities/at32f415_usart_iap_demo/source_code/app_led4_toggle/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f415_usart_iap_demo/source_code/bootloader/iar_v8.2/bootloader.ewt b/utilities/at32f415_usart_iap_demo/source_code/bootloader/iar_v8.2/bootloader.ewt index 7ee6e0f..fbcc4b7 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/bootloader/iar_v8.2/bootloader.ewt +++ b/utilities/at32f415_usart_iap_demo/source_code/bootloader/iar_v8.2/bootloader.ewt @@ -2,1193 +2,7 @@ 3 - 403A_Project - - ARM - - 1 - - C-STAT - 261 - - 261 - - 0 - - 1 - 600 - 0 - 2 - 0 - 1 - 100 - - - 1.5.5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RuntimeChecking - 0 - - 2 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - 407_Project + bootloader ARM diff --git a/utilities/at32f415_usart_iap_demo/source_code/bootloader/iar_v8.2/bootloader.eww b/utilities/at32f415_usart_iap_demo/source_code/bootloader/iar_v8.2/bootloader.eww index ddd092f..76adff6 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/bootloader/iar_v8.2/bootloader.eww +++ b/utilities/at32f415_usart_iap_demo/source_code/bootloader/iar_v8.2/bootloader.eww @@ -3,17 +3,4 @@ $WS_DIR$\bootloader.ewp - - - all - - bootloader - at_start_f403a - - - bootloader - at_start_f407 - - - diff --git a/utilities/at32f415_usart_iap_demo/source_code/bootloader/inc/at32f415_conf.h b/utilities/at32f415_usart_iap_demo/source_code/bootloader/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/bootloader/inc/at32f415_conf.h +++ b/utilities/at32f415_usart_iap_demo/source_code/bootloader/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f415_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx b/utilities/at32f415_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx index 9b6b1d9..ff819d2 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx +++ b/utilities/at32f415_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f415_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx b/utilities/at32f415_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx index d965b05..0956ccd 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx +++ b/utilities/at32f415_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IROM(0x08000000,0x100000) IRAM(0x20000000,0x38000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -499,4 +499,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f415_usart_iap_demo/source_code/bootloader/src/at32f415_clock.c b/utilities/at32f415_usart_iap_demo/source_code/bootloader/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/utilities/at32f415_usart_iap_demo/source_code/bootloader/src/at32f415_clock.c +++ b/utilities/at32f415_usart_iap_demo/source_code/bootloader/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f415_usart_iap_demo/tool_release/IAP_Programmer.exe b/utilities/at32f415_usart_iap_demo/tool_release/IAP_Programmer.exe index bba8fe7..72860c2 100644 Binary files a/utilities/at32f415_usart_iap_demo/tool_release/IAP_Programmer.exe and b/utilities/at32f415_usart_iap_demo/tool_release/IAP_Programmer.exe differ diff --git a/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.eww b/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.eww index 1efb72e..7b2d3d7 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.eww +++ b/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.eww @@ -3,17 +3,4 @@ $WS_DIR$\app_led3_toggle.ewp - - - all - - app_led3_toggle - at_start_f403a - - - app_led3_toggle - at_start_f407 - - - diff --git a/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/inc/at32f415_conf.h b/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/inc/at32f415_conf.h +++ b/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx b/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx index 323c56a..f5115f9 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx +++ b/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx b/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx index 74dfb85..ed9487a 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx +++ b/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -529,4 +529,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/src/at32f415_clock.c b/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/src/at32f415_clock.c +++ b/utilities/at32f415_usb_iap_demo/source_code/app_led3_toggle/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/inc/at32f415_conf.h b/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/inc/at32f415_conf.h +++ b/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx b/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx index d9bd7e8..94caa68 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx +++ b/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx b/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx index ed84c22..bff3c1a 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx +++ b/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -529,4 +529,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/src/at32f415_clock.c b/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/src/at32f415_clock.c +++ b/utilities/at32f415_usb_iap_demo/source_code/app_led4_toggle/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f415_usb_iap_demo/source_code/bootloader/iar_v8.2/bootloader.eww b/utilities/at32f415_usb_iap_demo/source_code/bootloader/iar_v8.2/bootloader.eww index ddd092f..76adff6 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/bootloader/iar_v8.2/bootloader.eww +++ b/utilities/at32f415_usb_iap_demo/source_code/bootloader/iar_v8.2/bootloader.eww @@ -3,17 +3,4 @@ $WS_DIR$\bootloader.ewp - - - all - - bootloader - at_start_f403a - - - bootloader - at_start_f407 - - - diff --git a/utilities/at32f415_usb_iap_demo/source_code/bootloader/inc/at32f415_conf.h b/utilities/at32f415_usb_iap_demo/source_code/bootloader/inc/at32f415_conf.h index bb93125..118874f 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/bootloader/inc/at32f415_conf.h +++ b/utilities/at32f415_usb_iap_demo/source_code/bootloader/inc/at32f415_conf.h @@ -44,8 +44,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ -#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f415_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx b/utilities/at32f415_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx index 474474c..47bf3d0 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx +++ b/utilities/at32f415_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f415_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx b/utilities/at32f415_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx index a328bc4..9c68555 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx +++ b/utilities/at32f415_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx @@ -16,7 +16,7 @@ -AT32F415RCT7 ArteryTek - ArteryTek.AT32F415_DFP.2.0.6 + ArteryTek.AT32F415_DFP.2.0.0 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -529,4 +529,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f415_usb_iap_demo/source_code/bootloader/src/at32f415_clock.c b/utilities/at32f415_usb_iap_demo/source_code/bootloader/src/at32f415_clock.c index 826e40a..f137828 100644 --- a/utilities/at32f415_usb_iap_demo/source_code/bootloader/src/at32f415_clock.c +++ b/utilities/at32f415_usb_iap_demo/source_code/bootloader/src/at32f415_clock.c @@ -45,12 +45,12 @@ */ void system_clock_config(void) { - /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - /* reset crm */ crm_reset(); + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f415_usb_iap_demo/tool_release/IAP_Programmer.exe b/utilities/at32f415_usb_iap_demo/tool_release/IAP_Programmer.exe index bba8fe7..72860c2 100644 Binary files a/utilities/at32f415_usb_iap_demo/tool_release/IAP_Programmer.exe and b/utilities/at32f415_usb_iap_demo/tool_release/IAP_Programmer.exe differ