ArteryTek/AT32F415_Firmware_Library
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update version to v2.0.8

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This commit is contained in:
Artery-MCU
2022-11-22 18:18:07 +08:00
parent d95c5fb9e8
commit d4910499d3
1365 changed files with 13037 additions and 14600 deletions
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2
project/at_start_f415/examples/crm/clock_failure_detection/inc/at32f415_clock.h
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@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_clock.h
* @version v2.0.7
* @date 2022-08-16
* @brief header file of clock program
**************************************************************************
* Copyright notice & Disclaimer

2
project/at_start_f415/examples/crm/clock_failure_detection/inc/at32f415_conf.h
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@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_conf.h
* @version v2.0.7
* @date 2022-08-16
* @brief at32f415 config header file
**************************************************************************
* Copyright notice & Disclaimer

2
project/at_start_f415/examples/crm/clock_failure_detection/inc/at32f415_int.h
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@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_int.h
* @version v2.0.7
* @date 2022-08-16
* @brief header file of main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer

4
project/at_start_f415/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvoptx
View File

@@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f415/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvprojx
View File

@@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F415RCT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F415_DFP.2.0.0</PackID>
<PackID>ArteryTek.AT32F415_DFP.2.0.6</PackID>
<Cpu>IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@@ -473,11 +473,6 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

4
project/at_start_f415/examples/crm/clock_failure_detection/readme.txt
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@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file readme.txt
* @version v2.0.7
* @date 2022-08-16
* @brief readme
**************************************************************************
*/
@@ -10,4 +8,4 @@
this demo is based on the at-start board, in this demo, swith sclk to
pll based hick when hext clock failure occured. pa8 output crm_clkout_pll_div_4
and led2 fresh per 200 ms.
for more detailed information. please refer to the application note document AN0117.
for more detailed information. please refer to the application note document AN0117.

6
project/at_start_f415/examples/crm/clock_failure_detection/src/at32f415_clock.c
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_clock.c
* @version v2.0.7
* @date 2022-08-16
* @brief system clock config program
**************************************************************************
* Copyright notice & Disclaimer
@@ -74,10 +72,10 @@ void system_clock_config(void)
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk */
/* config apb2clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk */
/* config apb1clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb1_div_set(CRM_APB1_DIV_2);
/* enable auto step mode */

2
project/at_start_f415/examples/crm/clock_failure_detection/src/at32f415_int.c
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_int.c
* @version v2.0.7
* @date 2022-08-16
* @brief main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer

6
project/at_start_f415/examples/crm/clock_failure_detection/src/main.c
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@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file main.c
* @version v2.0.7
* @date 2022-08-16
* @brief main program
**************************************************************************
* Copyright notice & Disclaimer
@@ -136,10 +134,10 @@ static void sclk_144m_hick_config(void)
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk */
/* config apb2clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk */
/* config apb1clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb1_div_set(CRM_APB1_DIV_2);
/* enable auto step mode */

2
project/at_start_f415/examples/crm/pll_config2/inc/at32f415_clock.h
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_clock.h
* @version v2.0.7
* @date 2022-08-16
* @brief header file of clock program
**************************************************************************
* Copyright notice & Disclaimer

2
project/at_start_f415/examples/crm/pll_config2/inc/at32f415_conf.h
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_conf.h
* @version v2.0.7
* @date 2022-08-16
* @brief at32f415 config header file
**************************************************************************
* Copyright notice & Disclaimer

2
project/at_start_f415/examples/crm/pll_config2/inc/at32f415_int.h
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_int.h
* @version v2.0.7
* @date 2022-08-16
* @brief header file of main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer

4
project/at_start_f415/examples/crm/pll_config2/mdk_v5/pll_config2.uvoptx
View File

@@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f415/examples/crm/pll_config2/mdk_v5/pll_config2.uvprojx
View File

@@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F415RCT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F415_DFP.2.0.0</PackID>
<PackID>ArteryTek.AT32F415_DFP.2.0.6</PackID>
<Cpu>IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@@ -473,11 +473,6 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

4
project/at_start_f415/examples/crm/pll_config2/readme.txt
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file readme.txt
* @version v2.0.7
* @date 2022-08-16
* @brief readme
**************************************************************************
*/
@@ -10,4 +8,4 @@
this demo is based on the at-start board, in this demo, 150 mhz sysclk
configed by crm_pll_config2 function. pa8 output crm_clkout_pll_div_4.
led2 fresh per 100 ms.
for more detailed information. please refer to the application note document AN0117.
for more detailed information. please refer to the application note document AN0117.

6
project/at_start_f415/examples/crm/pll_config2/src/at32f415_clock.c
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_clock.c
* @version v2.0.7
* @date 2022-08-16
* @brief system clock config program
**************************************************************************
* Copyright notice & Disclaimer
@@ -76,10 +74,10 @@ void system_clock_config(void)
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk */
/* config apb2clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk */
/* config apb1clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb1_div_set(CRM_APB1_DIV_2);
/* enable auto step mode */

2
project/at_start_f415/examples/crm/pll_config2/src/at32f415_int.c
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_int.c
* @version v2.0.7
* @date 2022-08-16
* @brief main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer

2
project/at_start_f415/examples/crm/pll_config2/src/main.c
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file main.c
* @version v2.0.7
* @date 2022-08-16
* @brief main program
**************************************************************************
* Copyright notice & Disclaimer

2
project/at_start_f415/examples/crm/sysclk_switch/inc/at32f415_clock.h
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_clock.h
* @version v2.0.7
* @date 2022-08-16
* @brief header file of clock program
**************************************************************************
* Copyright notice & Disclaimer

2
project/at_start_f415/examples/crm/sysclk_switch/inc/at32f415_conf.h
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_conf.h
* @version v2.0.7
* @date 2022-08-16
* @brief at32f415 config header file
**************************************************************************
* Copyright notice & Disclaimer

2
project/at_start_f415/examples/crm/sysclk_switch/inc/at32f415_int.h
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_int.h
* @version v2.0.7
* @date 2022-08-16
* @brief header file of main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer

4
project/at_start_f415/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvoptx
View File

@@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f415/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvprojx
View File

@@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F415RCT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F415_DFP.2.0.0</PackID>
<PackID>ArteryTek.AT32F415_DFP.2.0.6</PackID>
<Cpu>IRAM(0x20000000,0x8000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@@ -473,11 +473,6 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

4
project/at_start_f415/examples/crm/sysclk_switch/readme.txt
View File

@@ -1,12 +1,10 @@
/**
**************************************************************************
* @file readme.txt
* @version v2.0.7
* @date 2022-08-16
* @brief readme
**************************************************************************
*/
this demo is based on the at-start board, in this demo, swith sclk by pressed
button. led4 toggle, pa8 output crm_clkout_pll_div_4. led2 fresh per 100 ms.
for more detailed information. please refer to the application note document AN0117.
for more detailed information. please refer to the application note document AN0117.

6
project/at_start_f415/examples/crm/sysclk_switch/src/at32f415_clock.c
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_clock.c
* @version v2.0.7
* @date 2022-08-16
* @brief system clock config program
**************************************************************************
* Copyright notice & Disclaimer
@@ -74,10 +72,10 @@ void system_clock_config(void)
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk */
/* config apb2clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk */
/* config apb1clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb1_div_set(CRM_APB1_DIV_2);
/* enable auto step mode */

2
project/at_start_f415/examples/crm/sysclk_switch/src/at32f415_int.c
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f415_int.c
* @version v2.0.7
* @date 2022-08-16
* @brief main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer

10
project/at_start_f415/examples/crm/sysclk_switch/src/main.c
View File

@@ -1,8 +1,6 @@
/**
**************************************************************************
* @file main.c
* @version v2.0.7
* @date 2022-08-16
* @brief main program
**************************************************************************
* Copyright notice & Disclaimer
@@ -133,10 +131,10 @@ static void sclk_64m_hick_config(void)
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk */
/* config apb2clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk */
/* config apb1clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb1_div_set(CRM_APB1_DIV_2);
/* enable auto step mode */
@@ -210,10 +208,10 @@ static void sclk_96m_hext_config(void)
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk */
/* config apb2clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk */
/* config apb1clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
crm_apb1_div_set(CRM_APB1_DIV_2);
/* enable auto step mode */