ArteryTek/AT32F415_Firmware_Library
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update version to v2.0.4

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Artery-MCU
2022-04-11 19:32:28 +08:00
parent 07d7347ba4
commit ccd0f1e108
1470 changed files with 213761 additions and 13939 deletions
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38
libraries/drivers/inc/at32f415_debug.h
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@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f415_debug.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f415 debug header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,8 +31,8 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f415.h"
@@ -48,17 +48,17 @@ extern "C" {
* @{
*/
#define DEBUG_SLEEP ((uint32_t)0x00000001) /*!< debug sleep mode */
#define DEBUG_DEEPSLEEP ((uint32_t)0x00000002) /*!< debug deepsleep mode */
#define DEBUG_DEEPSLEEP ((uint32_t)0x00000002) /*!< debug deepsleep mode */
#define DEBUG_STANDBY ((uint32_t)0x00000004) /*!< debug standby mode */
#define DEBUG_WDT_PAUSE ((uint32_t)0x00000100) /*!< debug watchdog timer pause */
#define DEBUG_WWDT_PAUSE ((uint32_t)0x00000200) /*!< debug window watchdog timer pause */
#define DEBUG_TMR1_PAUSE ((uint32_t)0x00000400) /*!< debug timer1 pause */
#define DEBUG_WWDT_PAUSE ((uint32_t)0x00000200) /*!< debug window watchdog timer pause */
#define DEBUG_TMR1_PAUSE ((uint32_t)0x00000400) /*!< debug timer1 pause */
#define DEBUG_TMR3_PAUSE ((uint32_t)0x00001000) /*!< debug timer3 pause */
#define DEBUG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< debug i2c1 smbus timeout */
#define DEBUG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< debug i2c1 smbus timeout */
#define DEBUG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< debug i2c2 smbus timeout */
#define DEBUG_TMR2_PAUSE ((uint32_t)0x00000800) /*!< debug timer2 pause */
#define DEBUG_TMR4_PAUSE ((uint32_t)0x00002000) /*!< debug timer4 pause */
#define DEBUG_CAN1_PAUSE ((uint32_t)0x00004000) /*!< debug can1 pause */
#define DEBUG_TMR2_PAUSE ((uint32_t)0x00000800) /*!< debug timer2 pause */
#define DEBUG_TMR4_PAUSE ((uint32_t)0x00002000) /*!< debug timer4 pause */
#define DEBUG_CAN1_PAUSE ((uint32_t)0x00004000) /*!< debug can1 pause */
#define DEBUG_TMR5_PAUSE ((uint32_t)0x00040000) /*!< debug timer5 pause */
#define DEBUG_TMR9_PAUSE ((uint32_t)0x10000000) /*!< debug timer9 pause */
#define DEBUG_TMR10_PAUSE ((uint32_t)0x20000000) /*!< debug timer10 pause */
@@ -101,9 +101,9 @@ typedef struct
__IO uint32_t standby_debug : 1;/* [2] */
__IO uint32_t reserved1 : 2;/* [4:3] */
__IO uint32_t trace_ioen : 1;/* [5] */
__IO uint32_t trace_mode : 2;/* [7:6] */
__IO uint32_t wdt_pause : 1;/* [8] */
__IO uint32_t wwdt_pause : 1;/* [9] */
__IO uint32_t trace_mode : 2;/* [7:6] */
__IO uint32_t wdt_pause : 1;/* [8] */
__IO uint32_t wwdt_pause : 1;/* [9] */
__IO uint32_t tmr1_pause : 1;/* [10] */
__IO uint32_t tmr2_pause : 1;/* [11] */
__IO uint32_t tmr3_pause : 1;/* [12] */