ArteryTek/AT32F415_Firmware_Library
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update version to v2.0.4

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Artery-MCU
2022-04-11 19:32:28 +08:00
parent 07d7347ba4
commit ccd0f1e108
1470 changed files with 213761 additions and 13939 deletions
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40
libraries/cmsis/cm4/device_support/at32f415.h
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@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f415.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f415 header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -42,7 +42,7 @@ extern "C" {
/** @addtogroup AT32F415
* @{
*/
/** @addtogroup Library_configuration_section
* @{
*/
@@ -73,8 +73,8 @@ extern "C" {
#ifndef USE_STDPERIPH_DRIVER
/**
* @brief comment the line below if you will not use the peripherals drivers.
* in this case, these drivers will not be included and the application code will
* be based on direct access to peripherals registers
* in this case, these drivers will not be included and the application code will
* be based on direct access to peripherals registers
*/
#ifdef _RTE_
#include "RTE_Components.h"
@@ -89,7 +89,7 @@ extern "C" {
*/
#define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F415_LIBRARY_VERSION_MIDDLE (0x00) /*!< [23:16] middle version */
#define __AT32F415_LIBRARY_VERSION_MINOR (0x03) /*!< [15:8] minor version */
#define __AT32F415_LIBRARY_VERSION_MINOR (0x04) /*!< [15:8] minor version */
#define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24) | \
(__AT32F415_LIBRARY_VERSION_MIDDLE << 16) | \
@@ -201,7 +201,7 @@ typedef enum IRQn
/** @addtogroup Exported_types
* @{
*/
*/
typedef int32_t INT32;
typedef int16_t INT16;
@@ -243,19 +243,19 @@ typedef __I uint16_t vuc16; /*!< read only */
typedef __I uint8_t vuc8; /*!< read only */
/**
* @brief flag status
* @brief flag status
*/
typedef enum {RESET = 0, SET = !RESET} flag_status;
typedef enum {RESET = 0, SET = !RESET} flag_status;
/**
* @brief confirm state
*/
typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
*/
typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
/**
* @brief error status
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
/**
* @}
@@ -311,7 +311,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
/* apb2 bus base address */
/* apb2 bus base address */
#define IOMUX_BASE (APB2PERIPH_BASE + 0x0000)
#define EXINT_BASE (APB2PERIPH_BASE + 0x0400)
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
@@ -327,7 +327,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
#define TMR10_BASE (APB2PERIPH_BASE + 0x5000)
#define TMR11_BASE (APB2PERIPH_BASE + 0x5400)
#define SDIO1_BASE (APB2PERIPH_BASE + 0x8000)
/* ahb bus base address */
/* ahb bus base address */
#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
#define DMA1_CHANNEL1_BASE (AHBPERIPH_BASE + 0x0008)
#define DMA1_CHANNEL2_BASE (AHBPERIPH_BASE + 0x001C)