ArteryTek/AT32F415_Firmware_Library
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update version to v2.0.4

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Artery-MCU
2022-04-11 19:32:28 +08:00
parent 07d7347ba4
commit ccd0f1e108
1470 changed files with 213761 additions and 13939 deletions
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40
libraries/cmsis/cm4/device_support/at32f415.h
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@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f415.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f415 header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -42,7 +42,7 @@ extern "C" {
/** @addtogroup AT32F415
* @{
*/
/** @addtogroup Library_configuration_section
* @{
*/
@@ -73,8 +73,8 @@ extern "C" {
#ifndef USE_STDPERIPH_DRIVER
/**
* @brief comment the line below if you will not use the peripherals drivers.
* in this case, these drivers will not be included and the application code will
* be based on direct access to peripherals registers
* in this case, these drivers will not be included and the application code will
* be based on direct access to peripherals registers
*/
#ifdef _RTE_
#include "RTE_Components.h"
@@ -89,7 +89,7 @@ extern "C" {
*/
#define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F415_LIBRARY_VERSION_MIDDLE (0x00) /*!< [23:16] middle version */
#define __AT32F415_LIBRARY_VERSION_MINOR (0x03) /*!< [15:8] minor version */
#define __AT32F415_LIBRARY_VERSION_MINOR (0x04) /*!< [15:8] minor version */
#define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24) | \
(__AT32F415_LIBRARY_VERSION_MIDDLE << 16) | \
@@ -201,7 +201,7 @@ typedef enum IRQn
/** @addtogroup Exported_types
* @{
*/
*/
typedef int32_t INT32;
typedef int16_t INT16;
@@ -243,19 +243,19 @@ typedef __I uint16_t vuc16; /*!< read only */
typedef __I uint8_t vuc8; /*!< read only */
/**
* @brief flag status
* @brief flag status
*/
typedef enum {RESET = 0, SET = !RESET} flag_status;
typedef enum {RESET = 0, SET = !RESET} flag_status;
/**
* @brief confirm state
*/
typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
*/
typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
/**
* @brief error status
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
/**
* @}
@@ -311,7 +311,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
/* apb2 bus base address */
/* apb2 bus base address */
#define IOMUX_BASE (APB2PERIPH_BASE + 0x0000)
#define EXINT_BASE (APB2PERIPH_BASE + 0x0400)
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
@@ -327,7 +327,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
#define TMR10_BASE (APB2PERIPH_BASE + 0x5000)
#define TMR11_BASE (APB2PERIPH_BASE + 0x5400)
#define SDIO1_BASE (APB2PERIPH_BASE + 0x8000)
/* ahb bus base address */
/* ahb bus base address */
#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
#define DMA1_CHANNEL1_BASE (AHBPERIPH_BASE + 0x0008)
#define DMA1_CHANNEL2_BASE (AHBPERIPH_BASE + 0x001C)

16
libraries/cmsis/cm4/device_support/at32f415_conf_template.h
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@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file at32f415_conf.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f415 config header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,7 +31,7 @@
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief in the following line adjust the value of high speed exernal crystal (hext)

6
libraries/cmsis/cm4/device_support/startup/gcc/linker/AT32F415x8_FLASH.ld
View File

@@ -22,7 +22,7 @@
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20007FFF; /* end of RAM */
_estack = 0x20008000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
@@ -134,12 +134,12 @@ SECTIONS
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(4);
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */

6
libraries/cmsis/cm4/device_support/startup/gcc/linker/AT32F415xB_FLASH.ld
View File

@@ -22,7 +22,7 @@
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20007FFF; /* end of RAM */
_estack = 0x20008000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
@@ -134,12 +134,12 @@ SECTIONS
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(4);
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */

6
libraries/cmsis/cm4/device_support/startup/gcc/linker/AT32F415xC_FLASH.ld
View File

@@ -22,7 +22,7 @@
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20007FFF; /* end of RAM */
_estack = 0x20008000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
@@ -134,12 +134,12 @@ SECTIONS
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(4);
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */

30
libraries/cmsis/cm4/device_support/startup/gcc/startup_at32f415.s
View File

@@ -1,8 +1,8 @@
/**
******************************************************************************
* @file startup_at32f415.s
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief at32f415xx devices vector table for gcc toolchain.
* this module performs:
* - set the initial sp
@@ -106,7 +106,7 @@ Infinite_Loop:
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
@@ -130,7 +130,7 @@ g_pfnVectors:
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDT_IRQHandler /* Window Watchdog Timer */
.word PVM_IRQHandler /* PVM through EXINT Line detect */
@@ -211,20 +211,20 @@ g_pfnVectors:
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
@@ -241,10 +241,10 @@ g_pfnVectors:
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDT_IRQHandler
.thumb_set WWDT_IRQHandler,Default_Handler
.thumb_set WWDT_IRQHandler,Default_Handler
.weak PVM_IRQHandler
.thumb_set PVM_IRQHandler,Default_Handler
@@ -268,7 +268,7 @@ g_pfnVectors:
.thumb_set EXINT1_IRQHandler,Default_Handler
.weak EXINT2_IRQHandler
.thumb_set EXINT2_IRQHandler,Default_Handler
.thumb_set EXINT2_IRQHandler,Default_Handler
.weak EXINT3_IRQHandler
.thumb_set EXINT3_IRQHandler,Default_Handler
@@ -286,7 +286,7 @@ g_pfnVectors:
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler

16
libraries/cmsis/cm4/device_support/startup/iar/startup_at32f415.s
View File

@@ -1,7 +1,7 @@
;**************************************************************************
;* @file startup_at32f415.s
;* @version v2.0.3
;* @date 2022-02-11
;* @version v2.0.4
;* @date 2022-04-02
;* @brief at32f415 startup file for IAR Systems
;**************************************************************************
;
@@ -280,15 +280,15 @@ ADC1_IRQHandler
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)

8
libraries/cmsis/cm4/device_support/startup/mdk/startup_at32f415.s
View File

@@ -1,7 +1,7 @@
;**************************************************************************
;* @file startup_at32f415.s
;* @version v2.0.3
;* @date 2022-02-11
;* @version v2.0.4
;* @date 2022-04-02
;* @brief at32f415 startup file for keil
;**************************************************************************
;
@@ -77,8 +77,8 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SE_IRQHandler ; CAN1 SE
DCD EXINT9_5_IRQHandler ; EXINT Line [9:5]
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Brake and TMR9

22
libraries/cmsis/cm4/device_support/system_at32f415.c
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file system_at32f415.c
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief contains all the functions for cmsis cortex-m4 system source file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -31,7 +31,7 @@
/** @addtogroup AT32F415_system
* @{
*/
#include "at32f415.h"
/** @addtogroup AT32F415_system_private_defines
@@ -81,7 +81,7 @@ void SystemInit (void)
/* wait sclk switch status */
while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
CRM->cfg = 0;
@@ -193,7 +193,7 @@ void system_core_clock_update(void)
pllrcsfreq = HEXT_VALUE;
}
}
system_core_clock = (pllrcsfreq * pll_ns) / (pll_ms * (0x1 << pll_fr));
system_core_clock = (uint32_t)(((uint64_t)pllrcsfreq * pll_ns) / (pll_ms * (0x1 << pll_fr)));
}
break;
default:
@@ -211,7 +211,7 @@ void system_core_clock_update(void)
/**
* @}
*/
/**
* @}
*/

22
libraries/cmsis/cm4/device_support/system_at32f415.h
View File

@@ -1,17 +1,17 @@
/**
**************************************************************************
* @file system_at32f415.h
* @version v2.0.3
* @date 2022-02-11
* @version v2.0.4
* @date 2022-04-02
* @brief cmsis cortex-m4 system header file.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -39,7 +39,7 @@ extern "C" {
* @{
*/
/** @defgroup AT32F415_system_clock_stable_definition
/** @defgroup AT32F415_system_clock_stable_definition
* @{
*/
@@ -50,7 +50,7 @@ extern "C" {
* @}
*/
/** @defgroup AT32F415_system_exported_variables
/** @defgroup AT32F415_system_exported_variables
* @{
*/
@@ -60,10 +60,10 @@ extern unsigned int system_core_clock; /*!< system clock frequency (core clock)
* @}
*/
/** @defgroup AT32F415_system_exported_functions
/** @defgroup AT32F415_system_exported_functions
* @{
*/
extern void SystemInit(void);
extern void system_core_clock_update(void);