mirror of
https://github.com/ArteryTek/AT32F415_Firmware_Library.git
synced 2026-05-21 01:12:20 +00:00
update version to v2.0.2
This commit is contained in:
Artery-MCU
@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_adc.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 adc header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_can.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 can header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -110,16 +110,21 @@ extern "C" {
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/**
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* @brief can flag clear operation macro definition val
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*/
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#define CAN_MSTS_EOIF_VAL ((uint32_t)0x00000004) /*!< eoif bit w1 */
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#define CAN_MSTS_QDZIF_VAL ((uint32_t)0x00000008) /*!< qdzif bit w1 */
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#define CAN_MSTS_EDZIF_VAL ((uint32_t)0x00000010) /*!< edzif bit w1 */
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#define CAN_TSTS_TM0TCF_VAL ((uint32_t)0x00000001) /*!< tm0tcf bit w1 */
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#define CAN_TSTS_TM1TCF_VAL ((uint32_t)0x00000100) /*!< tm1tcf bit w1 */
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#define CAN_TSTS_TM2TCF_VAL ((uint32_t)0x00010000) /*!< tm2tcf bit w1 */
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#define CAN_RF0_RF0FF_VAL ((uint32_t)0x00000008) /*!< rf0ff bit w1 */
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#define CAN_RF0_RF0OF_VAL ((uint32_t)0x00000010) /*!< rf0of bit w1 */
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#define CAN_RF1_RF1FF_VAL ((uint32_t)0x00000008) /*!< rf1ff bit w1 */
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#define CAN_RF1_RF1OF_VAL ((uint32_t)0x00000010) /*!< rf1of bit w1 */
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#define CAN_MSTS_EOIF_VAL ((uint32_t)0x00000004) /*!< eoif bit value, it clear by writing 1 */
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#define CAN_MSTS_QDZIF_VAL ((uint32_t)0x00000008) /*!< qdzif bit value, it clear by writing 1 */
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#define CAN_MSTS_EDZIF_VAL ((uint32_t)0x00000010) /*!< edzif bit value, it clear by writing 1 */
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#define CAN_TSTS_TM0TCF_VAL ((uint32_t)0x00000001) /*!< tm0tcf bit value, it clear by writing 1 */
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#define CAN_TSTS_TM1TCF_VAL ((uint32_t)0x00000100) /*!< tm1tcf bit value, it clear by writing 1 */
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#define CAN_TSTS_TM2TCF_VAL ((uint32_t)0x00010000) /*!< tm2tcf bit value, it clear by writing 1 */
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#define CAN_TSTS_TM0CT_VAL ((uint32_t)0x00000080) /*!< tm0ct bit value, it clear by writing 1 */
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#define CAN_TSTS_TM1CT_VAL ((uint32_t)0x00008000) /*!< tm1ct bit value, it clear by writing 1 */
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#define CAN_TSTS_TM2CT_VAL ((uint32_t)0x00800000) /*!< tm2ct bit value, it clear by writing 1 */
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#define CAN_RF0_RF0FF_VAL ((uint32_t)0x00000008) /*!< rf0ff bit value, it clear by writing 1 */
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#define CAN_RF0_RF0OF_VAL ((uint32_t)0x00000010) /*!< rf0of bit value, it clear by writing 1 */
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#define CAN_RF0_RF0R_VAL ((uint32_t)0x00000020) /*!< rf0r bit value, it clear by writing 1 */
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#define CAN_RF1_RF1FF_VAL ((uint32_t)0x00000008) /*!< rf1ff bit value, it clear by writing 1 */
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#define CAN_RF1_RF1OF_VAL ((uint32_t)0x00000010) /*!< rf1of bit value, it clear by writing 1 */
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#define CAN_RF1_RF1R_VAL ((uint32_t)0x00000020) /*!< rf1r bit value, it clear by writing 1 */
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/** @defgroup CAN_exported_types
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* @{
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_cmp.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 cmp header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_crc.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 crc header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_crm.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 crm header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_debug.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 debug header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -133,7 +133,7 @@ typedef struct
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* @}
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*/
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#define DEBUG ((debug_type *) DEBUG_BASE)
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#define DEBUGMCU ((debug_type *) DEBUG_BASE)
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/** @defgroup DEBUG_exported_functions
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* @{
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69
libraries/drivers/inc/at32f415_def.h
Normal file
69
libraries/drivers/inc/at32f415_def.h
Normal file
@@ -0,0 +1,69 @@
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/**
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**************************************************************************
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* @file at32f415_def.h
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 macros header file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F415_DEF_H
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#define __AT32F415_DEF_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* gnu compiler */
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#if defined (__GNUC__)
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#ifndef ALIGNED_HEAD
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#define ALIGNED_HEAD
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#endif
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#ifndef ALIGNED_TAIL
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#define ALIGNED_TAIL __attribute__ ((aligned (4)))
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#endif
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#endif
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/* arm compiler */
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#if defined (__CC_ARM)
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#ifndef ALIGNED_HEAD
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#define ALIGNED_HEAD __align(4)
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#endif
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#ifndef ALIGNED_TAIL
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#define ALIGNED_TAIL
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#endif
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#endif
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/* iar compiler */
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#if defined (__ICCARM__)
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#ifndef ALIGNED_HEAD
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#define ALIGNED_HEAD
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#endif
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#ifndef ALIGNED_TAIL
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#define ALIGNED_TAIL
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#endif
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_dma.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 dma header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_ertc.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 ertc header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_exint.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 exint header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_flash.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 flash header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_gpio.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 gpio header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -423,7 +423,7 @@ typedef struct
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};
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/**
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* @brief gpio wcr register, offset:0x10
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* @brief gpio scr register, offset:0x10
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*/
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union
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{
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_i2c.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 i2c header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_misc.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 misc header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -64,11 +64,11 @@ extern "C" {
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*/
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typedef enum
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{
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NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x700), /*!< 0 bits for preemption priority, 4 bits for subpriority */
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NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x600), /*!< 1 bits for preemption priority, 3 bits for subpriority */
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NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x500), /*!< 2 bits for preemption priority, 2 bits for subpriority */
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NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x400), /*!< 3 bits for preemption priority, 1 bits for subpriority */
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NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x300) /*!< 4 bits for preemption priority, 0 bits for subpriority */
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NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
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NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
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NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
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NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
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NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
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} nvic_priority_group_type;
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/**
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_pwc.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 pwc header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -57,6 +57,11 @@ extern "C" {
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* @}
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*/
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/**
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* @brief pwc wakeup pin num definition
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*/
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#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */
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/** @defgroup PWC_exported_types
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* @{
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*/
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@@ -159,7 +164,7 @@ void pwc_reset(void);
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void pwc_battery_powered_domain_access(confirm_state new_state);
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void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
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void pwc_power_voltage_monitor_enable(confirm_state new_state);
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void pwc_wakeup_pin_enable(confirm_state new_state);
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void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
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void pwc_flag_clear(uint32_t pwc_flag);
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flag_status pwc_flag_get(uint32_t pwc_flag);
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void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_sdio.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 sdio header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_spi.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 spi header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -122,8 +122,8 @@ typedef enum
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*/
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typedef enum
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{
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SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is software mode */
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SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is hardware mode */
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SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is hardware mode */
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SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is software mode */
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} spi_cs_mode_type;
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/**
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_tmr.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 tmr header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_usart.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 usart header file
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**************************************************************************
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* Copyright notice & Disclaimer
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_usb.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 usb header file
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**************************************************************************
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||||
* Copyright notice & Disclaimer
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||||
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_wdt.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 wdt header file
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**************************************************************************
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||||
* Copyright notice & Disclaimer
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||||
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@@ -1,8 +1,8 @@
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/**
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**************************************************************************
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* @file at32f415_wwdt.h
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* @version v2.0.0
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* @date 2021-11-26
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* @version v2.0.2
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* @date 2021-12-31
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* @brief at32f415 wwdt header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
|
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