mirror of
https://github.com/ArteryTek/AT32F415_Firmware_Library.git
synced 2026-05-21 01:12:20 +00:00
update version to v2.1.7
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@@ -128,7 +128,7 @@ extern "C" {
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*/
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#define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
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#define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */
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#define __AT32F415_LIBRARY_VERSION_MINOR (0x06) /*!< [15:8] minor version */
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#define __AT32F415_LIBRARY_VERSION_MINOR (0x07) /*!< [15:8] minor version */
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#define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24) | \
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(__AT32F415_LIBRARY_VERSION_MIDDLE << 16) | \
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@@ -141,14 +141,14 @@ void system_core_clock_update(void)
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pll_mult_h = CRM->cfg_bit.pllmult_h;
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/* process high bits */
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if((pll_mult_h != 0U) || (pll_mult == 15U)){
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pll_mult += ((16U * pll_mult_h) + 1U);
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pll_mult += ((16U * pll_mult_h) + 1U);
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}
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else
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{
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pll_mult += 2U;
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pll_mult += 2U;
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}
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if (pll_clock_source == 0x00)
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if(pll_clock_source == 0x00)
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{
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/* hick divided by 2 selected as pll clock entry */
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system_core_clock = (HICK_VALUE >> 1) * pll_mult;
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@@ -156,7 +156,7 @@ void system_core_clock_update(void)
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else
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{
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/* hext selected as pll clock entry */
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if (CRM->cfg_bit.pllhextdiv != RESET)
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if(CRM->cfg_bit.pllhextdiv != RESET)
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{
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/* hext clock divided by 2 */
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system_core_clock = (HEXT_VALUE / 2) * pll_mult;
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@@ -173,7 +173,7 @@ void system_core_clock_update(void)
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pll_ns = CRM->pll_bit.pllns;
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pll_fr = CRM->pll_bit.pllfr;
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if (pll_clock_source == 0x00)
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if(pll_clock_source == 0x00)
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{
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/* hick divided by 2 selected as pll clock entry */
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pllrcsfreq = (HICK_VALUE >> 1);
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@@ -181,7 +181,7 @@ void system_core_clock_update(void)
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else
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{
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/* hext selected as pll clock entry */
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if (CRM->cfg_bit.pllhextdiv != RESET)
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if(CRM->cfg_bit.pllhextdiv != RESET)
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{
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/* hext clock divided by 2 */
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pllrcsfreq = (HEXT_VALUE / 2);
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