ArteryTek/AT32F415_Firmware_Library
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update version to v2.1.2

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Artery-MCU
2024-01-25 10:08:14 +08:00
parent 9d554c6b91
commit 0a93017e07
105 changed files with 3447 additions and 242 deletions
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6
libraries/drivers/inc/at32f415_crm.h
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@@ -133,7 +133,7 @@ typedef enum
CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 21), /*!< i2c1 periph clock */
CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 22), /*!< i2c2 periph clock */
CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 25), /*!< can1 periph clock */
CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28), /*!< pwc periph clock */
CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28) /*!< pwc periph clock */
} crm_periph_clock_type;
@@ -174,7 +174,7 @@ typedef enum
CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< i2c1 periph reset */
CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< i2c2 periph reset */
CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x10, 25), /*!< can1 periph reset */
CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28), /*!< pwc periph reset */
CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28) /*!< pwc periph reset */
} crm_periph_reset_type;
@@ -268,7 +268,7 @@ typedef enum
CRM_PLL_FREF_8M = 2, /*!< pll refrence clock between 7.8125 mhz and 8.33 mhz */
CRM_PLL_FREF_12M = 3, /*!< pll refrence clock between 8.33 mhz and 12.5 mhz */
CRM_PLL_FREF_16M = 4, /*!< pll refrence clock between 15.625 mhz and 20.83 mhz */
CRM_PLL_FREF_25M = 5, /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */
CRM_PLL_FREF_25M = 5 /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */
} crm_pll_fref_type;
/**

1
libraries/drivers/inc/at32f415_dma.h
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@@ -498,6 +498,7 @@ void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number);
uint16_t dma_data_number_get(dma_channel_type* dmax_channely);
void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state);
flag_status dma_flag_get(uint32_t dmax_flag);
flag_status dma_interrupt_flag_get(uint32_t dmax_flag);
void dma_flag_clear(uint32_t dmax_flag);